JPH0447848B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an arithmetic device, and more specifically, to an arithmetic device that uses a real-value representation method based on double exponential division. , then the mathematically significant operation result for it is
It relates to a device that responds quickly.

[Background of the invention]

In the prior art, real value representation methods based on double exponential division are known.

Information Processing Society of Japan Transactions Vol. 22, No. 6, ``Data Length Independent Real Number Representation Method Based on Double Exponential Split'' is a real number representation method for data processing devices based on the binary system, that is, based on double exponential splitting. A real numerical representation method is proposed. This representation is format independent of the length of the data. It has features such as easy precision conversion, a sufficiently wide range of numbers that can be expressed, and virtually no overflow.

Information Processing Society of Japan Transactions Vol. 24, No. 2, ``Data Length-Independent Real Value Representation Method Based on Double Exponential Split''
The above real number representation method is improved, and non-numbers and their four arithmetic operations are defined.

With reference to FIG. 1, an improved real value representation method based on double exponential division will be described. In the following, 2 ⁿ will be expressed as exp2(n) to avoid misunderstanding.

Figure 1 shows the structure of the real numerical representation method. The representation method consists of a sign part 11, an exponent part 12, and a coefficient part 13. The exponent part 12 further includes a main exponent part 121
and a sub-exponent part 122. The code part 11 is 1
Bit length is fixed, but other bits are variable length.

Now, let x be the number we want to represent. This is expressed as x=exp2(e)×f (1) using two numbers, an exponent e and a mantissa f. However, e is an integer, and in order to uniquely represent the value, 1≦f<2 or -2≦f<-1 (2).

First, if the mantissa f is negative, "1" is set as the sign part 11, and otherwise, "0" is set as the sign part 11.

Next, due to the constraint of equation (2), the binary representation of the part obtained by removing the sign from the mantissa f is f=1.f ₁ f ₂ ... f _j ... (3). At this time, let "f ₁ f ₂ . . . f _{j .} . ." be the bit pattern of the mantissa part 13.

Also, if the exponent e is m binary digits including its sign (m≧0, but the equal sign is e=0 or e=-1
The integer e is expressed as follows.

When x>0, e≧0 1...10e _n-1 ...e _{2 e} 1 When x>0, e<0 0...01e _n-1 ...e _{2 e 1 When} x<0, e≧0 0 …01e _n-1 …e ₂ e ₁ When x<0, e<0 1…10e _n-1 …e ₂ e ₁ …(4) Here “e _n-1 …e ₂ e ₁ ” is the exponent e is expressed in m binary digits, with the most significant digit removed. Moreover, the upper line "" represents an operation of reversing "1" and "0" of each digit. Further, the upper digits "1...1" and "0...0" indicate that the exponent e is represented by m binary digits. It is a string of m+1 digits of "1" or "0". These "1" or "0"
``0'' or ``1'' is placed after the ``0'' or ``1'' for delimitation. At this time, the string of "1..." or "0..." in equation (4) and the "0" or "1" for delimitation are used as the bit pattern of the main exponent part 121.
Also, the remaining “e _n-1 …e ₂ e ₁ ” or “ _n-1 … _{2 1} ”
Let be the bit pattern of the sub-exponent part 122.

This concludes the explanation of the real number representation method based on double exponential division.

Next, with reference to FIG. 2, an explanation will be given of the calculation procedure using the real number expression method based on double exponential division.

As an example, the addition procedure is shown in FIG.

When an operand is given, it is first separated 21 into an exponent and a mantissa. As mentioned above, since the exponent part has a variable length, the length of the exponent part is determined based on the bit pattern of the main exponent part, and the operand is separated into its exponent part and mantissa part.

Below, the exponent matching 22 performed to add the mantissa parts of the operands, the addition 23 of the mantissa parts, and the mantissa normalization 24 to satisfy the constraint of equation (2) are the steps of addition using the normal floating point representation method. is the same as

Finally, for additions using real-valued representations based on double exponential division, the exponent and mantissa parts of the result are combined 25. To do this, first select a bit pattern for the main exponent part that is appropriate for the exponent part, combine it with the sub-exponent part, and finally decide the length of the mantissa part so that the overall result is a fixed length. Join. This is the result.

Regarding other four arithmetic operations, separation of exponent and mantissa 2
The operations for connection 1 and connection 25 are similar.

This concludes the explanation of the calculation procedure using the real number representation method based on double exponential division.

Next, with reference to FIGS. 3 to 6, the representation method of non-numbers in this real number representation method and its four arithmetic operations will be explained.

In this real number representation method, six types of non-numbers are defined. They are shown below.

∞ (unsigned infinity) −∞ (negative infinity) -0 (negative infinitesimal) 0 (zero or unsigned infinitesimal) +0 (positive infinitesimal) +∞ (positive infinity) The bit pattern is shown below.

∞:10…00 −∞:10…01 −0:11…11 0:00…00 +0:00…01 +∞:01…11…(5) All of these are defined as natural sequences of numerical expressions. has been done.

Furthermore, definitions of four arithmetic operations involving non-numbers are shown in FIGS. 3 to 6. In the figure, x ₁ and x ₂ represent the absolute values of the first and second operands, respectively, and r represents the absolute value of the operation result without considering non-numbers. Also, what is NS?
Indicates that the calculation result has no mathematical significance.

Figure 3 defines addition. In the figure, 31 is the first operand (addend), 32 is the second operand (addend)
shows. According to Figure 3, for example, “+0” is changed to “+0”.
It can be seen that adding "0" must result in "+0", or that the operation of adding "-0" to "+0" is meaningless.

Figure 4 defines the operations. In the figure, 41 is the first operand (minuend), and 42 is the second operand (minuend).
shows.

Figure 5 defines multiplication. In the figure, 51 is the first operand (multiplicand), and 52 is the second operand (multiplier).
shows.

Figure 6 defines division. In the figure, 61 is the first operand (dividend), 62 is the second operand (divisor)
shows.

This concludes the explanation of how to represent non-numbers and its four arithmetic operations.

In conventional arithmetic procedures that do not take into account non-numbers, the arithmetic results may not always be obtained as defined in Figures 3 to 6, so in that case, the operands are It is necessary to check whether the value is not a non-number, and if it is a non-number, to process it by software, or to process it by software as an exception due to an interrupt from an arithmetic unit. For this reason, there was a drawback that it took a long time to process the calculations.

[Object of the Invention] The object of the present invention is to add some devices to an arithmetic device using a real number representation method based on double exponential division, so that at least one operand is a non-number in the arithmetic device. To speed up the calculation speed of an arithmetic unit by eliminating software processing when performing calculations for cases, and by utilizing the fact that the calculation results can be known even without performing the calculations.

[Summary of the invention]

One of the features of the real number representation method based on double exponential division
One is the so-called non-numbers (0, +0, -0, ∞, +∞, -
∞) can be expressed as a natural continuation from the usual representation of numerical values. Therefore, in an arithmetic unit using this representation method, even if the operand is a non-number or the result of an operation is a non-number, exceptional handling cannot be used as long as the result does not lose mathematical significance. There is a need to speed up calculations by allowing them to be executed naturally without any problems.

In order to meet the above requirements, the present invention adds a device for processing operations involving non-numbers to a conventional arithmetic device.

Upon receiving an arithmetic execution command from an instruction processing device, the device of the present invention quickly detects a non-number operand in parallel with processing by a conventional arithmetic device.
When a non-number operand is confirmed, processing by a conventional arithmetic unit is stopped, and an appropriate arithmetic result is output without requiring software processing such as an interrupt. Moreover, in this case, the result of the operation is either a non-number or an operand,
Since there is no need to execute the calculation, the calculation ends sooner than usual.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 7 to 11. FIG. 7 shows the interface between the instruction processing unit and the arithmetic unit. FIG. 8 shows the configuration of the arithmetic device. 9 and 10 show the operation of the output selection circuit of the arithmetic device. FIG. 11 shows a timing diagram of the main parts of the arithmetic device.

In the timing diagram, the reference time is set as t ₀ for convenience of explanation. Furthermore, considering unit time, for a natural number n, the time n units of time after the reference time t ₀ is determined as t _o .

First, the interface between the instruction processing device and the arithmetic device will be explained with reference to FIG. In order for the instruction processing device 71 to issue a request to the arithmetic unit 72 to execute an operation, first, “1” is applied to the request signal line 711. Next, specify the type of operation that you want the order signal line 713 to perform on the first operand signal line 715.
and the second operand signal line 71.
Apply the second operand to 6. If the calculation result does not lose mathematical significance, first apply "1" to the data sending signal line 721, and then apply the calculation result to the output data signal line 725 to instruct the calculation unit 72. It responds to the processing device 71.
If the calculation result loses mathematical significance, the calculation unit 72 responds to the instruction processing unit 71 by applying "1" to the interrupt signal line 729.

Usually, a request signal line 711 from the instruction processing device 71 to the arithmetic device 72, and a data sending signal line 721 from the arithmetic device 72 to the instruction processing device 71,
“0” must be applied to the interrupt signal line 729.

This concludes the explanation of the interface between the instruction processing device and the arithmetic device.

Next, details of the arithmetic device of this embodiment will be explained with reference to FIGS. 8 to 11.

Although this embodiment shows an arithmetic device that performs only addition, it is easy to see that it can be extended to any other operations, such as subtraction, multiplication, division, etc. Furthermore, the length of the numerical data to be handled is not particularly determined. It is possible to handle arbitrary fixed length data.

First, an overview of the configuration of the arithmetic device of the embodiment will be explained with reference to FIG.

The order register 806 is for storing the type of operation to be executed. First operand register 801 and second operand register 802
are for storing the first and second operands, respectively.

The part 810 that performs normal addition correctly outputs the sum of the numerical values of both operands when both the first operand and the second operand are not non-numbers using a real value representation method based on double exponential division.

The parts newly added according to the present invention are a part 840 for detecting a non-number and selecting an output, a non-number generating circuit 860, and a selector 870. The portion 840 that detects a non-number and selects an output includes a first operand non-number determination circuit 841, a second operand non-number determination circuit 842, and an output selection circuit 845. The non-number judgment circuit 841 for the first operand and the non-number judgment circuit 842 for the second operand determine the types of the first operand and the second operand, respectively. Find out what is. The output selection circuit 845 is
Appropriate outputs are selected according to the types of the first and second operands. Non-number generation circuit 860
is the six types of non-numbers defined by the real number representation method based on double exponential division, namely +0, 0, -0, +
Generates bit patterns of ∞, ∞, and -∞. The selector 870 uses the output selection circuit 845 to select and output one of the output of the portion 810 that performs normal addition, the first operand, the second operand, and six types of non-numbers from the non-number generation circuit 860.

The arithmetic control circuit 890 issues control signals to various parts within the arithmetic device and controls the operation of the arithmetic device.

This concludes the explanation of the configuration of the arithmetic device of the embodiment.

Next, details of the operation of the arithmetic device of the embodiment will be explained with reference to FIGS. 8 to 11.

In the initial state, the request signal line 711 from the instruction processing device, the data sending signal line 849 from the part 840 that detects a non-number and selects the output, the data sending signal line 891 from the arithmetic control circuit, and the data sending signal line 891 to the instruction processing device. “0” is applied to the data sending signal line 721 and the interrupt signal line 729. Furthermore, a non-number detection signal line 843-1 from the non-number judgment circuit 841 of the first operand, a non-number detection signal line 844-1 from the non-number judgment circuit 842 of the second operand, and a non-number detection signal line 844-1 are connected to detect and output a non-number. “0” is applied to the non-number detection signal line 848 from the selection portion 840. Furthermore, a code "0" indicating that the output of the portion 810 that performs normal addition is selected is applied to the output selection signal 846 from the output selection circuit 845.

Now, as described in the interface between the instruction processing device and the arithmetic device, first, "1" is applied to the request signal line 711 in FIG. 8, and a request to execute the arithmetic operation is issued. This time is the reference time,
Let it be t ₀ as shown in Figure 11. Request signal line 7
The signal on 11 reaches the arithmetic control circuit 890.

At time t ₁ , which is a unit time after time t ₀ , a code indicating the type of operation is transmitted from the instruction processing device to the order signal line 713 in FIG.
Numerical data of the first operand and the second operand are applied to the signal line 15 and the second operand signal line 716, respectively, in accordance with the real value expression method based on double exponential division. The order signal line 713 is the order register 8
05, the first operand signal line is connected to the first operand register 801, and the second operand signal line is connected to the second operand register 801.
Operand register 802 is reached.

The arithmetic control circuit 890 that receives the arithmetic execution request signal on the request signal line 711 registers the order register 805 and the first operand register 8 at time _t2 .
01, issues a latch request signal to the second operand register 802; Order register 805 and first operand register 80 that received the latch request signal
1, the second operand register 802 is connected to the order signal line 71 after time _t2 as shown in FIG.
3. Store information on the first operand signal 715 and second operand signal 716, respectively, and apply the information to the order signal line 806, first operand signal line 803, and second operand signal line 804 inside the arithmetic device. The order signal line 806 reaches an output selection circuit 845 in a portion 840 that detects a non-number and selects an output, and an arithmetic control circuit 890. 1st
The operand signal line 803 is connected to a circuit 811 that separates the exponent part and mantissa part of the first operand in a part 810 that performs normal addition, and a circuit 811 that separates the exponent part and mantissa part of the first operand in a part 810 that performs normal addition, and a circuit 811 that separates the exponent part and mantissa part of the first operand in a part 840 that detects a non-number and selects an output. The non-number determination circuit 841 and the selector 870 are reached. The second operand signal line 804 is connected to a circuit 812 in a section 810 that performs normal addition that separates the exponent part and mantissa part of the second operand, and a circuit 812 in a section 840 that detects a non-number and selects an output. 2-operand non-number determination circuit 842 and selector 87
reaches 0.

From this, depending on the type of operation on the order signal line 806, the first operand and the second operand on the first operand signal line 803 and the second operand signal line 804,
and a portion 840 for detecting a non-number and selecting an output, each process is started in parallel.

First, the operation of the section 810 that performs normal addition will be explained.

The arithmetic control circuit 890 issues a control signal to the section 810 that performs normal addition to separate the exponent and mantissa parts at time t ₂ and to cause the exponents to match at time t ₃ . At time _t4 , the arithmetic control circuit 890
examines the non-number detect signal line 848 from the portion 840 that detects the non-number and selects the output. When the signal on the non-number detection signal line 848 is "0", in order to cause the part 810 that performs normal addition to continue processing, the mantissa is added at time _t4 , and the mantissa is added at time _t5 . A control signal is issued to normalize the exponent part and combine the mantissa part at time _t6 . When the non-number detection signal line 848 is "0", the processing in the section 810 that performs normal addition is stopped, and the arithmetic control circuit 890 does not issue any control signals thereafter.

Arithmetic control circuit 890 also applies a signal to data sending signal line 891. Normally, "1" is applied to the signal line 891. As mentioned above, time t ₄
Then, the arithmetic control circuit 890 checks the non-number detection signal line 848 from the part 840 that detects a non-number and selects an output. The signal on the non-number detection signal line 848 is “0”
, the arithmetic control circuit 890 _determines the time t
Then, “1” is applied to the data sending signal line 891. The signal line 891 reaches the OR circuit 895, and the 11th
As shown in the figure, at time _t7 , "1" is applied to the data sending signal line 721 to the instruction processing device.

A part 810 that performs normal addition first includes a circuit 811 that separates the exponent part and mantissa part of the first operand, and a circuit 811 that separates the exponent part and mantissa part of the second operand according to a control signal issued from the arithmetic control circuit 890. The circuit 812 separates the numerical data on the first operand signal line 803 and the second operand signal line 804 into an exponent part and a mantissa part, and as shown in _FIG. , signal line 8
13 is the exponent part of the first operand, and the signal line 814 is
The mantissa part of the first operand is applied to the signal line 815, the exponent part of the second operand is applied to the signal line 816, and the mantissa part of the second operand is applied to the signal line 816. The signal line 813 is a circuit 817 that increases the exponent part of the first operand.
The signal line 814 is connected to a shift circuit 818 for the mantissa part of the first operand, the signal line 815 is connected to a circuit 819 for increasing the exponent part of the second operand, and the signal line 815 is connected to a circuit 819 for increasing the exponent part of the second operand.
16 is a shift circuit 82 for the mantissa part of the second operand.
reaches 0.

Next, the section 810 that performs normal addition performs exponent matching. The exponent part of the first operand on the signal line 813 and the exponent part of the second operand on the signal line 815 are compared, and the larger value is adjusted to the other value. To this end, the circuit 817 that increases the exponent part of the first operand and the circuit 819 that increases the exponent part of the second operand increase the exponent part with the smaller value by the smaller amount. At the same time, the mantissa part paired with the exponent part whose value has been increased is divided by 2 by the amount by which the exponent part has been increased. That is, the shift circuit 818 for the mantissa part of the first operand
or a shift circuit 820 for the mantissa part of the second operand.
, arithmetic shifts the mantissa to the right. By the above index matching, at time t ₄ , as shown in Figure 11,
The exponent part matched with the signal line 821 is connected to the signal line 82
The mantissa part of the first operand is applied to signal line 824, and the mantissa part of the second operand is applied to signal line 824. signal line 8
21 reaches a circuit 829 that increases or decreases the exponent part for normalizing the mantissa part, and signal lines 822 and 824 reach a circuit 826 that adds the values of the mantissa part.

Next, add the mantissa parts. Addition circuit 826
adds the mantissa of the first operand on signal line 822 and the mantissa of the second operand on signal line 824 as fixed-point numbers, and as shown in _FIG . is applied to signal line 828. The signal line 828 reaches a shift circuit 830 for normalization of the mantissa.

Next, the mantissa is normalized. signal line 828
The shift circuit 830 arithmetic shifts the mantissa to the right or left so that the value of the upper mantissa becomes 1 or more and less than 2, or -2 or more and less than -1. At the same time, the exponent increment or decrement circuit 829 increments or decrements the exponent as the mantissa is shifted to the right or left. With the above normalization of the mantissa, at time t ₆ , as shown in Figure 11,
An exponent part is applied to a signal line 831, and a normalized mantissa part is applied to a signal line 832. A signal line 831 and a signal line 832 are connected to a circuit 8 that connects an exponent part and a mantissa part.
Reach 33.

Next, the exponent part and the mantissa part are combined. A circuit 833 that combines the exponent part and the mantissa part generates a bit pattern that expresses the value of the exponent part using a real number expression method based on double exponential division, using the exponent part on the signal line 831, and outputs a signal. By combining the mantissa parts on line 832, at time t ₇ as shown in FIG.
The calculation result of a fixed length as a whole is applied to the normal calculation result signal line 834. Signal line 834 reaches selector 870.

As described above, the operation started at time _t2 in FIG. 11 ends at time _t7 , and the normal operation result signal line 8
The result of the calculation is applied on 34.

This completes the explanation of the operation of the section 810 that performs normal addition.

Next, the operation of performing operations involving non-numbers will be explained.

At time _t2 , the arithmetic control circuit 890 issues a control signal for causing the first operand non-number determining circuit 841 and the second operand non-number determining circuit 842 to determine the type of operand.

To determine the type of operand, first, the bit pattern of each of the six defined non-numbers, +0, 0, -0, +∞, ∞, and -∞, is compared with the bit pattern of the operand. If the bit pattern of an operand matches the bit pattern of a non-number, it is known that the operand is a non-number.
Furthermore, if the operand is not a non-number, the leftmost bit of the bit pattern is checked, and if it is ``0'' it is a positive number, and if it is ``1'' it is a negative number.
These determinations can be made in parallel.

The non-number determination circuit 841 for the first operand
The type of numerical value on the operand signal line 803, that is, whether it is a non-number or not, positive or negative, and if it is a non-number, the type is checked, and three signals are outputted corresponding to each. At time t ₂ , the non-number determination circuit 841 of the first operand receives a signal issued from the arithmetic control circuit 890 and outputs three signals at time t ₃ after a unit time. That is, the first operand signal line 8
If the data on 03 is a non-number, enter "1",
Otherwise, set "0" to signal line 843-1.
to be applied. In addition, the first operand signal line 803
If the above data is a negative number, "1" is applied to the signal line 843-2, otherwise "0" is applied to the signal line 843-2. Furthermore, if the data on the first operand signal line 803 is a non-number, its type (+0,
0, -0, +∞, ∞, -∞) is applied to the signal line 843-3. The signal line 843-1 is
It reaches OR circuit 847. Signal line 843-1 also reaches output selection circuit 845 along with signal line 843-2 and signal line 843-3.

The non-number determination circuit 842 for the second operand
Similar to the operand non-number determination circuit, the type of numerical value on the second operand signal line 804 is checked. The non-number determination circuit 842 of the second operand receives the signal issued from the arithmetic control circuit 890 at time t ₂ and outputs three signals at time t ₃ after a unit time. That is, if the data on the second operand signal line 804 is a non-number, "1" is applied to the signal line 844-1, otherwise "0" is applied to the signal line 844-1, and if the data is a negative number, "1" is applied to the signal line 844-1. If so, apply "1" to the signal line 844-2, otherwise apply "0" to the signal line 844-2,
Furthermore, if the data is a non-number, a code representing its type (+0, 0, -0, +∞, ∞, -∞) is applied to the signal line 844-3. Signal line 844-
1 reaches the OR circuit 847. Signal line 844-1
Also, signal line 844-2 and signal line 844-3
At the same time, the output selection circuit 845 is reached.

The OR circuit 847 outputs "0" when both the signals on the signal line 843-1 and the signal line 844-1 are "0", that is, the first operand and the second operand are not non-numbers; otherwise, That is, when at least one of the first operand and the second operand is a non-number, "1" is applied to the non-number detection signal line 848. Non-number detection signal line 848
reaches the arithmetic control circuit 890.

At this time, that is, at time _t3 , the arithmetic control circuit issues a control signal to the part 810 that performs normal addition to perform index matching.
In response to the "1" signal on the non-number detection signal line 848, the arithmetic control circuit 890 no longer issues any control signal after time _t4 . Therefore, in this case, the section 810 that performs normal addition stops performing operations.

The output selection circuit 845 connects the signal lines 843-1 to 84 from the non-number determination circuit 841 of the first operand.
3-3, and the signals on the signal lines 844-1 to 844-3 from the non-number determination circuit 842 of the second operand, that is, the output selection signal line according to the types of the first operand and the second operand. 846
Apply the code to select the output to. Signal line 846 reaches selector 870 and selector 87
0 is the normal operation result signal line 834, the first operand signal line 803, the second operand signal line 804,
and non-number data signal line 861 to be selected. A code "0" is normally applied to the signal line 846, which indicates the normal operation result signal line 834 from the section 810 that performs normal addition.
Specify to select.

The output selection circuit 845 includes a signal line 843-1 indicating whether the first operand is a non-number, a signal line 843-2 indicating whether the first operand is a positive number or a negative number, and a signal line 843 indicating the type of the first operand if it is a non-number. -3, and a signal line 844-1 indicating whether the second operand is a non-number, a signal line 844-2 indicating whether it is a positive number or a negative number, and a signal line 844-3 indicating the type of the second operand if it is a non-number. A code for selecting an appropriate output is generated according to the type of each of the above signals, that is, the first operand and the second operand, and the output selection signal line 846 is generated at time _t4 as shown in FIG. Send to. An example of output selection for addition in this embodiment is shown in the ninth section.
As shown in the figure.

FIG. 9 shows what is output according to the type 91 of the first operand and the type 92 of the second operand. In the figure, "+X" and "-X" respectively indicate positive or negative non-number operands, such as "+0", "0", "-0", "+∞", "∞",
“-
∞” indicates a non-number. Moreover, "R" is a normal operation result signal line 83 from the part 810 that performs normal addition.
4 is selected, and "OP1" and "OP2" are
the first operand signal line 803 or the second operand signal line, respectively.
Indicates that the operand signal line 804 is selected.
Further, "I" indicates that the operation based on the combination of operands has no mathematical meaning. In this case, no output selection is performed.

The output selection can also be made as shown in FIG. 10 instead of as shown in FIG. According to Figure 10,
A non-number generating circuit 860, which will be described later, becomes unnecessary. This takes advantage of the property that in the case of addition, even if a non-number must be output as a result, the non-number matches at least one of the first operand or the second operand. In the diagram, “OP1/
OP2'' indicates that either the first operand signal line 803 or the second operand signal line 804 is selected.

Output selection circuit 845 also applies signals to data sending signal line 849 and interrupt signal line 729. Normally, "0" is applied to these. If at least one of the first operand and the second operand is a non-number and the operation result has mathematical significance, that is, in FIG. 9 or 10, "OP1", "OP2", "+0", "0" ”, “-0”, “+
∞", "∞", or "-∞" as the output, "1" is applied to the data sending signal line 849 at time _t4 . The signal line 849 reaches the OR circuit 895, and as shown in FIG. 11, at time _t4 , "1" is applied to the data sending signal line 721 to the instruction processing device. In addition, when both the first operand and the second operand are non-numbers and the result of the operation based on their combination has no mathematical significance, that is, when it is indicated as "I" in Figure 9 or Figure 10, is time t ₄
Then, "1" is applied to the interrupt signal line 729 to the instruction processing device.

The non-number generating circuit 860 internally generates six types of non-numbers,
In other words, each bit pattern of +0, 0, -0, +∞, ∞, -∞ is memorized, and these 6 bit patterns are always stored.
A different type of non-number bit pattern is applied to the non-number data signal line 861. Signal line 861 reaches selector 870.

The selector 870 selects the portion 8 that performs normal addition according to the output selection signal on the output selection signal line 846.
10, the normal operation result signal line 834, the first operand signal line 803, and the second operand signal line 80
4, and the non-number data signal line 861 from the non-number generation circuit 860, and applies the selected data to the output data signal line 725 to the instruction processing device.

If both the first operand and the second operand are not non-numbers, the output selection signal line 846
A code "0" indicating that the normal calculation result signal line 834 is selected continues to be applied. in this case,
As shown in FIG. 11, at time _t7 , the result of the addition is applied to the normal operation result signal line 834. As shown in FIG. 11, selector 870 selects at time _t8 ,
The data on the normal operation result signal line 834 is applied to the output data signal line 725.

If at least one of the first operand or the second operand is a non-number and the result of the operation has mathematical significance, at time _t4 , as shown in FIG.
A code is applied to the output selection signal line 846 which means to select the appropriate data. The selector 870 selects data on the first operand signal line 803, data on the second operand signal line 804, or six types of non-numeric data on the non-numeric data signal line 861 according to the code on the output selection signal line 846. One of them is selected and the selected data is applied to the output data signal line 725 at time _t5 as shown in FIG.

This concludes the explanation of the operation of the arithmetic device of this embodiment.

Next, effects specific to this embodiment will be explained.

In this embodiment, if at least one of the two operands is a non-number, the calculation result is obtained at time _t5 as shown in FIG. Conventionally, when at least one of two operands is a non-number, exceptional processing by software is required, which takes a lot of time. Furthermore, in this embodiment, when neither of the two operands is a non-number, the operation result is obtained at time _t8 as shown in FIG. 11, but when the operands include a non-number, It can be seen that calculation results can be obtained quickly. +0, 0, - in operand
Since 0 is often included, the average calculation execution time of the calculation device of this embodiment is considerably shortened compared to the conventional one.

〔Effect of the invention〕

According to the present invention, in an operation in which a non-number is included in the operand, whereas conventionally the execution of the operation always needs to be interrupted and exceptional handling by software is required, as long as the mathematical significance is not lost. , correct calculation results can be obtained within the calculation device. Furthermore, in this case, compared to the case where the operands do not include non-numbers, complicated data processing is not required, so the calculation result can be obtained more quickly.

Operands often include non-numbers such as +0, 0, -0, etc., and the average processing time of the arithmetic device according to the present invention is shortened.

[Brief explanation of drawings]

Figure 1 is a block diagram of the real number representation method based on double exponential division, Figure 2 is a diagram showing the procedure for performing addition using the real number representation method based on double exponential division, and Figure 3 is addition including non-numbers. Figure 4 is a diagram that defines subtraction that includes non-numbers, Figure 5 is a diagram that defines multiplication that includes non-numbers, Figure 6 is a diagram that defines division that includes non-numbers, and Figure 7 is a diagram that defines division that includes non-numbers. is an explanatory diagram of the interface between the instruction processing device and the arithmetic unit, FIG. 8 is a block diagram of an embodiment of the present invention, and FIG. 9 is an illustration of the output selection circuit 845 in FIG.
Like FIG. 9, FIG. 10 is a diagram showing another example of the operation of the output selection circuit 845 in FIG. 8. FIG. FIG. 3 is a timing diagram showing the operation of main parts. 71...Instruction processing device, 711...Request signal line, 713...Order signal line, 715...First operand signal line, 716...Second operand signal line, 721...Data sending signal line, 725...
...Output data signal line, 729...Interrupt signal line,
801...first operand register, 802...
Second operand register, 810... Normal addition circuit, 840... Non-number arithmetic processing circuit, 841... First operand non-number judgment circuit, 842... Second operand non-number judgment circuit, 845... Output selection circuit,
846...Output selection signal line, 848...Non number detection signal line, 860...Non number generation circuit, 861...Non number data signal line, 870...Selector, 890...
...Arithmetic control circuit.

Claims (1)

[Scope of Claims] 1. First and second data specified by the instruction processing device, both of which are expressed by a real value representation method based on double exponential division and have variable length exponent and mantissa parts, A device that performs operations specified by the instruction processing device converts each of the first and second data into third and fourth data having fixed-length exponent and mantissa parts, and converts the converted data into third and fourth data. An arithmetic circuit that performs the above-specified arithmetic operation on the data, converts the fifth data obtained as a result of the arithmetic operation into corresponding sixth data having a variable-length exponent part and a mantissa part, and outputs the sixth data, which When at least one of the first and second data is not a non-number, outputs the desired operation result; and whether each of the first and second data is a non-number or not. Sometimes, the type is determined from the bit pattern of each data without converting each data into the third and fourth data, and when both of those data are non-numbers, the operation results are non-numbers. The circuit determines whether the data is a number or not based on the non-number type of the data and the specified operation, the circuit determining whether the data is a number or not based on the non-number type of the data and the specified operation, wherein the first
(1) When it is determined that one of those data is not a non-number and the other is a non-number, the non-number of those data is A non-number determined by the type and the type of the above-mentioned operation is output as the result of the above operation, and (2) when both of those data are non-numbers and the result of the above-mentioned operation on them is not a non-number, (3) both the first and second data are non-numbers;
and a non-number processing circuit that outputs the non-number as the result of the operation when the result of the operation on them is a non-number, and responds to the determination result by the determination circuit.