JPH0447855B2 - - Google Patents

Abstract

PURPOSE:To improve an internal monitoring capacity of a microcomputer by outputting a data on an internal bus line on which internal information is concentrated, from an output terminal by a regular output and a time division. CONSTITUTION:A test instruction code 11 in an instruction register 10 is decoded by an instruction decoder 14 and sent to an output mode register 17. It determines an internal bus line data time division output mode. A multiplexer 23 inputs the test instruction code 11 from the output mode register 17, an immediate data 12 from the instruction register 10, a data of a bus line 18, and a clock signal group 13, and selects one from in the clock group. The data of the bus line 18, and an output of an output latching circuit 20 are outputted by a time division, when a clock signal is on, and when it is of, respectively, amplified by an output buffer 24, and outputted from an output terminal 25.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to microcomputers, and more particularly to one-chip microcomputers.

(Prior Art) Conventionally, it has often been necessary to monitor the internal state of a microcomputer, but monitoring the internal state requires a great deal of effort.

FIG. 1 is a block diagram of a circuit portion near an output terminal of an example of a conventional microcomputer.

The output data signal 1 is taken in and latched by the output latch circuit 2 as a take-in signal 3, outputted as a sweep signal 4, amplified by an output buffer 5, and outputted from an output terminal 6.

With such a circuit configuration, only the value of a single type of signal (ie, output data signal 1) can be output from the output terminal 6. Moreover, the output latch circuit 2
Since the take-in signal 3 to be taken in is determined by the internal clock signal, a change in the output data signal 1 will not appear at the output terminal 6 while the take-in signal 3 is not turned on. As described above, microcomputers with conventional configurations have the disadvantage that it is difficult to sufficiently monitor the data on the bus line where various internal data are accumulated.

(Object of the Invention) An object of the present invention is to eliminate the above-mentioned drawbacks, and to transfer data on the internal bus line where internal information is concentrated and normal output in a time-sharing manner within one clock cycle without storing it in memory. Enables output from the output terminal. Therefore, it is an object of the present invention to provide a microcomputer having a function of increasing the rate of finding defective products in a product inspection process by facilitating on-time monitoring of internal conditions.

(Structure of the Invention) The present invention is characterized by an internal clock signal group, an instruction register for storing a test instruction code and immediate data, an instruction decoder for decoding the test instruction code, and a temporary output data signal. In a microcomputer having an output latch circuit for storing, an output buffer, and an output terminal for outputting a signal from the output buffer, determining a time division output mode of bus line data and an output signal of the output latch circuit, and an output mode register having a reset terminal, further inputting the output signal of the output mode register, the output signal of the output latch circuit, the immediate data, and the internal clock signal group, and During the period when a predetermined clock signal among the clock signals is on, the output signal of the output latch circuit is transmitted, and during the period when it is off, the signal of the bus line data is transmitted externally via the output buffer and the output terminal in a time-sharing manner. A microcomputer is equipped with a multiplexer that outputs output to peripheral devices.

(Example) Next, an example of the present invention will be described using the drawings.

FIG. 2 is a block diagram of one embodiment of the present invention.

This embodiment includes an instruction register 10 having a part for storing test instruction codes and a part for storing immediate data, an instruction decoder 14 for decoding test instruction codes 11,
an output mode register 17 that determines the internal bus line data time division output mode and temporarily stores the decoded test instruction code; and an output data signal 19.
an output latch circuit 20 that inputs and temporarily stores the
Internal clock signal group 13, immediate data 12 output from instruction register 10, test instruction code 11 output from output mode register 17, output data output from output latch circuit 20, and data on bus line 18. is input, selects one clock signal from the internal clock signal group 13, selects the data on the bus line 18 only while the selected one clock signal is on, and selects the output data of the output latch circuit 20 during the off period. Multiplexer 23 for selecting and time-division output
It consists of:

Next, the operation of this embodiment will be explained.

When the test instruction is executed, the test instruction code 11 stored in the instruction register 10 is decoded by the instruction decoder 14 and sent to the output mode register 17. Output mode register 1
Reference numeral 7 denotes a register for determining the internal bus line data time-division output mode, and by resetting the stored contents with a reset signal 16, normal output can be made.

Multiplexer 23 output mode register 1
The output mode signal output from 7, the immediate data 12 sent from the instruction register 10, the data on the bus line 18, and the internal clock signal group 13 are input, and the internal clock signal group 1
3, one clock signal specified by immediate data 12 is selected. As a result, when this test command is executed, the bus line 18 is turned on only while this selected one clock signal is on.
During the off period, the output data of the output latch circuit 20 is selected and output in a time-division manner.
The output is amplified by the output buffer 24 and sent to the output terminal 25.
is output in a time-division manner.

With this configuration, the buffer 18 accumulates various internal data such as read-only memory (ROM), address data and memory data of temporary storage memory (RAM), and input/output data of logic processing unit (ALU). data can be monitored at each timing of the internal clock signal group,
The ability to monitor internal conditions is improved.

In the above embodiment, the output terminal 25 is shown as a dedicated terminal, but it may also be used as an input/output terminal. Further, although one multiplexer is shown, two multiplexers may be used to share the functions.

(Effects of the Invention) As explained in detail above, according to the present invention,
When the output mode signal of the output mode register, which determines the time-sharing output mode based on the output of the instruction decoder, is on, the internal clock signal group consisting of multiple internal clock signals with different phases is specified by the immediate data. One predetermined internal clock signal selected from among them controls the output data output from the output latch circuit during the on period, and the address data of the ROM and RAM on the bus line, the input/output data of the ALU, etc. during the off period. When the output mode signal is reset and is at low level, the output is normal. Therefore, in the time-division output mode, two systems of data can be output from the output terminals to external peripheral devices in a time-division manner within one clock cycle. This makes it possible to directly monitor on-time from the outside without having to store it in memory, which has the effect of increasing the rate of defective product detection by the microcomputer during the product inspection process.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a circuit near the output terminal of a conventional microcomputer, and FIG. 2 is a block diagram of an embodiment of the present invention. 1...Output data signal, 2...Output latch circuit, 3...Take-in signal, 4...Sweep signal, 5...
...Output buffer, 6...Output terminal, 10...Instruction register, 11...Test instruction code, 12...Immediate data, 13...
Internal clock signal group, 14...Instruction decoder, 1
6... Reset signal, 17... Output mode register, 18... Bus line, 19... Output data signal, 20... Output latch circuit, 21... Take-in signal, 22... Sweep signal, 23... Multiplexer, 24...Output buffer, 25...Output terminal.

Claims (1)

[Claims] 1. An internal clock signal group, an instruction register for storing test instruction codes and immediate data, an instruction decoder for decoding the test instruction codes, an output latch circuit for temporarily storing output data signals, and an output buffer. , an output terminal for outputting a signal from the output buffer, and an output mode register for determining a time division output mode of the bus line data and the output signal of the output latch circuit, and having a reset terminal. , further inputting the output signal of the output mode register, the output signal of the output latch circuit, the immediate data, and the internal clock signal group, and inputting a predetermined one clock signal from the internal clock signal group. A multiplexer is provided that outputs the output signal of the output latch circuit during the period when the signal is on, and the signal of the bus line data during the period when the signal is off, in a time division manner to an external peripheral device via the output buffer and the output terminal. A microcomputer featuring: