JPH0447861A - Image reading analog signal digital processing device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to analog image processing for image scanners such as digital copying machines, facsimile machines, or computer image processing devices that read original images with line image sensors and generate image information. The present invention relates to a digital processing device that converts signals into digital image data.

[Conventional technology]

For example, a digital copying machine has a digital scanner that uses a CCD image sensor to convert image light into an analog electrical signal and an A/D converter to convert the analog signal into digital data. If the brightness of the original image light or the brightness of the background changes or varies due to variations in the background density, etc., and the quantization reference voltage of the A/D converter for digitization is a fixed value, when the digital data Changes or variations occur due to changes over time or variations in the background density of the original, and the density of both images (copies) recorded using the digital data may differ from the original image density, or the original background may be reproduced and recorded and the background may vary. It may cause stains.

Therefore, in the past, an A/D converter was used to generate several levels of quantized reference voltages proportional to an externally applied reference voltage and quantize the analog image signal by comparing it with these reference voltages. A peak hold circuit holds the peak value (white) of the analog image signal when the line image sensor is reading a reference white plate outside the copy or original.
The analog voltage held by the peak hold circuit or the voltage obtained by amplifying it (multiplying it by a coefficient) is applied to the reference voltage input terminal of the A/D converter.

FIG. 2 shows a conventional example of this type of image reading section of a digital copying machine. This image reading section includes a COD image sensor 11 that converts an image into an analog electrical signal, and a black level ( Clamp circuit that reproduces the direct current (pulsating current) that becomes the image) 12. A sample and hold circuit 13 that samples and holds the image signal (document width) portion pixel by pixel. There is an A/D converter 14 that converts the image signal from an analog value to a digital value in accordance with the reading speed, and a peak hold instruction signal WS (high level H).
=H), it is composed of a peak hold circuit 16 and the like that peak-holds the voltage of the capacitor Co charged by the switch element 15 that is turned on.

The output from the peak hold circuit 16 is input to the reference voltage input terminal Vref of the A/D converter 14. Signal W
S (WS=H) is generated in a reading section where the maximum value (white or background) of the input level of the original exists.

Fluorescent lamps or halogen lamps are commonly used as the light source for copying machines, but the illuminance on the document surface is not constant due to ambient temperature, changes in the light source over time, changes in lighting conditions, dirt, etc. The maximum illuminance value also changes depending on the background, so fixing the white level can cause background stains. Therefore, a method is adopted in which the maximum value of the input that is regarded as the white level is changed at any time.For example, there is a method in which the full scale of the A/D converter 14 is changed in accordance with the maximum value of the input. This is done by changing the reference voltage of the A/D converter 14.

3a, 3b and 3c, the signal WS (W
This figure shows how to set the interval in which S=H) occurs.

FIG. 3a shows an example in which the WS generation section is set at the beginning of the document 17. Generally, in a black and white document original, there are no characters around the edges of the original, only the background, so when the area is read, a signal w S (VS = H) is generated, and the WS
The peak value (maximum value of the white level) of the read analog signal between =H is held in the peak hold circuit 16.

Similar to FIG. 3a, FIG. 3b shows the case of a monochrome document, but the signal WS is generated at the center of the document. Generally, on a copy machine, the center of the document is the brightest.
It gets darker as you go further around. This is called shading, and is caused by non-uniform illuminance of the light source in the document width direction and the light focusing ability of the lens. For this reason, in the example of FIG. 3a described above, the signal WS is generated around the edge of the document, so in order to correct this shading, the signal WS is sent from the peak hold circuit 16 to the A/D converter 1.
The reference voltage given to 4 must be the peak value multiplied by the correction coefficient, but in the case of Figure 3b, the generation section (peak hold section) of the signal WS is set in the center. Optimal design can be achieved without the need to multiply by the above-mentioned correction coefficient.

Also, in this case, the manuscript is mainly text-based.

The peak detection circuit (15, Co, 16) sufficiently detects and holds the peak (white) of the background portion of the original.

However, in halftone images such as photographs, the background rarely appears in the center of the document.

FIG. 3c is an example of a color copying machine.

In the case of a color original, it is not possible to set a white part on the background, so a reference white level is required outside the original. 3rd c
In the figure, a sub-reference plate 18 is provided alongside the original 17 in the sub-scanning direction of the scanner.

3a, 3b, and 3c, the WS section has a white level that becomes the reference voltage of the A/D converter 14, and the maximum value is set in the peak hold circuit 16 during main scanning (one line reading). By holding the A/D converter 1
4 reference voltage is given.

Conventionally, this peak hold is often performed by an analog circuit (for example, Japanese Patent Application Laid-Open No. 1-284177 and Japanese Utility Model Application No. 1-151668).

[Problems to be Solved by the Invention] However, with analog circuits, it is difficult to achieve both high-speed peak detection and long-time holding. As a result, the high-speed response is poor and it is not possible to follow the peak voltage, or conversely, the voltage hold for a long time is not sufficient, so the reference voltage of the A/D converter 14 fluctuates, and as a result, the converted digital value has a gradation. Moreover, considering the variation in sensitivity among the five pixels, the peak value of one pixel will occur sporadically, so the response characteristics of peak hold cannot be sacrificed.

There is a close relationship between the response characteristics (response speed) and hold characteristics (stability of hold voltage) of the hold capacitor CO of the peak hold circuit 16. - For boat fishing, if the capacitance of the hold capacitor C is small, the response characteristics will be good but the hold characteristics will be poor; conversely, if the capacitance of the hold capacitor C is large, the hold characteristics will be good but the response characteristics will be poor. This is because if the capacitance of the hold capacitor C8 is large, the time constant becomes large and the start-up during charging becomes difficult. On the other hand, during hold, the discharge time constant of the capacitor C is proportional to the capacitance.

FIG. 4 shows the hold characteristics (droop characteristics) of the peak hold circuit 16.

At this time, the changing voltage ΔV of the peak hold circuit 16 is:
There is the following relationship.

ΔV=IbXTXCh...-(1) ■b=Discharge current T2 Hold time Ch: Capacitance discharge current Ib of capacitor co is the leakage current of capacitor co.

It is determined by the input current of the peak hold circuit 16 and the leakage current of the switch element 15 when it is off.

The input section of the peak hold circuit 16 is composed of an amplifier using an FET and has an impedance of about 1012Ω. Furthermore, if the switch element 15 is also constituted by an FET, the impedance will be approximately the same. Also, capacitor co
The leakage current varies depending on conditions such as humidity.

From equation (1), improving the rise response characteristics of the peak hold circuit 16 and improving the hold characteristics are essentially incompatible.

An object of the present invention is to obtain stable image data by improving peak response characteristics and hold characteristics when a white reference is set as a reference voltage input of an A/D converter.

[Means to solve problems]

The present invention relates to a digital processing device that converts an analog image signal obtained by reading an original image with a line image sensor (1) into digital data.

It has a reference signal input terminal (Vref), and quantizes the analog image signal output by the line image sensor (1) with a reference voltage specified by the reference voltage applied to the reference signal input terminal (Vref) to convert it into digital data. A/D conversion means (4) for converting; data memory means (5) for storing digital data generated by the A/D conversion means (4); converting data stored in the data memory means (5) into analog signals D/A conversion means (7); peak hold instruction signal (
In response to ws = H), a predetermined level of voltage (Vvs) is applied to the reference signal input terminal (Vref) while it is there;
D while there is no peak hold instruction signal (VS = H)
Signal switching means (8) for applying the analog signal generated by the /A converting means (7) to the reference signal input terminal (Vref); and, in response to the peak hold instruction signal (VS = H), The digital data generated by the /D conversion means (4) is compared with the data stored in the data memory means (5), and when the value indicated by the former digital data is greater than the value indicated by the latter stored data, the data is stored in the data memory means (5). Data updating means (6, 9) for updating and storing the former digital data
) ;

Note that symbols in parentheses indicate corresponding elements in the embodiments shown in the drawings and described later.

[Effect]

When the peak hold instruction signal (ilIS = O) is generated, the data updating means (6, 9)
The digital data generated by the A/D conversion means (4) is compared with the data stored in the data memory means (5), and when the value indicated by the former digital data is greater than the value indicated by the latter stored data, the data memory means (5) The former digital data is updated and stored. Therefore, this causes digital data indicating the peak value of the analog image signal to be stored in the data memory means (5).

When the peak hold instruction signal (tts = )l) disappears, data in the data memory means (5) is not updated, so the primary peak hold instruction signal (us = H)
The data memory means (5) retain digital data representing the peak value of the analog image signal until the peak value of the analog image signal is generated.

On the other hand, when the peak hold instruction signal (ws=H) disappears, the signal switching means (8) applies the analog signal generated by the D/A converting means (7) to the reference signal input terminal (Vref), Since the conversion means (7) is given the data stored in the data memory means (5), the reference signal input terminal (Vref) of the A/D conversion means (4) receives an analog signal indicating the peak value of the analog image signal. is applied.

Therefore, the A/D conversion means (4) converts the analog image signal output by the line image sensor (1) into a quantum signal with a reference voltage defined by the reference voltage (peak value) applied to the reference signal input terminal (Vref). and convert it into digital data.

As described above, the digital data indicating the peak value during the peak value detection period (WS=H) is stored in the data memory means (5), and outside the peak value detection period, this digital data is converted into analog data and converted into A/D. Since it is applied to the reference signal input terminal (Vref) of the conversion means (4), there is no gradual decrease in the hold voltage over time (Δ■ in Figure 4) unlike when using a conventional analog peak hold circuit, and the reference voltage There is no deterioration in gradation of A/D conversion due to fluctuations in . therefore,
Peak detection during the peak value detection period (WS=H) can be performed with high-speed responsiveness, and high-speed peak detection and long-term stable holding are both compatible, and stable image data can be obtained.

Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the drawings.

〔Example〕

FIG. 1 shows an embodiment of the present invention. An analog image signal from a COD image sensor 1 that converts an image into an electrical signal is provided to a clamp circuit 2.

The clamp circuit 2 reproduces a direct current (pulsating current corresponding to the black density of the image) that becomes a black level from the output voltage of the CCD 1.

The sample and hold circuit 3 captures this DC voltage level in synchronization with one pixel synchronization signal and holds it for one cycle of the synchronization signal (until the next synchronization signal appears). The A/D converter 4 converts the hold voltage into digital data (image data) during this one cycle.

A memory 5 for storing the digital signal converted by the A/D converter 4 in order to detect and hold the peak value (white) of the analog image signal. a digital comparator 6 that compares the value indicated by the digital data stored in the memory 5 with the value indicated by the digital data newly converted by the A/D converter 4, and updates and writes the larger one to the memory 5;
Ant gate 9 which performs this operation only during the peak value detection period (WS=H). Digital data in memory 5,
D/A that converts to an analog value multiplied by an appropriate coefficient Vk
When the converter 7 and the peak value check instruction signal WS are present (WS=H), the fixed reference voltage Vws is not set (
When WS=L), a switch element 8 is provided which switches the analog output of the D/A converter 7 and inputs it to the reference voltage input terminal V ref of the A/D converter 4.

Next, the operations between the constituent elements will be explained. The switch element 8 connects the fixed reference voltage Vws to the reference voltage terminal Vref of the A/D converter 4 in response to the peak hold instruction signal (WS=H) generated once in each main scan.

The fixed reference voltage Vvs is set to the maximum voltage of the CCD output voltage within the range assumed in the design. This is also the maximum value of the reference voltage that the A/D converter 4 can take.

In response to the peak hold instruction signal (WS=H), the switching element 8 sets the fixed reference voltage V vs tt A/D
While applying the voltage to the reference voltage terminal V ref of the converter 4, the COD read signal (analog image signal) of the background portion of the original 17 (FIGS. 3a and 3b) or the sub-reference plate 18 (FIG. 3c) is The analog image signal is applied to an A/D converter 4 via a clamp circuit 2 and a sample hold circuit 3, and the A/D converter 4 converts this analog image signal into a fixed reference voltage V.
Reference voltage defined by vs (multi-stage reference voltage for distinguishing which height range the analog voltage level is in)
, and converts it into digital data (data indicating the level stage to which the analog voltage level belongs). This digital data is applied to the write data input terminal of the memory 5 and the digital comparator 6. The digital comparator 6 compares the stored data (B) of the memory 5 with the digital data (B) of the A/D converter 4.
Compare with A).

When the latter (A) exceeds the former (B), a memory write instruction signal is given to the AND gate 9. and gate 9
A peak hold instruction signal (WS=H) is applied to the memory 5, whereby a memory write instruction signal is applied to the memory 5, and the output data (A) of the A/D converter 6 is written into the memory 5. With the above operation, while the peak hold instruction signal (WS=H) is present, the original 17 (FIG. 3a) is maintained.

The background part of Fig. 3b) or the sub-reference plate 18 (Fig. 3c)
The peak value of the COD read signal (analog image signal) (
Data indicating the white peak level) will be stored in the memory 5.

When the peak hold instruction signal disappears (WS=L),
The switch element 8 switches and supplies the output of the D/A converter 7 (analog conversion voltage of the data in the memory 5) to the reference voltage input terminal Vref of the A/D converter 4.

The D/A converter 7 generates an analog voltage corresponding to the value obtained by multiplying the peak data held in the memory 5 by a coefficient Vk. This D/A converter 7 is called a multiplying DAC (multiplying type D/A converter), and by inputting a signal indicating the coefficient Vk to the reference voltage input terminal of the D/A converter 7, , outputs a voltage corresponding to a value obtained by multiplying the input digital value by a coefficient Vk. When the coefficient Vk is shown in FIGS. 3a and 3c, the peak hold instruction signal (
Since WS=H) is generated at the edge of the document and does not reach the maximum value (a value that holds the peak at the center of the document), it is necessary to correct it. This coefficient Vk is determined by reading a shading correction plate (for example, a white board 18 shown in FIG. 3c) arranged in the main scanning direction before starting scanning of the original 17.

It is obtained by setting the ratio of the reference value to the read value as Vk. Alternatively, the coefficient data may be calculated in advance from the shading data and written into the memory.

When one image reading in the main scanning direction (one line of image signal processing) is completed, the next peak hold instruction signal (WS
The digital maximum value stored in the memory 5 at the beginning (rising edge) of =H) is cleared by the CLR signal in preparation for the next peak value detection and storage.

The reference voltage of the A/D converter 4 set in this way is based on the light intensity of the illumination light source and the original background (third
In the case of Figures a and 3b), the reference value (skin density O
Corresponding value) + In the A/D converter 4, the quantization reference voltage of each stage is determined in conjunction with this, and in which of the level regions defined by the quantization reference voltage of each stage the analog image signal level is located. , that is, digital data is generated.

According to this, it is possible to achieve both good rise characteristics and good hold characteristics, which were not compatible with the conventional peak hold using capacitor C8. That is,
Since peak detection is performed at high speed by the A/D converter 4, it follows even the peak of one pixel. Furthermore, the hold characteristic does not change because the maximum value is held in the memory 5 as a digital value.

〔Effect of the invention〕

According to the present invention, as described above, the peak value detection period (WS
=H) is stored in the data memory means (5), and outside the peak value detection period, this digital data is converted into analog data and the A/D conversion means (4)
Since it is applied to the reference signal input terminal (Vref) of
There is no deterioration in the gradation of A/D conversion due to fluctuations in the reference voltage. Therefore, peak detection during the peak value detection period (WS=H) can be performed with high-speed responsiveness, and high-speed peak detection and long-term stable holding are compatible, and stable image data can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a block diagram showing one configuration of a conventional digital conversion device. FIGS. 3a, 3b, and 3c are plan views showing the original 17 to be read, and show peak hold intervals (WS) for the original. FIG. 4 is a graph showing the change in the hold voltage of the peak hold circuit 16 shown in FIG. 2 over time. 1: ccD (line image sensor) 2: Clamp circuit 3: Sample hold circuit 4: A/D converter (A/D conversion means) 5:
Memory (data memory means) 6: Digital comparator 7: D
/A converter (D/A conversion means) 8: Switch element (
signal switching means) 9: AND gate (6, 9: data updating means) 11: C
CD 12: Clamp circuit 13: Sample hold circuit 14: A/D converter 15:
Switch element 16: Peak hold circuit 17
:M draft (M draft) 18: Sub-reference plate

Claims (1)

[Claims] A digital processing device that converts an analog image signal obtained by reading a document image with a line image sensor into digital data, which has a reference signal input terminal and converts the analog image signal output from the line image sensor into the reference signal. A/D conversion means for quantizing and converting into digital data using a reference voltage defined by a reference voltage applied to the signal input terminal; data memory means for storing digital data generated by the A/D conversion means; D/A conversion means for converting the data stored in the data memory means into an analog signal; in response to a peak hold instruction signal, a voltage at a predetermined level is applied to the reference signal input terminal while the peak hold instruction signal is present, and there is no peak hold instruction signal; signal switching means for supplying the analog signal generated by the D/A conversion means to the reference signal input terminal; data updating means for comparing data with data stored in the data memory means and updating and storing the former digital data in the data memory means when a value indicated by the former digital data is greater than a value indicated by the latter stored data; Digital processing device for image reading analog signals.