JPH0447863A - Synchronizing separator circuit - Google Patents

Abstract

PURPOSE:To set a slice level optimum to the separation of a horizontal synchronizing signal and a vertical synchronizing signal by providing a transistor(TR) to the synchronizing separator circuit, in which its collector connects to an emitter of a constant current source TR via a resistor, its emitter connects to ground and its base receives a vertical pulse signal. CONSTITUTION:Since a setting value of a slice level for synchronizing separation of a synchronizing separation TR Q1 is changed by giving a vertical pulse signal to a base of a TR Q5 whose collector connects to an emitter of a constant current source TR Q2 via a resistor and whose emitter connects to a base of a TR Q5 whose emitter connects to ground so as to change a current flowing through the constant current source TR Q2 even when only a vertical synchronizing signal is attenuated, both the horizontal synchronizing signal and the vertical synchronizing signal are separated by making a slice level for a vertical fly-back period deeper than a slice level for a video signal period.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application 1] The present invention relates to a synchronous separation circuit in a deflection signal processing circuit of a television receiver.

[Prior art] Fig. 3 is a circuit diagram showing an example of a conventional synchronous separation circuit;
Figure iAl, (B) is a waveform diagram showing the composite video signal and the collector voltage of the synchronization separation transistor Q, Figure 5f
A) to (D) are waveform diagrams for explaining the problems of the synchronous separation circuit of FIG. 3.

This synchronous separation circuit consists of an input terminal 1 to which a composite video signal as shown in FIG.
, resistors R, J and capacitor C1 which are connected in series between the synchronous isolation transistor Q1 and the input terminal 1, and a constant current source transistor whose collector is connected to the emitter of the synchronous isolation transistor Q1. Q2 and
A constant current source resistor R3 connected between the emitter of the constant current source transistor Q2 and the ground, a DC power supply 3, and resistors R6, R7, connected in series between the DC power supply 3 and the ground. R8, resistor R4, resistor R6, and the minus (-) side input terminal are synchronous separation transistor Q,
The comparator circuit 2 is connected to the collector of the circuit, and the positive (+) side input terminal is connected to the connection point between the resistors R6 and R7, the output terminal 4, and the bases are connected to the resistors R2 and R7.

Which connection point is connected to, the collector is connected to the DC power supply 3, the emitter is connected to the resistor R4, and the transistor Q3 supplies a predetermined bias voltage from the emitter to the base of the synchronous isolation transistor Q, and the collector is connected to the resistor R4. , the collector and base are connected, the emitter is connected to ground via a resistor R6, and the transistor Q4 supplies a bias voltage to the base of the constant current source transistor Q2. , the synchronization signal separated by the synchronization separation transistor Q1 is waveform-shaped by the comparator circuit 2, and then outputted from the output terminal 4.

Next, regarding the operation of this synchronous separation circuit, FIG.
This will be explained using iB).

Composite video signal including a video signal and a synchronization signal (Fig. 4 (A)
)) is input to the input terminal 1, the synchronization separation transistor Q becomes conductive during the synchronization signal period TC and charges the capacitor C1 with its emitter current ΔIE. on the other hand,
During the video signal period TD, the synchronous separation transistor Q1 is cut off, so the charge in the capacitor C1 is discharged via the constant current source transistor Q2. That is, the charging and discharging of the capacitor C1 is as shown by the dotted line in FIG. 4fA).

Therefore, the fourth
The slice level ■8 for synchronizing signal separation shown by the dashed line in the figure (Al) is as follows: ■3=△IEXRI, where the resistance value of the resistor R3 is R1.Here, the current flowing through the constant current source resistor R3 is ■
. Assuming that the amount of charge charged to the capacitor C3 and the amount of discharged charge are equal, △I E X T c ” I o x T .

Therefore, the slice level 8 is set using equation (1). In addition, the current ■. is the voltage value of DC power supply 3. ,
The resistance values of resistors R3 to R8 are R3-R8, respectively, and the base-emitter voltages of constant current source transistor Q2 and transistors Q, , Q, are . Then, (2) formula % formula % Video signal period T. Since the synchronous separation transistor Q is cut off, no current flows through the resistor R2, so the synchronous separation transistor Q is cut off.

The collector voltage of DC power supply 3 is as shown in Fig. 4 fBl.
voltage value E. bawl. On the other hand, since the synchronous separation transistor Q1 is conductive during the synchronous signal period Tc, the synchronous separation transistor Q is connected to the resistor R2.

Since the collector current ΔIcf=ΔI E + I O) flows, the collector voltage of the synchronous separation transistor Q is E, assuming that the resistance value of the resistor R2 is R2. -ΔIcXR2
(See Figure 4 fB)). Therefore, a signal obtained by separating the synchronization signal of the composite video signal is obtained at the collector of the synchronization separation transistor Q1. The separated synchronization signal is input to the negative (-) side input terminal of the comparator circuit 2,
The voltage values obtained by the three resistors R6 to R8 (Eo and E
.

-ΔI (voltage value between

[Problems to be Solved by the Invention] In the conventional synchronization separation circuit described above, the synchronization signal is separated by the slice level Vs set as shown in equation (1).
If the setting is set near the peak of the synchronization signal as shown in Figure 5, sufficient attenuation tolerance can be obtained when both the horizontal synchronization signal and the vertical synchronization signal are attenuated, but when only the vertical synchronization signal is attenuated as shown in Figure 5 fBl, the vertical synchronization signal is not separated, but only the horizontal synchronizing signal is separated;
Even if the slice level vs is set deep toward the video signal side as shown in Figure 5(D), when both the horizontal synchronization signal and the vertical synchronization signal are attenuated, the slice level 8
This has the disadvantage that the signal becomes too deep and separates the video signals, making it impossible to perform normal synchronization separation.

An object of the present invention is to provide a synchronization separation circuit that can set an optimal slice level for separating horizontal synchronization signals and vertical synchronization signals.

[Means to solve the problem]

The synchronous separation circuit of the present invention includes a transistor whose collector is connected to the emitter of a constant current source transistor via a resistor, whose emitter is connected to ground, and whose base receives a vertical pulse signal.

[Operation] By inputting a vertical pulse signal to the base of the transistor whose collector is connected to the emitter of the constant current source transistor via a resistor and whose emitter is connected to ground, the current flowing through the constant current source transistor is reduced. By changing the value, the setting value of the slice level for synchronous separation of the synchronous separation transistor can be changed, so the fifth
Even if only the vertical synchronization signal attenuates as shown in Figure (B),
By making the slice level in the vertical retrace period deeper than the slice level in the video signal period, both the horizontal synchronization signal and the vertical synchronization signal can be separated.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the synchronous separation circuit of the present invention, and FIG. 2 is a waveform diagram showing a composite video signal and a vertical pulse signal.

The synchronous separator circuit of this embodiment is different from the conventional synchronous separator circuit shown in FIG. It has a transistor Qs connected to the emitter of the transistor Q2, whose emitter is connected to ground, and whose base receives a vertical pulse signal.

Next, the operation of the synchronous separation circuit of this embodiment will be explained using FIG. 2.

When the composite video signal shown in FIG. 2(A) inputted to the input terminal 1 is in a video signal period other than the vertical retrace period, the composite video signal shown in FIG. 2(B) is inputted to the vertical pulse signal input terminal 5. Since the vertical pulse signal is at a low level, transistor Q5 is cut off. Therefore, the value of the current flowing through the constant current source transistor Q2 at this time is:
Current I flowing through constant current source resistor R3. bawl. Note that this current I. is expressed by equation (2) as in the conventional example.

In addition, Fig. 2 (A
) - the slice level v for synchronization signal separation shown by the dotted chain line
s is also set using equation (1) as in the conventional example.

On the other hand, when the composite video signal input to the input terminal 1 is in the vertical retrace period, the vertical pulse signal input to the vertical pulse signal input terminal 5 is at a high level, so that the transistor Q5 becomes conductive. Therefore, the current Io° flowing through the constant current source transistor Q2 at this time is
Ignoring the saturation voltage of the resistor R9 and assuming that the resistance value of the resistor R9 is R9, the slice level vs° for synchronous separation of the synchronous separation transistor Q1 is expressed as the equation (4), and the video signal It becomes larger than the slice level ■5 for the period.

As a result, the synchronous separation circuit of this embodiment is as shown in FIG. 2(A).
As shown in Fig. 5(B), the slice level ■5'' of the vertical retrace period can be made deeper than the slice level VS of the video signal period, so when only the vertical synchronizing signal is attenuated as shown in Fig. 5(B), However, both the horizontal and vertical synchronization signals can be separated.

Note that the vertical pulse signal input to the vertical pulse signal input terminal 5 may be generated by frequency-dividing a horizontal pulse signal using a countdown method in vertical deflection signal processing.

In the embodiment described above, the slice level ■s° of the vertical retrace period is made deeper than the slice level ■8 of the video signal period, but the reverse nature of the vertical pulse signal shown in FIG. 2(B) is reversed. By making the current value flowing through the constant current source transistor Q2 during the vertical retrace period larger than the current value during the video signal period, the slice level v3° of the vertical retrace period is changed to the slice level v3° of the video signal period.
It may be shallower than 5. In this case, Fig. 5(B)
Contrary to the case shown in , when only the horizontal synchronization signal is attenuated, both the horizontal synchronization signal and the vertical synchronization signal can be separated.

Further, the comparison circuit 2 for waveform shaping shown in FIG. 1 is not necessarily necessary, and the collector voltage of the synchronous separation transistor Q1 may be outputted from the output terminal 4 as it is.

(Effects of the Invention) As explained above, the present invention has a collector connected to the emitter of a constant current source transistor via a resistor, an emitter connected to the ground, and a vertical pulse signal manually applied to the base. By having a transistor for synchronous separation, it is possible to change the current value flowing through the constant current source transistor that sets the synchronous separation slice level of the synchronous separation transistor using a vertical pulse signal. This has the effect that an optimal slice level can be set for separation.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the sync separation circuit of the present invention, FIG. 2 is a waveform diagram showing a composite video signal and a vertical pulse signal, and FIG. 3 is a circuit diagram showing an example of a conventional sync separation circuit. figure,
4(A) and 4(B) are waveform diagrams showing the composite video signal and the collector voltage of the synchronization separation transistor Q1;
Figures (A) to (D) are waveform diagrams for proving the problems of the synchronous separation circuit of Figure 3. 1... Input terminal, 2- Comparison circuit, 3... DC power supply, 4- Output terminal, 5... Vertical pulse signal input terminal, Q+"" synchronous separation transistor, Q2" constant current source transistor, Q3~Qs-) transistor, R,, R2, R4~R,-...resistance, R3-...resistance for constant current source, C,-...capacitor, ΔIE, ΔIc, Io "" current, Vs-...・Slice level.

Claims (1)

[Claims] 1. An input terminal into which a composite video signal is input, a synchronous separation transistor whose base is inputted with a predetermined bias voltage, and a mutual connection between the synchronous separation transistor and the input terminal. A resistor and a capacitor connected in series, a constant current source transistor whose collector is connected to the emitter of the synchronous separation transistor, and a constant current source transistor connected between the emitter of the constant current source transistor and ground. In the synchronous separation circuit having a constant current source resistor, the collector is connected to the emitter of the constant current source transistor via the resistor, the emitter is connected to ground, and a vertical pulse signal is input to the base. A synchronous separation circuit characterized by having a transistor.