JPH0448344A - Software debug mechanism - Google Patents

Abstract

PURPOSE:To easily collect the outputs necessary for debug by providing a means which stops the clock of a processor and also stops the execution of a microprogram as long as both address and register coincidence signals are equal to ''1''. CONSTITUTION:The value of a microinstruction execution address register 6 is always compared with the value of an address latch 5 by a address comparator means 7 during the execution of a microprogram. When the coincidence is obtained between both values, the means 7outputs a coincidence signal 8 to an AND gate 9. If a register coincidience signal 4 and an address coincidence signal 8 are equal to ''1'' when an enable signal 10 is equal to ''1'', the output of the gate 9 is equal to ''O''. Then a processor clock signal 11 is prevented by an AND gate 12 and not supplied to a processor 13 any more. Thus the execution of the microprogram is discontinued. Therefore the execution of the microprogram is stopped only when the value of the register 6 is equal to the expected value and these relevant data is collected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a firmware depacking mechanism, and more particularly to a firmware depacking mechanism using a microprogram address and stop mechanism.

[Conventional technology]

Conventionally, a firmware depacking mechanism built into this type of processor has a structure in which execution of a microinstruction is stopped at the execution address of the microinstruction set by an operator.

[Problem to be solved by the invention]

In the conventional firmware storage mechanism described above,
The execution of the necessary microinstructions will stop at the set stop address, so if the address is executed many times during operation and it is necessary to stop only under certain conditions to collect and depack the data, the necessary data will be The drawback was that it was difficult to collect.

[Means to solve the problem]

The firmware depacking mechanism of the present invention compares an address switch for setting a stop address with the execution address of the microinstruction of the address switch in an information processing device in which a processor executes a microinstruction, and if they are equal, generates an address match signal. means, a register selection switch for selecting a register, a data switch for setting register comparison data, a value of the register selected by the register selection switch and a value of the data switch are compared, and if they are equal, a register match signal is generated. and means for stopping the clock of the processor and stopping the execution of the microprogram if both the address match signal and the register match signal are "1".

〔Example〕

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

The register selection switch 1 selects a register corresponding to the value of the set switch from among the register group 14 included in the information processing device, and outputs the value. A value to be compared with the value of the register group 14 is set in the data switch 2 by the operator, and the register comparison means 3
compares the value of the register selected and output by the register selection switch with the value of the data switch 2, and if they are equal, outputs a register match signal 4 to the NAND gate 9. Reference numeral 5 denotes a means for setting a stop address using a hardware switch, that is, an address switch, which is arbitrarily set by the operator.

6 is a micro register that indicates the address of the micro instruction being executed, and is a micro instruction execution address register 6.
The value of is always compared with the value of the address switch 5 by the address comparison means 7 during execution of the microprogram, and if they are equal, the address comparison means 7 outputs the address match signal 8 to N.
Output to AND gate 9. Enable signal 10 is “1”
”, if both the register match signal 4 and the address match signal 8 are 1, the output of the NAND gate 9 becomes "O", and the processor clock signal 11 is blocked by the AND gate 12 and is no longer supplied to the processor 13. Execution of the microprogram stops.

〔Effect of the invention〕

As explained above, the present invention uses both the hardware register value and address as the address stop condition to determine the value of any register based on the address that is executed many times during operation, and determines the expected value. This has the effect that execution of the microprogram can be stopped only when the value is equal to , and the data at that time can be collected.

. . . NAND gate, 10 . . . Enable signal, 11 . . . Processor clock signal, 12.
...AND gate, 13...processor, 14...register.

Claims (1)

[Claims] In an information processing device in which a microinstruction is executed by a processor, an address switch for setting a stop address, a means for comparing an execution address of a microinstruction of the address switch and generating an address match signal if they are equal, and a register selection for selecting a register. switch and
a data switch for setting register comparison data; means for comparing the value of the register selected by the register selection switch with the value of the data switch and generating a register match signal if they are equal; A firmware debugging mechanism characterized by comprising means for stopping a processor clock and stopping execution of a microprogram if both signals are "1".