JPH0449433A - Debugging mechanism for firmware - Google Patents

Abstract

PURPOSE:To make it possible to sample data necessary for each processing by providing the debugging mechanism with a means for forming a register coincidence signal and a means for aborting a clock of a processor and aborting the execution of a microprogram when both of an address coincidence signal and the register coincidence signal are '1'. CONSTITUTION:A register comparing means 8 compares the value of a debug ging register 5 with the value of a comparing register 6, and when both the values are equal, outputs a register coincidence signal 9 to a NAND gate 10. If both the address coincidence signal 4 and register coincidence signal 9 are '1' when an enable signal 11 is logical '1', the output of the NAND gate 10 becomes '0' and a processor clock signal 12 is gated by an AND gate 13 is not supplied to a processor 14, so that the execution of the microprogram is stopped. Consequently comparing values can be changed in each processing by an address stop in a routine to be used for various processing in common and data when the comparing values of each processing coincide with each other can be sampled.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a firmware debugging mechanism, and more particularly to a firmware debugging mechanism using a microprogram address stop mechanism.

[Conventional technology]

Conventionally, a firmware debugging mechanism built into this type of processor has a structure in which execution of a microinstruction is stopped at the execution address of the microinstruction set by operation i.

[Invention or problem to be solved]

In the conventional firmware debugging mechanism described above, the execution of microinstructions always stops at the set stop address, so data is periodically collected under certain conditions at an address that is executed many times during operation. When it is necessary to debug, there is a drawback that it is difficult to collect the necessary data.

[Means to solve the problem]

The firmware debugging mechanism of the present invention, in an information processing device in which a processor executes microinstructions, uses an address switch for setting a stop address, and compares the stop address set by the address switch with the execution address of the microinstruction to ensure that they are equal. means for generating an address match signal, a debug register for storing debug information, means for setting register comparison data by firmware, and a value of the debug register and register comparison data set by the firmware. Comprising means for generating a register match signal if the address match signal and the register match signal are equal, and means for stopping the processor clock and stopping the execution of the microprogram if the address match signal and the register match signal are both 1. .

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

] is stopped by a hardware switch.

This is an address switch that sets the address, and is set arbitrarily by the operator. 2 is a microinstruction execution address register indicating the microinstruction execution address indicating the address of the microinstruction being executed, and the value of the microinstruction execution address register 2 is always the stop address set by the address switch 1 during execution of the microprogram. The address comparison means 3 compares the address match signal 4 with the value of 1, and if they are equal, the address comparison means 3 outputs the address match signal 4 as N.
Output to AND gate 10. 5 is a debugging register in which various information for debugging is stored.

Data to be compared with the debugging register is set in the comparison register 6 through the conveyor data setting means 7 by a firmware microinstruction. The register comparing means 8 compares the value of the debug register 5 and the value of the comparison register 6, and if they are equal, outputs a register match signal to the NAND gate 10. enable signal 1
1 is logic "1", if address match signal 4 and register match signal 9 are both ]°', NAND gate 10
The output of the microprogram becomes 0'0', and the processor clock 12 is gated by the AND gate 13 and is no longer supplied to the processor 14, stopping the execution of the microprogram.

In the manner described above, data can be collected.

〔Effect of the invention〕

As explained above, the present invention uses both the register value and the address value as the address stop condition to determine the value of the debugging register based on the address that is executed many times during operation, and compares it with the expected value. By making it possible to stop the execution of the microprogram only when they are equal, and by making it possible to freely set the comparison value of the register by firmware, it is possible to stop the execution of the microprogram only when the values are equal. This has the advantage that the comparison value can be changed for each process, and data can be collected when the comparison values for each process match.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Address switch, 2... Microinstruction execution address register, 3... Address comparison means, 4...
・Address match signal, 5...Debug register, 6
. . . Comparison register, 7. Comparison value setting means, 8.
...Register comparison means, 9...Register match signal, 1
o...NAND gate, ]1... Enable signal,
12...Processor clock signal, 13...AND
Gate, 14...processor.

Claims (1)

[Claims] In an information processing device that executes a microinstruction by a processor, an address switch for setting a stop address, and means for comparing the stop address set by the address switch and an execution address of the microinstruction and generating an address match signal if they are equal. a debugging register for storing debugging information; a means for setting register comparison data by firmware; and a means for comparing the value of the debugging register with the register comparison data set by the firmware and generating a register match signal if they are equal. and means for stopping a processor clock and stopping execution of a microprogram if both the address match signal and the register match signal are "1".