JPH0448650A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To improve data-hold characteristics by forming an active region of a load transistor of a third conductive layer which is an upper layer of a second conductive layer and extends on a gate electrode of a driving transistor and by forming a gate electrode of a load transistor of a fourth conductive layer which is an upper layer of the third conductive layer. CONSTITUTION:A ground power supply line 21 is formed of a second layer of a polycrystalline Si layer 47 and the polycrystalline Si layer 47 is connected to n<+>-diffusion layers 42a, 42c which are source regions of nMOS transistors 11, 12 through contact holes 46d, 46e. An active region of pMOS transistors 15, 16 and a driving power supply line 25 are formed of a third layer of a polycrystalline Si layer 48. A gate electrode of pMOS transistors 15, 16 is formed of a fourth layer of polycrystalline Si layer 51, 52. Source/drains region of pMOS transistors 15, 16 and the driving power supply line 25 are formed in self-alignment to polycrystalline Si layers 51, 52, that is, a gate electrode, through ion implantation of p-type impurities using polycrystalline Si layers 51, 52 as a mask.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory called a complete CMO3 type SRAM.

[Summary of the Invention] The present invention provides a semiconductor memory as described above, in which an active region of a load transistor is formed by a conductive layer extending over a gate electrode of a drive transistor, and a conductive layer is formed in a layer above the active region. By arranging the gate electrode and arranging the power supply line in the lower layer, data retention characteristics are improved, and manufacturing yield and reliability are also improved.

[Conventional technology]

FIG. 4 shows a memory cell of a complete CMO3 type SRAM, and this memory cell consists of a pair of nMO3 transistors 11 and 12 for driving and a pair of nMOS transistors 1 for transfer.
3.14 and a pair of load PMO3) transistors 15.1
It consists of 6.

A ground power supply line 21 is connected to the source regions of the nMOS transistors 11 and 12. Further, the word line 22 serves as the gate electrode of the nMO3) transistors 13.14, and the bit 1IA23.2 is connected to the source/drain region of each of the nMO3) transistors 13 and 4.
4 are connected. Furthermore, the PMOS transistor 15
．． A driving power supply line 25 is connected to the 16 source regions.

A type of completely CMO3 type SRAM like this, 2MO3)
There are transistors in which the transistors 15 and 16 are formed of polycrystalline Si thin film transistors, and FIG. 5 shows one conventional example thereof (for example, IEDM882, 48-51).

In this conventional example, the gate electrodes of the nMO3) transistors 11 and 12, the ground power supply line 21 and the word line 22 are connected to Si.
Polycide layers 31 to 3 which are the first conductive layer on the substrate
It is formed by 4.

Further, the gate electrode of the pMO3) transistor 15.16 is formed of a polycrystalline Si layer 35.36 which is the second conductive layer, and the active region of the pMO3) transistor 15.16 and the drive power line 25 are It is formed of polycrystalline Si layers 37 and 38 which are the third conductive layer.

[Problem to be solved by the invention]

However, in this conventional example, the pMOS transistor 1
Since the active region of 5.16 is formed of a conductive layer above the gate electrode, the source/drain regions cannot be formed in self-alignment with the gate electrode.

For this reason, a margin for mask alignment is required in the source and drain regions, and since the gate length is short by that much, PMOS
The off-state current of transistors 15 and 16 is large. Therefore, in this conventional example, the data retention characteristics are not necessarily good.

Moreover, as is clear from FIG. 5, one drive power supply line 25
is actually formed of separate polycrystals 5iii37.38. Therefore, the structure and pattern are more complex than resistive load type SRAMs, and the manufacturing yield is correspondingly lower.

Further, although not shown, the bit lines 23 and 24 are formed of a fourth conductive layer. For this reason, pMO3
) The chaffle regions of transistors 15 and 16 are connected to bit line 23.
．． Under the influence of the potential of 24, the pMOS transistor 15
．． 16 characteristics vary. Therefore, in this conventional example,
Reliability is not necessarily high.

[Means to solve the problem]

In the semiconductor memory according to the present invention, the driving transistor 1
The gate electrodes of each of the transfer transistors 1.12 and 13.14 are connected to the first conductive layers 43 to 45 on the semiconductor substrate 41.
．． The driving transistors 11 and 12
The power supply line 21 electrically connected to the source regions 42a and 42c is connected to the second conductive layer above the first conductive layers 43-45.
The load transistor 1 is formed of a conductive layer 47 of
5.16 active regions are formed of a third conductive layer 48 which is above the second conductive layer 47 and extends over the gate electrode of the driving transistor 11.12; The gate electrodes of the load transistors 15 and 16 are formed in the fourth conductive layer 51. which is located above the third conductive layer 48.
52.

[Function] In the semiconductor memory according to the present invention, the load transistor 1
5. The gate electrode of 16 is in the conductive layer 5 above the active region.
1.52, the source/drain regions can be formed in self-alignment with the gate electrode. Therefore, no allowance for mask alignment is required in the source/drain regions, and the gate length is long, so the off-state current of the load transistors 15 and 16 is small.

Further, the conductive layer 48 in which the active region of the load transistor 15.16 is formed is connected to the drive transistor 11.12.
Since it extends over the gate electrode of the semiconductor memory, it is of the same type as a resistive load type semiconductor memory.

Further, the conductive layer 48 in which the active region of the load transistor 15.16 is formed, the conductive layer 47 in which the power supply line 21 is formed, and the conductive layer 51 in which the gate electrode of the load transistor 15.16 is formed. It is sandwiched between .52 and .52. Therefore, it is possible to prevent the channel regions of the load transistors 15, 16 from being influenced by the potentials of other conductive layers, and to suppress variations in the characteristics of the load transistors 15, 16.

〔Example〕

Hereinafter, first and second embodiments of the present invention applied to the complete CMO3 type SRAM shown in FIG. 4 will be described with reference to FIGS. 1 to 3.

FIG. 1 shows a first embodiment. In this first embodiment, n diffusion layers 42a to 42g, which are source/drain regions of nMOS transistors 11 to 14, are formed in a Si substrate 41 (FIG. 3).

Furthermore, the gate electrodes of the nMO3) transistors 11 and 12 and the word line 22 are formed of first-layer polycrystalline Si layers 43 to 45 on the Si substrate 41.

The polycrystalline Si layer 43 is in buried contact with the n' diffusion layers 42d and 42f through contact holes 46a and 46b, and the polycrystalline St layer 44 is in buried contact with the n' diffusion layer 42b through a contact hole 46c. There is.

The ground power supply line 21 is formed of a second layer of polycrystalline Si layer 47, and this polycrystalline Si layer 47 is formed of n" diffusion layers 42a, 4, which are the source regions of the nMOS transistors 11 and 12.
2c through contact holes 46d and 46e.

The active region of the pMO3) transistor 15.16 and the drive power line 25 are formed of the third layer of polycrystalline Si layer 48, and the gate electrode of the PMOS transistor 15.16 is formed of the fourth layer of polycrystalline Si layer. It is formed by 51.52.

The source/drain regions of the pMOS transistor 51.16 and the drive power line 25 are formed by ion implantation of p-type impurities using the polycrystalline Si layer 51.52 as a mask.
The i-layers 51 and 52 are formed in a self-aligned manner with respect to the gate electrode.

Therefore, the part of the polycrystalline Si layer 48 that overlaps with the polycrystalline Si layer 5 becomes the channel region of the pMO3) transistor 15, and the part that overlaps with the polycrystalline Si layer 52 becomes the pMO3) transistor 15.
5) It is a channel region of the transistor 16.

PMOS transistor 15 in polycrystalline Si layer 48.
The drain region 16 is connected to the gate electrode of the polycrystalline Si layer 44, 43 and the nMOS transistor 12, 11 through contact holes 46f, 46g.

Moreover, the polycrystalline Si layer 52, that is, the pMOS transistor 1
The gate electrode 6 is connected to the drain 61 region of the pMO3) transistor 15 of the polycrystalline 5iJi 48 through the contact hole 46h.

As is clear from FIG. 1, the active regions of the pMOS transistors 15 and 16 in the polycrystalline Si layer 48 are made of polycrystalline Si.
Layer 44.43 extends over the gate electrode of nMO3 transistor 12.11.

The polycrystalline Si layer 51, that is, the gate electrode of the pMOS transistor 15, is connected to the drain region of the pMOS transistor 16 in the polycrystalline Si layer 48 via the contact holes 46i, 46j and the fifth polycrystalline Si layer 53. It is connected.

The bit lines 23 and 24 are formed of an A1 layer which is an upper conductive layer next to the polycrystalline Si layer 53, and these A1 layers are formed by n゛, which is one of the source and drain regions of the nMO3) transistors 13 and 14. It is connected to the diffusion layers 42e and 42g.

2 and 3 show a second embodiment.

As shown in FIG. 2, this second embodiment is a polycrystalline SiJ!
151, that is, pMO3) The gate electrode of the transistor 15 is connected to the polycrystalline Si layer 43, that is, n
The first embodiment shown in FIG. 1 is different from the first embodiment shown in FIG. 1, except that an opening 54 is formed in the polycrystalline Si layer 47, which is connected to the gate electrode of the MOS transistor 11 and serves as the ground power supply line 21. They have substantially the same configuration.

Therefore, in this second embodiment, the polycrystalline Si layer 53 in the first embodiment is unnecessary, and the manufacturing process is accordingly shortened.

Further, as shown in FIG. 3, the channel region 16a of the pMOS transistor 16 is formed of polycrystalline S
It is sandwiched between the i-layer 52 and the polycrystalline Si layer 47, which is the ground power supply line 21, from above and below.

Therefore, the channel region 16a is not affected by the potential of the bit line 24 or the diffusion layers 42b, 42d, pMO3).
The characteristics of the transistor 16 do not change, and polycrystalline Si
Even if the vertical relationship between layer 52 and polycrystalline Si layer 47 is reversed, the same effect can be achieved. The same applies to the pMO3) transistor 15 and the first embodiment described above.

〔Effect of the invention〕

The semiconductor memory according to the present invention has excellent data retention characteristics because there is less current when the load transistor is turned off.

Further, since the semiconductor memory according to the present invention is of the same type as the resistive load type semiconductor memory, the structure and pattern layout are simple and the manufacturing yield is high.

Further, since the channel region of the load transistor can be prevented from being affected by the potential of other conductive layers and the characteristics of the load transistor can be suppressed from changing, reliability is high.

[Brief explanation of the drawing]

1 and 2 are plan views of the first and second embodiments of the present invention, respectively, FIG. 3 is a side sectional view taken along the line ■-■ of FIG. 2, and FIG. FIG. 2 is an equivalent circuit diagram of the completely 0MO3 type SRAM obtained. FIG. 5 is a plan view of a conventional example of the present invention. In addition, in the symbols used in the drawings, 11, 12-----------------------------------------------------------------------------------) nMOSh transistor for transfer 15.16; ---pMO for loading
S transistor 2 t----m------
--m-Ground power supply line 41---------------------
Si base 42a, 42cm・---n” diffusion layer 43.44, 45, 47.48, 51.52・=−・・
- It is a polycrystalline Si layer.

Claims (1)

[Claims] A flip-flop consisting of a pair of drive transistors consisting of a first conductivity type MOS transistor and a pair of load transistors consisting of a second conductivity type MOS transistor; In a semiconductor memory in which a memory cell is constituted by a transfer transistor, each gate electrode of the drive transistor and the transfer transistor is formed of a first conductive layer on a semiconductor substrate, and the drive transistor A power supply line electrically connected to the source region of the load transistor is formed of a second conductive layer above the first conductive layer, and an active region of the load transistor is formed above the second conductive layer. A third conductive layer is formed as an upper layer and extends over the gate electrode of the driving transistor, and the gate electrode of the load transistor is formed of a fourth conductive layer that is an upper layer than the third conductive layer. A semiconductor memory made of conductive layers.