JPH0448664B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention provides a reception control circuit for a train that includes a combination of a receiving antenna that receives information from an on-board device and a ground switch that provides stop information to the on-board device. Regarding speed checking devices for automatic train stopping devices of variable frequency type, which are installed in multiple sets spaced apart in the running direction of a train, it is possible to detect and memorize the malfunction of a switching element that controls a ground element due to a failure of the device. Regarding equipment.

Prior Art Speed checking devices for automatic train stopping devices are generally
When the train is running, a reception control circuit consisting of a receiving antenna such as a loop coil that receives information from onboard equipment mounted on the train and a ground element such as a resonant circuit that provides stop information to the onboard equipment is installed. A plurality of receiving control circuits are provided spaced apart from each other in the direction, each receiving control circuit is connected to a speed checking circuit, and the above-mentioned ground transducer is enabled for a certain period of time from the time when information from the onboard device is received, and when the certain period of time is Once the time has elapsed, the ground coil is disabled. Further, the checking circuit connects each receiving antenna to a processing circuit, and each time information from the on-board device is received by the receiving antenna, the processing circuit operates a timer relay, and a contact point of the timer relay triggers a timer. A counter that increments at the leading edge of the output signal of this timer counts the number of operations of the timer relay, and a counter relay used as a switching element (control element) individually corresponding to the ground element is used to calculate the count value of the counter. Each counter relay enables or disables the corresponding ground element.

Problems to be Solved However, in this type of conventional speed checking device, the counter is cleared when the train leaves the speed checking section. For this reason, even if one of the ground transducers malfunctions due to a failure in the reception control circuit or speed checking circuit, the counter is cleared without distinguishing between the ground transducers and the malfunctioning ground transducer. It had the disadvantage of being left alone.

The present invention has been made in view of the above-mentioned drawbacks, and is an automatic train stop device that allows a malfunctioning beacon to be easily confirmed even after the counter that counts the number of times the timer relay operates is cleared as before. The object of the present invention is to provide a speed checking device.

Means for Solving the Problems In order to achieve the above object, in the present invention, the speed check device of the automatic train stop device is provided with a plurality of reception control circuits 60 spaced apart on the running path 3, and a check circuit 4.
and a failure detection circuit 5, each reception control circuit 60 has reception antennas A1, A
The receiving antennas A1, A2, A3 receive signals from the onboard device 2 of the train 1 and input them to the verification circuit 4, C3 provides the on-board device 2 with stop information from the verification circuit 4, and the verification circuit 4 is connected to the receiving antennas A1, A2, A3.
A processing circuit 20 that is switch-connected to a subsequent timer relay TMR, a timer 21 that performs a counting operation by the timer relay TMR, a counter 22 that counts the number of operations of the timer 21, and a counter 22 that counts the number of times the timer 21 operates.
One of them operates according to the count value of the ground element C.
It has switching elements COR1, COR2, and COR3 that disable the corresponding ones of C1, C2, and C3,
It outputs stop information to the ground elements C1, C2, and C3, and outputs the operating states of the switching elements COR1, COR2, and COR3 to the failure detection circuit 5. The determination means 70 inputs the signal from the checking circuit 4 and determines whether each of the circuits C1,
The structure is such that it determines whether the operations of C2 and C3 are normal or abnormal, and the storage means 80 stores the determination results.

Embodiments Hereinafter, the present invention will be explained based on embodiments shown in the drawings.

In the embodiment shown in FIGS. 1 to 4, 1 is a train equipped with an on-board device 2, which travels along a running path 3 from left to right in FIG.

The above-mentioned onboard device 2 has the same well-known configuration as the conventional one, and as shown in FIG. Installed car top 11
It has a processing circuit 12 that selects, amplifies, rectifies and smoothes a signal of frequency fo, and a main relay MR that is operated by the output signal.The operating contact of the main relay MR is connected to the brake command circuit 13. It is inserted. In each figure, the contacts of the relays are indicated by the same symbols as the corresponding relays, the operating contacts are indicated by V-shaped marks, and the recovery contacts are indicated by inverted V-shaped marks.

The processing circuit 12 activates the main relay only when the oscillator 10 is oscillating at the frequency fo.
This is a circuit for operating the MR, in which the output signal of the oscillator 10 is passed through a bandpass filter 14 to extract a signal of frequency fo, the level of the extracted signal is detected by a level detection circuit 15, and the output signal is amplified by an amplifier 16. After that, the rectifier and smoother circuit 17 rectifies and smoothes the signal (converts it to direct current) and outputs it to the main relay MR.In response to the input of the signal with the frequency fo, the main relay MR is operated and the input signal is output to the main relay MR. If the rectified and smoothed output is not turned on by the main relay
Restore MR.

Brake command circuit 13 outputs a brake command to apply the brakes because main relay MR has fallen.

Three sets of reception control circuits 60 are installed in a speed check section of the running route 3 where the speed of the train 1 is checked. In other words, on driving route 3 in the speed check section,
A total of three sets of a pair of receiving antenna A1 and beacon C1, a pair of receiving antenna A2 and beacon C2, and a pair of receiving antenna A3 and beacon C3 are installed in three appropriately spaced locations in order in the running direction of train 1. A reception control circuit 60 is provided. These receiving antennas A1, A2,
Each pair of A3 and the beacon C1, C2, and C3 (receiving control circuit 60) is installed in the traveling direction of the train 1 with distances L1, L2, and L3 maintained in the order of the receiving antenna and the beacon, respectively.

Each receiving antenna A1, A2, A3 is a known circuit in which a coil, a capacitor, and a load resistor are connected in parallel, and is connected to a reference circuit 4. Each ground element C1, C2, C3 is composed of a resonant circuit in which a coil and a capacitor are connected in parallel, and counter relay COR1, which is a switching element,
The COR2 and COR3 are also connected to the checking circuit 4 through the operating contacts (see FIG. 3). In addition,
The contact points of the relays provided between each ground element C1, C2, C3 and the reference circuit 4 are counter relay COR1,
It does not need to be an operating contact for COR2 and COR3,
In some cases, the contact point of a control relay (not shown) operated by these counter relays may be used.

The verification circuit 4 calculates the time it takes for the onboard element 11 of the train 1 to reach the ground element C1 from the receiving antenna A1,
It is also used to determine whether or not the time from receiving antenna A2 to reach beacon C2 and the time from receive antenna A3 to reach beacon C3 are each longer than a predetermined time T1. This circuit provides stop information to the onboard device 2 by activating the ground terminals C1, C2, and C3 for a predetermined time T1 from the time when the signal reaches the receiving antennas A1, A2, and A3, and furthermore, the failure detection circuit 5 The output is also connected.

This checking circuit 4, as shown in FIG.
A processing circuit 20 that selects a component of fo, amplifies it, rectifies it, smoothes it, and outputs it; a timer relay TMR that operates based on the output; a timer 21 that is triggered every time the timer relay TMR operates;
The counter 22 counts the number of times the timer relay TMR is operated based on the output signal of the timer relay TMR.

The input terminal of the band filter 23 is connected to each counter relay COR1, COR2, COR to the receiving antenna C1.
It is connected in series through the respective falling contacts of counter relay COR1, and is also connected to receiving antenna A2 through the operating contact of counter relay COR1.
Furthermore, there is a counter relay for receiving antenna A3.
Connected via the operating contact of COR2.

In the processing circuit 20, receiving antennas A1, A2,
The frequency fo component of the signal input from A3 is extracted (selected) by the band filter 23, the level (peak value) of the extracted signal is detected by the level detection circuit 24, and the output signal is amplified by the amplifier 25. The rectified and smoothed output is passed through a rectifying and smoothing circuit 26 to operate a timer relay TMR.

For timer 21, timer relay TMR is shown in Fig. 5C.
When the operation is as shown, the operation contact is also activated on timer 21.
The same signal as shown in Figure 5C is input through TMR, and it is triggered at the rising edge of the signal input through the operating contact TMR of timer relay TMR, and from the time it is triggered as shown in Figure 5D. A signal that becomes high level after a certain period of time T1 is output. That is, each time timer relay TMR operates, it outputs a high level signal after time T1.

The counter 22 includes three output terminals individually associated with the ground elements C1, C2, and C3, and increments every time the output signal of the timer 21 rises. This counter 22 becomes capable of counting by a signal inputted through the operating contact of the reaction relay HR, which is activated when the train 1 enters the speed check section (while it is present), and then the output signal of the timer 21 is Each time it rises, it steps forward and outputs a signal to the output terminal.

Counter relays COR1, COR2, COR3 are
It is used as a switching element (control element) connected to each of the three outputs of the counter 22, and operates according to the count value of the counter 22, that is, individually corresponding to the ground elements C1, C2, and C3. . In other words, when the count value of counter 22 is 1, relay COR1 operates, and when it is 2, relay COR1 operates.
COR2 operates, and when it is 3, relay COR3 operates.

The operating contacts of the corresponding counter relays COR1, COR2, COR3 are connected to the ground wires C1, C2, C3, and the corresponding counter relays COR
1, COR2, and COR3 (that is, outputting stop information), they are short-circuited and become invalid.

In addition to the parts equivalent to the conventional ones explained above, the ground equipment of this embodiment also receives signals from the reference circuit 4 (operating states of switching elements COR1, COR2, COR3).
The system is equipped with a failure detection circuit 5 that operates based on the following.

The failure detection circuit 5 includes a determination means 70 and a storage means 80 subsequent thereto. The determining means 70
The signal from the verification circuit 4 is input to each terminal C.
1, C2, and C3 are operating normally.
The judgment result is stored. The determining means 70 of the embodiment includes six flip-flops 31, 3.
2, 33, 34, 35, 36, AND gates 43, 44, 45 connected to these outputs in a predetermined manner, and AND gates 46, 47, following these, respectively.
Three judgment circuits 37, 38, 39 consisting of 48,
It further includes a timer 49, a delay circuit 30, and the like.

The storage means 80 consists of three flip-flops (memory circuits 40, 41, 42), and a display device is connected to the rear stage of the storage means 80. (See Figure 4).

As shown in FIG. 4, each counter is outputted by delaying the signal input by the delay circuit 30 corresponding to the state of the operating contact of the reaction relay HR, which operates while the train 1 is in the speed check section described above. relay
6 flip-flops 31, 32, 3 for monitoring the operating status of COR1, COR2, COR3
3, 34, 35, and 36 are kept operational.

The delay circuit 30 delays the signal shown in FIG. 5A, which is input through the operating contact of the reaction relay HR, by a predetermined time T2 as shown in FIG. 5B.

Flip-flop 31 is a counter relay COR
The flip-flops 32 and 33 are set by the voltage input through the operating contact of counter relay COR1 (i.e., by the closing of the operating contact). Flip-flops 34 and 35 are set by the voltage input through the operating contact of counter relay COR2, and flip-flop 36 is set by the voltage input through the operating contact of counter relay COR3.

Each flip-flop 31, 32, 33, 34,
The outputs of 35 and 36 have respective children C1, C2, and C.
Determination circuits 37, 38, and 39 are connected to each of the circuits 37, 38, and 39 for determining whether or not 3 operates normally. Each determination circuit 37, 38, 39 is a two-input AND circuit 4.
3, 44, 45 and AND circuits 46, 47, 48, which are respectively associated with ground switches C1, C2, and C3 in this order. That is, the AND circuit 43 receives the Q output of the flip-flop 31 and the Q output of the flip-flop 32.
The Q output of the flip-flop 33 and the Q output of the flip-flop 34 are connected to the AND circuit 45, and the Q output of the flip-flop 35 and the Q output of the flip-flop 3 are connected to the AND circuit 45.
Six Q outputs are connected to each. AND circuit 4
The outputs of 3, 44, and 45 are individually connected to one terminal of each of the corresponding AND circuits 46, 47, and 48 at the subsequent stage, and the output of a timer 49 is commonly connected to the other terminal. Strengthen. The timer 49 is triggered at the rising edge of the signal (voltage) input through the recovery contact of the reaction relay HR, and outputs the determination command signal shown in FIG. Therefore, each determination circuit 3
7, 38, and 39 output a determination result as to whether or not each gear operated normally when the train 1 moved out of the speed check section. That is, the judgment circuits 37, 3
In the next stage of 8, 39, each top child C1, C2, C3
Memory circuits 40, 41, and 42 each made up of flip-flops are provided as a memory means 80, respectively.

Each memory circuit 40, 41, 42 is adapted to store the output signal of each preceding stage judgment circuit 37, 38, 39, and the stored contents are cleared by a signal input via a manually operated reset switch 50. be done.

The Q output of each memory circuit 40, 41, 42 is individually supplied to each input terminal of a 3-input NOR circuit 51 and used to notify that a failure has occurred. Indicator lights 55, 56, 57, which are individually supplied to the corresponding lamp drivers 52, 53, 54, are turned on in response to the failure situation.

Operation Next, the operation of the speed checking device described above will be explained in more detail with reference to FIG.

First, if train 1 has not entered the speed check section, the reaction relay HR has been restored, so the counter 22 and each flip-flop 31, 32, 3
3, 34, 35, and 36 are inhibited from operating (inoperable). For this reason, each counter relay COR
1, COR2, and COR3 have been restored, and the respective children C1, C2, and C3 are in a valid state. Flip-flop 31 is not set because it is inoperable, although the high-level signal shown in FIG. 5E is input thereto. Furthermore, the receiving circuit 2
0 is each counter relay COR1, COR2, COR
It is connected to the receiving antenna A1 via the recovery contact No. 3.

In this state, when the train 1 enters the speed check section at time t1, the reaction relay HR is activated, and as a result, a signal rising at time t1 is input to the counter 22 and the delay circuit 30 as shown in FIG. 5A. As a result, the counter 22 is maintained operable as shown in FIG. 5B, and the delay circuit 30 is maintained for a certain period of time T from time t1.
A signal that rises at time t2 after 2 elapses is output. Even if the counter 22 is maintained operable, the count value at that time is 0, so each counter relay
COR1, COR2, and COR3 remain restored, so each of the topology C1, C2, and C3 is enabled, and processing circuit 20 remains connected to receive antenna path A1. Next, the delay circuit 30 starts at time t.
When the signal shown in FIG. 5B rising to 2 is output, each flip-flop 31, 32, 33, 34, 3
5, 36 are maintained operative, and flip-flop 31 is then set to activate the counter relay.
Memorize that COR1, COR2, and COR3 have been restored. At time t3, the onboard child 11 uses the receiving antenna A.
1, between time t3 and t4 the vehicle upper child 1
Since the signal of frequency fo from reception antenna A1 is input to processing circuit 20 via the recovery contacts of counter relays COR1, COR2, and COR3, timer relay TMR operates from time t3 to time t4. As a result, the timer 21 receives the signal shown in FIG.
The counter 22 outputs a signal shown in FIG. 5D that rises for a short time at t5, and as a result, the counter 22 increments to 1 at time t5.

When the count value of the counter 22 reaches 1, the counter relay COR1 operates, and the ground element C1 is disabled by its contact. Therefore, the onboard child 11 of train 1
When reaches the ground element C1 before time t5,
Upon receiving the stop information, main relay MR drops and outputs a brake command from brake command circuit 13. However, when the onboard member 11 reaches the beacon C1 after time t5, the beacon C1 has become invalid, so the train 1 does not receive stop information and can proceed as is.

When counter relay COR1 operates, flip-flops 32 and 33 have a fifth pulse rising at time t5.
Since the signal shown in Figure F is input, it is set and it is stored that counter relay COR1 has operated.
Furthermore, the processing circuit 20 is switch-connected to the receiving antenna A2.

Next, while the counter relay COR1 is operating, the onboard child 11 of the train 1 changes from time t6 to t7.
When passing over receiving antenna A2, timer relay TMR also operates during that time, and timer 21
is triggered and a certain period of time T1 has elapsed, at time t8
Outputs a signal that rises for a short time. As a result, the counter 22 increments to 2 at time t8, and the count value becomes 2, and as a result, the counter relay COR1 recovers and returns the ground element C1 to the valid state, and disconnects the receiving antenna A2 from the processing circuit 20. , the counter relay COR2 operates to disable the ground element C2 and the receiving antenna A3 to the processing circuit 20.
connection and switching is performed. And just like before,
In the end, the train 1 receives stop information if the time when the onboard child 11 reaches the ground child C2 is before t8, but does not receive the stop information if it is after time t8.

When counter relay COR2 operates, flip-flops 34 and 35 are set by inputting the signal shown in FIG. 5G rising at time t8, and store that counter relay COR2 has operated.

Next, the same applies when the onboard child 11 passes over the receiving antenna A3 between time t9 and t10, during which time the timer relay TMR operates, the timer 21 is triggered, and the time t11 is reached after a certain period of time T1 has elapsed.
Outputs a signal that rises for a short time. As a result, the counter 22 increments to 3 at time t11, and as a result, the counter relay COR2 recovers and enables the ground element C2, disconnects the receiving antenna A3 from the processing circuit 20, and further disables the ground element C3. . Therefore, in the train 1, the onboard member 11 is connected to the ground member C3.
If the time reaches before t11, the stop information will be received, but if it is after t11, the stop information will not be received.

When counter relay COR3 operates, flip-flop 36 is set by inputting the signal shown in FIG. 5H that rises at time t11, and stores that counter relay COR3 has operated.

Then, when the train 1 advances from the speed check section at time t12, the reaction relay HR is restored as shown in FIG. 5A, so the counter 22 becomes inoperable. In response, the timer 49 outputs the determination command signal shown in FIG. 5I, which rises for a short time from time t12. As a result, each determination circuit 37, 38, 39 determines whether or not each transistor C1, C2, C3 operates normally based on the states of the flip-flops 31 to 36, and this determination result is used in the storage circuit 40, 41,
42.

Thereafter, at time t13, the output signal of the delay circuit 30 falls as shown in FIG.
becomes inoperable. However, each switching element
Whether or not COR1, COR2, and COR3 are normal is stored in memory circuits 40, 41, and 42, which are memory means 80.

When the train passes, each counter relay COR1,
When COR2 and COR3 all operate normally,
Each flip-flop 31, 32, 33, 34, 3
5 and 36 are set, each judgment circuit 37,
When the judgment command signal is input, the outputs of 38 and 39 become signals with a truth value of "0" which means that they are normal, and this is held in the memory circuit, and therefore the output of the NOR circuit 51 means that it is normal. The truth value "0" is held.

If counter relay COR1 does not operate, flip-flops 32 and 33 will not be set. In this case, the AND circuit 43 has an output, and the AND circuit 46, which also receives the output of the timer 49 after the reaction relay HR has recovered, has an output and sets the memory circuit 40 (flip-flop), so the NOR circuit 51 is set to have an output, and at the same time, the lamp driver 52 is driven to light up the display 55. Therefore, it can be seen that there was a failure.

Next, if counter relay COR2 does not operate after counter relay COR1 operates, flip-flops 34 and 35 are not set. Also, if flip-flop 33 is set by the operation of counter relay COR1, AND circuit 4
4 has an output, and after the reaction relay HR is restored, the AND circuit 47 has an output, and the memory circuit 41
In order to set the flip-flop, the NOR circuit 51 is set to have an output, and the indicator light 56 is turned on to drive the lamp driver 53 to notify the failure.

Similarly, when counter relay COR3 does not operate after counter relays COR1 and COR2 operate, NOR circuit 51 is enabled to output, and lamp driver 54 lights up indicator lamp 57 to notify of a failure.

Note that the stored contents of the memory circuits 40, 41, and 42 can be cleared by operating the reset switch 50.

As mentioned above, even though the input conditions are set for receiving antennas A1 to A3, the corresponding switching elements, that is, counter relays COR
If any of the relays 1 to COR3 does not operate, the point corresponding to that relay can be detected and stored as a malfunction point. Note that the point of malfunction can be easily found by turning on the indicator light.

Effects of the Invention As described above, in the present invention, the operating state of the switching element for enabling and disabling each transistor is monitored, the determining means determines whether or not each transistor operates normally, and the determination result is stored. Since a fault detection circuit is provided for storing information in the means, it is possible to easily confirm a malfunctioning ground element based on the contents stored in the memory circuit.

[Brief explanation of drawings]

FIG. 1 is an embodiment of a speed checking device for an automatic train stopping device, FIG. 2 is an embodiment of an onboard device according to the present invention, and FIG. 3 is an embodiment of a speed checking circuit according to the present invention. 4 is a diagram showing an embodiment of the failure detection circuit according to the present invention, and FIG. 5 is a timing chart of electric signals according to the apparatus of the present invention. 1...Train, 2...Onboard equipment, 3...Runway,
4... Verification circuit, 5... Failure detection circuit, 20...
processing circuit, 21...timer, 22...counter,
37, 38, 39...determination circuit, 40, 41, 4
2... Memory circuit, 60... Reception control circuit, 70...
...Determination means, 80...Storage means, A1, A2, A
3... Receiving antenna, C1, C2, C3... Ground transducer, TMR... Timer relay, COR1, COR2,
COR3...Switching element.

Claims (1)

[Scope of Claims] 1. A speed check device for an automatic train stop device, which includes a plurality of reception control circuits 60, a check circuit 4, and a failure detection circuit 5 provided separately on a running path 3, wherein each reception The control circuit 60 controls the reception antennas A1, A
The receiving antennas A1, A2, A3 receive signals from the onboard device 2 of the train 1 and input them to the verification circuit 4, C3 provides the on-board device 2 with stop information from the verification circuit 4, and the verification circuit 4 is connected to the receiving antennas A1, A2, A3.
A processing circuit 20 that is switch-connected to a subsequent timer relay TMR, a timer 21 that performs a counting operation by the timer relay TMR, a counter 22 that counts the number of operations of the timer 21, and a counter 22 that counts the number of times the timer 21 operates.
One of them operates according to the count value of the ground element C.
It has switching elements COR1, COR2, and COR3 that disable the corresponding ones of C1, C2, and C3,
It outputs stop information to the ground elements C1, C2, and C3, and outputs the operating states of the switching elements COR1, COR2, and COR3 to the failure detection circuit 5. The determination means 70 inputs the signal from the checking circuit 4 and determines whether each of the circuits C1,
A speed check device for an automatic train stop device, which determines whether the operations of C2 and C3 are normal or abnormal, and stores the determination results in a storage means 80.