JPH0448775A - Semiconductor device - Google Patents

Abstract

PURPOSE:To lower a soft-error rate by a method wherein the gate width of a transfer transistor is made narrower than the gate width of a memory transistor and the threshold voltage of the transfer transistor is made higher than the threshold voltage of the memory transistor. CONSTITUTION:In order to make the threshold voltage of transfer transistors high by 0.1V as compared with the threshold voltage of memory transistors 8, the gate width of the transfer transistors 7 is designed at 1.0mum against 2.0mum for the gate width of the memory transistors 8. When the gate width of the transfer transistors 7 is set at 1.0mum against 2.0mum for the gate width of the memory transistors 8, the threshold voltage of the transfer transistors 7 can be made high as compared with that for the memory transistors 8. Thereby, a high-resistance very small electric current can be supplied to the memory transistors 8 without being leaked to the side of the transfer transistors 7, a margin is increased against the leak of a storage node of the memory transistors 8 by alpha-rays from the outside, and a soft-error rate is lowered.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a transistor in a semiconductor device.

[Conventional technology]

FIG. 3 is a circuit diagram showing a memory cell of a static RAM, FIG. 4 is a cross-sectional view of an N-channel transistor, and FIG. 5 is a front view of a partial layer of a memory cell of a static RAM.

The N-channel transistor shown in FIG.
An oxide film 2, a gate oxide film 3, a gate electrode 4, and an N-type diffusion layer 5 are formed. That is, a non-active region on the P-type semiconductor substrate 1 is selectively oxidized thickly to form an element isolation oxide film 2.
form.

Next, impurity 6 is shallowly implanted to control the threshold voltage of the N-channel transistor.

Furthermore, a thin gate oxide M3 is formed on the surface of the semiconductor substrate 1 excluding the element isolation oxide film 2, and polysilicon is deposited by CVD.
Deposit according to law. Then, the gate electrode 4 is formed by photolithography and etching.

Next, using the inter-element isolation oxide film 2 and the gate electrode 4 as a mask, N-type impurity ions are implanted, and an N-type diffusion layer 5 is formed by heat treatment.

FIG. 3 is a circuit diagram of a general high resistance load type memory cell, in which 7 is a transfer transistor;
8 is a memory transistor, 9 is a high resistance, IO is a word line, 11 is a bit line, 12 is a power supply line with voltage value VCC, and 13 is a ground line.

FIG. 5 is a pattern diagram of the element isolation oxide film 2 and the gate electrode 4. Here, the threshold voltage is determined by the transistor 7.8, assuming that the gate width of each transistor 7.8 is the same.
and 8 are set the same.

[Problem to be solved by the invention]

Since the conventional static RAM is configured as described above, there have been problems such as a high-resistance minute current leaking to the transfer transistor side and being susceptible to soft errors.

The present invention has been made in view of these points, and an object of the present invention is to obtain a semiconductor device with a low soft error rate.

[Means to solve the problem]

In order to achieve these objects, the present invention makes the gate width of the transfer transistor narrower than the gate width of the memory transistor, and makes the threshold voltage of the transfer transistor higher than the threshold voltage of the memory transistor. It is something.

[Effect]

In the semiconductor device according to the present invention, the margin against leakage of the storage node of the memory transistor due to external α rays increases, and the soft error rate decreases.

〔Example〕

FIG. 1 shows a static RAM as an embodiment of a semiconductor device according to the present invention. Figure 1 is a front view of the partial layer.
FIG. 2 is a pattern diagram of an element isolation oxide M2 and a gate electrode 4, and FIG. 2 shows an example of a narrow channel effect of a transistor. In FIG. 1, 5 is an N-type diffusion layer, 7 is a transfer transistor, and 8 is a memory transistor.

The threshold voltage of the transfer transistor 7 in FIG. 1 is compared with the threshold voltage of the memory transistor 8.
．． In order to increase the IV, the gate width of the transfer transistor 7 is designed to be 1.0 μm while the gate width of the memory transistor 8 is 2.0 μm (see FIG. 2). The manufacturing method is the same as that shown in the conventional example.

In this way, the gate width of the memory transistor 8 is 2.0μ.
The gate width of the transfer transistor 7 is set to 1.
By setting it to 0 μm, the transfer transistor 7
The threshold voltage of the memory transistor 8 can be made higher than that of the memory transistor 8. As a result, a small current with high resistance is supplied to the memory transistor 8 without leaking to the transfer transistor 7 side, increasing the margin against leakage of the storage node of the memory transistor 8 due to external alpha rays, and Error rate is reduced.

〔Effect of the invention〕

As explained above, the present invention makes the gate width of the transfer transistor narrower than the gate width of the memory transistor, and the threshold flt&voltage of the transfer transistor is made higher than the threshold (+!! voltage) of the memory transistor. This has the effect of increasing the margin against leakage of the storage node of the memory transistor due to α rays from the irradiation, and reducing the soft error rate.Furthermore, since the above threshold voltage can be set with only one impurity implantation, This has the effect of reducing the soft error rate without increasing the number of masks.

[Brief explanation of drawings]

FIG. 1 is a front view showing an embodiment of a semiconductor device according to the present invention, FIG. 2 is a graph showing an example of the narrow channel effect of a transistor, FIG. 3 is a circuit diagram showing a static RAM memory cell, and FIG. is a cross-sectional view of an N-channel transistor, and FIG. 5 is a static RA as a conventional semiconductor device.
FIG. 3 is a front view of a partial layer of a memory cell of M; 2... Inter-element isolation oxide film, 4... Gate electrode, 5...
...N-type diffusion layer, 7...transfer transistor,
8...Memory transistor.

Claims (1)

[Claims] In a semiconductor device having a transfer transistor and a memory transistor, the gate width of the transfer transistor is made narrower than the gate width of the memory transistor,
A semiconductor device characterized in that the threshold voltage of a transfer transistor is higher than the threshold voltage of a memory transistor.