JPH0448820A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To quicken the level conversion without increase in a delay time by providing a level conversion function and a signal holding function on a level conversion means and activating either the level conversion function or the signal holding function in response to an internal synchronizing signal. CONSTITUTION:A level conversion circuit 20 is provided with PMOS transistors(TRs) 401-404, 422, 423 and NMOS TRs 301, 302. For example, when a clock signal CLK is at an L level and a clock signal CLK' is at an H level, a TR 402 is turned on and a TR 423 is turned off. Thus, no current flows to the TRs 402, 403. Thus, the data holding function consisting of the TRs 402, 403, 301, 302 is lost and the level conversion function is activated. When the clock signal CLK is at an H level and the clock signal CLK' is at an L level conversely, the operation is opposite to above-mentioned operation. Thus, the level conversion function attained with the TRs 401, 404, 301, 302 is lost and the data holding function is activated.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit, and particularly to a BiCMO3
Related to synchronous semiconductor integrated circuits to which technology can be applied.

[Prior Art] Synchronous semiconductor integrated circuits in which input and output signals are controlled by internal synchronization signals have been developed. On the other hand, in order to obtain a semiconductor integrated circuit capable of high-speed operation and low power consumption, bipolar transistors and M
A composite integration technology has been developed in which OSFETs are integrated on the same chip. This composite integration technology is BiCMO
This is called 3 techniques.

As an example of a synchronous semiconductor integrated circuit, a self-time random access memory (hereinafter referred to as STRAM) is shown in FIG. This STRAM is, for example,
It is disclosed in No. 9-124075 and Japanese Unexamined Patent Publication No. 175286/1986.

STRAM is a synchronous RAM whose input and output signals are controlled by a clock signal, and is commonly used in that the write operation is initiated by the clock signal and the write pulse is automatically generated internally. It is different from asynchronous RAM.

In actual memory systems, skinny occurs in input signals such as addresses, so it is necessary to lengthen the cycle time to prevent malfunctions.

In contrast, in STRAM, the input and output signals are held in a data holding circuit, and the input and output operations are controlled by a clock signal, so even if the input signal is skewed, there is no problem with signal skinny at the system level. There is no need to consider.

In FIG. 9, STRAM receives an address signal ADD and input data DIN applied from the outside.

Write enable signal WE and chip select signal■
The input data holding circuit 1 temporarily holds the output data from the multiplexer 2, and the output data holding circuit 3 temporarily holds the output data from the multiplexer 2.

The STRAM also includes an internal clock generation circuit 4 and a write pulse generation circuit 5. Internal clock generation circuit 4
receives an external clock signal CLKO and generates an internal clock signal CLKI that controls data acquisition and retention in the input data holding circuit 1 and the output data holding circuit 3. The write pulse generation circuit 5 receives an internal clock signal C.
A predetermined write pulse is generated at a predetermined timing in response to LKI, a write enable signal WE, and a chip select signal.

Address signal ADD held in input data holding circuit 1
is applied to row decoder 6a and column decoder 6b at a predetermined timing in response to internal clock signal CLKI. Memory cell array 7 includes a plurality of memory cells arranged in a matrix in a plurality of rows and columns. Row decoder 6a and column decoder 6b select memory cells in memory cell array 7 in response to address signals. Input data DIN held in input data holding circuit 1 is provided to sense amplifier/write driver 8 and multiplexer 2 in response to internal clock signal CLKI. During writing, in response to a write pulse from the write pulse generation circuit 5,
The sense amplifier number write driver 8 is controlled, and data is written into the selected memory cell. When it comes out one after another,
Sense amplifier/write driver 8 is controlled in response to a write pulse from write pulse generation circuit 5, and data is read from the selected memory cell. The data amplified by the sense amplifier is provided to an output data holding circuit 3 via a multiplexer 2. Output data holding circuit 3 temporarily holds data and outputs the data to the outside as output data DOUT in response to internal clock signal CLKI.

When a system is configured using a plurality of STRAMs, even if there is a skew in input signals such as address signals, data is simultaneously loaded into the plurality of STRAMs in response to an external clock signal.

Therefore, it is possible to suppress variations in data output timing to variations in access time of a single RAM itself. In this way, by using STRAM, the system cycle time can be set without considering the skew of the input signal given to each STRAM.
The cycle time of the system can be reduced compared to when M is used.

It is conceivable to apply BiCMO8 technology to such STRAM. In this case, a bipolar circuit is used for the input/output circuit, and a CMO8 is used for the memory cell and its peripheral circuit.
Use circuits. This makes it possible to realize a large-capacity STRAM having an ECL (emitter-coupled logic) interface, which is difficult to realize using only bipolar technology.

Figure 10 shows a STRAM with an ECL interface.
FIG. 2 is a diagram showing an example of a configuration from an ECL buffer circuit to a decoder when BiCMO5 technology is applied to the system.

The ECL buffer circuit 10a receives an input signal Vin at an ECL level, and outputs complementary output signals a, a, and a signal at an ECL level.
Output a. The level conversion circuit 20 receives complementary output signals a and a at the ECL level and outputs complementary output signals a and b at the MOS level. Normally, the load driving capability of the level conversion circuit 20 is small, so a driver circuit 30 is connected to the output side of the level conversion circuit 20. The driver circuit 30 outputs MOS level output signals b.
, and outputs a complementary output signal C1τ to drive the decoder 40 having a large load. The decoder 40 is provided with a plurality of ECL input buffer circuits 82, and in FIG.
Only 0 is shown.

The ECL human cover 7 circuit 10a includes bipolar transistors 101 to 103, 105, and 106.

113 to 116, resistors 201, 202 and constant current source 9
Including 01-904. Transistor 101 and constant current source 901 constitute an input section. The base of the transistor 101 receives the ECL level input signal Vin, the collector is connected to the ground terminal 11 receiving the ground voltage Vcc, and the emitter is connected via the constant current source 901 to the power supply terminal 12 receiving the negative voltage vEE. .

Transistors 102 and 103 constitute an input current switch. The base of transistor 102 is connected to the emitter of transistor 101, and the collector is connected to resistor 201.
It is connected to the ground terminal 11 via. The base of transistor 103 receives reference voltage vBB, and the collector is connected to ground terminal 11 via resistor 202. Transif.

The emitters of transistors 102 and 103 are commonly connected to the collector of transistor 113. The base of the transistor 113 receives the clock signal CLK, and the emitter is connected to the power supply terminal 12 via a constant current source 902.

Transistors 105, 106 and constant current sources 903, 9
04 constitutes the output section. The base of the transistor 105 is connected to the collector of the transistor 102, the collector is connected to the ground terminal 11, and the emitter is connected to the constant current source 903.
It is connected to the power supply terminal 12 via. The base of the transistor 106 is connected to the collector of the transistor 103, the collector is connected to the ground terminal 11, and the emitter is connected to the power supply terminal 12 via a constant current source 904.

Transistors 114 and 115 constitute a data holding current switch. The base of transistor 114 is connected to the emitter of transistor 105, and the collector is connected to the collector of transistor 103. The base of transistor 115 is connected to the emitter of transistor 106, and the collector is connected to the collector of transistor 102. The emitters of transistors 114 and 115 are commonly connected to the collector of transistor 116. The base of transistor 116 is connected to clock signal CL.
K, and its emitter is connected to a constant current source 902.

Complementary output signals a, a are taken out from the emitters of transistors 105 and 106.

Note that the clock signals CLK and CLK are complementary signals and are generated from an internal clock generation circuit.

Normally, the ground voltage VCC is set to OV, and the negative voltage VEt
jt Set to 4.5V or -5.2V. EC
The @H” level of the L level input signal Vin is normally −〇.
9V, and the IIL'' level is normally -1.7■.

The reference voltage VBB is the base voltage of the transistor 102.
The voltage is set to be an intermediate voltage between the "H" level and the "L" level.

Next, the ECL Jin Kabaka 82 Fufu creation shown in FIG. 10 will be explained.

When clock signal CLK is at “L” level and clock signal CLK is at “H” level, transistor 1
13 is turned on and transistor 116 is turned off. As a result, the transistor 102.

The input current switch composed of transistors 103 operates, and the data holding current switch composed of transistors 114 and 115 does not operate.

In this case, if the input signal Vin is at "H" level, the transistor 102 is turned on and the transistor 103 is turned off. As a result, the base voltage of transistor 105 becomes "L" level, and the base voltage of transistor 106 becomes "H" level. As a result, the output signal a (OR output) is “H”.

level, and the output signal a (NOR output) becomes "L" level.

Conversely, when the input signal Vin is at the "L" level, the transistor 102 is turned off and the transistor 103 is turned on. As a result, the base voltage of the transistor 105 is “
The base voltage of the transistor 106 is “H” level, and the base voltage of the transistor 106 is “
As a result, the output signal a becomes "L" level, and the output signal τ becomes "H" level.

When clock signal CLK is at "H" level and clock signal CLK is at "L" level, transistor 113 is turned off and transistor 116 is turned on. As a result, the input current switch composed of transistors 102 and 103 does not operate, and the transistor 11
The data holding current switch consisting of 4.115 operates. As a result, the states of the output signals a, a are held regardless of the state of the input signal Vin.

In this way, the ECL input buffer circuit 10a shown in FIG.
, a, and the clock signals CLK, C
It has a data holding circuit that is selectively switched in response to LK.

FIG. 11 shows a STRAM with an ECL interface.
FIG. 7 is a diagram showing another example of the configuration from an ECL buffer circuit to a decoder when BiCMO8 technology is applied to the ECL buffer circuit.

The ECL input buffer circuit 10b shown in FIG. 11 differs from the ECL input buffer circuit 10a shown in FIG. 10 in that a data holding circuit consisting of transistors 114-116 is not provided. Therefore, ECL
The human buffer circuit 10b derives complementary output signals a, a according to the input signal Vin. Level conversion circuit 2
A CMOS data holding circuit 50 is connected between 0 and the driver circuit 30.

The CMOS data holding circuit 50 includes NMOS transistors 313, 314, PMO8) transistors 415 and 416.
and an inverter 23; a transfer gate; and a cross-coupled inverter 21.
22. CMO8) The transfer gate receives the output signals S and B of the level conversion circuit 20 and is controlled by the clock signal CLK. Output signals d, d of cross-coupled inverters 21 and 22 are provided to a driver circuit 30.

Note that the clock signal CLK is generated from an internal clock generation circuit.

When the clock signal CLK is at the "H" level, the output signals S and B of the level conversion circuit 20 are output from the inverter 21 cross-coupled via the CMOS transfer gate.
．． 22 will be informed. Therefore, the output signal d of the CMOS data holding circuit 50.

d changes according to the input signal Vin.

When the clock signal CLK is at the "L" level, the output signals S and B of the level conversion circuit 20 are not transmitted to the cross-coupled inverters 21 and 22. Therefore, C
The states of the output signals d, d of the MOS data holding circuit 50 are held regardless of the state of the input signal Vin. The driver circuit 30 receives the output signals d and d, outputs an output signal C2τ, and drives the decoder 40 having a large load.

Note that each of the inverters 21 and 22 includes a PMO transistor 417 and an NMOS transistor 315 connected between the ground terminal 11 and the power supply terminal 12, as shown in FIG.

For example, the level conversion circuit 20 is shown in FIGS. 13 and 14.
A circuit as shown in FIG. 1 and FIG. 15 has been proposed.

The level conversion circuit shown in FIG.
No. 6, Japanese Patent Application Laid-open No. 123825/1983, and the like.

The level conversion circuit shown in FIG. 13 includes first and second current mirror circuits connected between a ground terminal 11 and a power supply terminal 12. The first current mirror circuit is a PMO
8) Includes transistors 418 and 419 and NMOS transistors 316 and 317. The second current mirror circuit includes PMOS transistors 420, 421 and NMO
8) Contains transistors 318 and 319. transistor 4
The output signal a of the ECL buffer circuit is applied to the gates of transistors 19 and 420, and the output signal i is applied to the gates of transistors 418 and 421. transistor 421
A MOS level output signal S is taken out from the connection point between the transistor 419 and the transistor 319, and a MOS level output signal S is taken out from the connection point between the transistor 419 and the transistor 317.

The “H” level of the output signals S and b is the ground voltage v0°, and the “L” level is the negative voltage VI! , is.

For example, when the output signal a becomes "H" level and the output signal i becomes "L level", the transistors 418 and 42
1 turns on and transistors 419 and 420 turn off.

As a result, transistor 317 is turned on and transistor 319 is turned off. Therefore, the output signal is “H”
level (ground voltage Vcc), and the output signal is “L#
level (becomes negative voltage Vp1).

The level conversion circuit shown in FIG. 14 consists of 1. Fukushi
et, al,: “A 256Kbit E
CLRAM with redundancy19
88 l5SCC, pp, 134-135 (F e
b, 1988).

The level conversion circuit in FIG. 14 consists of PMOS transistor 4
05-408, NMo5 transistors 303-306 and bipolar transistors 109.110. A transistor 405 is connected between the ground terminal 11 and the power supply terminal 12.
．． 406 are connected in series. Further, transistors 407 and 408 are connected in series between the ground terminal 11 and the power supply terminal 12.

The output signal a of the ECL human cover 7 circuit is the transistor 4.
The output signal i is applied to the gates of transistors 405 and 408. The connection point between transistor 405 and transistor 406 is connected to the base of transistor 109, and
3 to the power supply terminal 12. transistor 4
The connection point between 07 and transistor 408 is transistor 1
10 and to the power supply terminal 12 via a transistor 306.

The collector of the transistor 109 is connected to the ground terminal 11, and the emitter is connected to the power supply terminal 1 via the transistor 304.
Connected to 2. The collector of transistor 110 is connected to ground terminal 11, and the emitter is connected to power supply terminal 12 via transistor 305. Further, the emitter of transistor 109 is connected to the gates of transistors 305 and 306, and the emitter of transistor 110 is connected to the gates of transistors 303 and 304. An output signal S is taken from the emitter of transistor 109, and an output signal S is taken from the emitter of transistor 110.

Output signal a becomes “H” level and output signal a becomes “L” level.
" level, transistors 405 and 408 turn on, and transistors 406 and 407 turn off. As a result, transistor 109 starts to turn on, and transistor 1
10 starts to turn off.

Then, the emitter of transistor 109 is rapidly charged, the gate voltages of transistors 305 and 306 rise, and these transistors are turned on. Therefore, transistor 110 and transistors 303 and 304 are turned off.

Therefore, the output signal is at "H" level (ground voltage Vc
c Vr), and the output signal S becomes "L" level (negative voltage VEI).

Here, vf represents the base-emitter voltage of a bipolar transistor when almost no current flows through the transistor.

The level conversion circuit shown in FIG. 15 is based on the previously filed patent application No.
-127113.

The level conversion circuit in FIG. 15 consists of PMO3) transistor 4
11.414 and NMO8) transistors 309-31
Contains 2. Transistor 411°309 is the first CMO
The transistors 414 and 310 constitute a second CMO8 inversion circuit. The output signal a of the ECL buffer circuit is applied to the gate of transistor 414.310, and the output signal i is applied to the gate of transistor 411.30.
Given to 9 gates. The connection point between the transistor 411 and the transistor 309 is connected to the gate of the transistor 312, and the connection point between the transistor 414 and the transistor 310 is connected to the gate of the transistor 312.
The connection point with is connected to the gate of the transistor 311. The sources of transistors 411 and 414 are connected to ground terminal 11, and the sources of transistors 311 and 312 are connected to power supply terminal 12. A MOS level output signal is taken out from the connection point between transistor 411 and transistor 309, and is output from transistor 414 and transistor 3.
A MOS level output signal is output from the connection point with 10.

Output signal a becomes “H” level and output signal i becomes “L” level.
When the temperature becomes low, transistors 411 and 310 are turned on, and transistors 309 and 414 are turned off. As a result, the transistor 312 turns on, and the transistor 311
turns off. Therefore, the output signal is “H” level (
ground voltage Vcc), and the lower output signal goes to “L” level (
becomes a negative voltage vE2).

In this case, since the potential of the output signal a is approximately -0.8V, the transistor 414 is sufficiently non-conductive. Therefore, no through current flows through the second CMOS inversion circuit constituted by the transistors 414 and 310. Also, since the potential of the output signal i is -1.8v,
Transistor 309 is not completely non-conductive.

However, at this time, since the potential of the output signal S has decreased to the negative voltage V02, the transistor 311 is completely non-conductive. Therefore, transistor 411.30
No through current flows through the first CMOS inversion circuit constituted by 9.

[Problems to be Solved by the Invention] In the ECL buffer circuit 10a shown in FIG.
Transistor 114,1 in the output section consisting of 03,904
A data holding current switch consisting of 15 is connected. Therefore, the load capacitance of the output node from which the output signals a and a are derived is large. As a result, there is a problem that the delay time from the input signal Vin to the output signals B, a is longer than that of the ECL human cover circuit 10b shown in FIG.

Furthermore, in order to operate the level conversion circuit at high speed while maintaining its sensitivity, it is necessary to increase the amplitude of the input signal to the level conversion circuit to some extent. However, the 10th
In the ECL human cover 7 circuit 10a shown in the figure, a transistor 11 constituting a current switch for data retention
To avoid saturation of 4.115, the output signal a, a
It is not possible to increase the amplitude very much. Therefore, the delay time from the output signals a, i to the output signal "s" in the level conversion circuit 20 shown in FIG.
This is larger than the delay time in the level conversion circuit 20 shown in FIG.

On the other hand, the ECL human cover 7 circuit 10 shown in FIG.
Since the circuit b does not have a data holding current switch, the delay time from the input signal Vin to the output signals a and a is small. Furthermore, since saturation of the transistors does not need to be considered, the amplitude of the output signals a, a of the ECL buffer circuit 10b can be increased. Therefore, the level conversion circuit 20 can be operated at high speed.

However, the level conversion circuit 20 and the driver circuit 30
Since the CMOS data holding circuit 50 is connected between the output signals of the level conversion circuit 20,
There will be a delay time until the output signals d and d of the MOS data holding circuit 50 are reached.

This delay time is calculated by the ECL manual power 3 shown in FIG.
This is even greater than the increased delay time due to having a 77-titch.

As described above, in the circuit configurations shown in FIGS. 10 and 11, a delay time occurs from the input signal Vin applied to the ECL buffer circuit to the output signal applied to the driver circuit 30.

An object of the present invention is to convert an input signal of a first logic level to a second logic level.
In semiconductor integrated circuits that have the function of converting to a logic level signal and the holding function of holding the level-converted signal, the signal holding function eliminates the delay time and enables high-speed level conversion operation. It is to be.

[Means for Solving the Problems] A semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit equipped with means for generating an internal synchronization signal, and includes input buffer means and level conversion means.

The input buffer means receives an input signal at a first logic level. The level converting means receives the output signal of the input buffer means and has a level converting function of level converting the output signal to a signal of a second logic level, and a signal holding function of holding the level converted signal, Either the level conversion function or the signal holding function is selectively activated in response to the internal synchronization signal.

[Function] In the semiconductor integrated circuit according to the present invention, the level conversion means has a level conversion function and a signal holding function, and either the level conversion function or the signal holding function is selectively performed in response to an internal synchronization signal. is activated. When the level conversion function of the level conversion means is activated in response to the internal synchronization signal, the output signal of the input buffer means is level converted to a signal of the second logic level. When the signal holding function of the level conversion means is activated in response to the internal synchronization signal, the level converted signal is held.

In this way, the function of the level conversion means is selectively activated in response to the internal synchronization signal, so there is no increase in delay time due to the signal holding function, and the level conversion operation can be performed at high speed. becomes.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of a first embodiment of the present invention.

In FIG. 1, an ECL driver circuit 10 is connected to a driver circuit 30 via a level conversion circuit 20. Driver circuit 30 is connected to decoder 40. The configuration of the ECL buffer circuit 10 is similar to the configuration of the ECL buffer circuit 10b shown in FIG.

The level conversion circuit 20 includes PMOS transistors 401 to 401.
404, 422, 423 and NMOS transistor 3
Contains 01.302. The source of transistor 422 is connected to ground terminal 11, the drain is connected to node N3, and the gate receives tarok signal CLK. The source of the transistor 423 is connected to the ground terminal 11, the drain is connected to the node N4, and the gate is connected to the clock signal CLK.
receive.

Tarock signals CLK and CLK are complementary signals and are generated by an internal clock generation circuit (see FIG. 9).

The source of transistor 401 is connected to node N3,
The drain is connected to node N1. transistor 40
The source of 2 is connected to node N4, and the drain is connected to node N1. The drain of the transistor 301 is connected to the node N1, and the source is connected to the power supply terminal 12.

The source of transistor 403 is connected to node N4,
The drain is connected to node N2. transistor 40
The source of 4 is connected to node N3, and the drain is connected to node N2. The drain of transistor 302 is connected to node N2, and the source is connected to power supply terminal 12.

The gates of transistors 402 and 301 are connected to node N2, and the gates of transistors 403 and 302 are connected to node N1. E at the gate of the transistor 401
An output signal a of the CL buffer circuit 10 is applied, and an output signal i is applied to the gate of the transistor 404. An output signal S is taken out from the node N1, and an output signal S is taken out from the node N2.

The transistors 401 to 404, 301, and 302 constitute a data holding circuit having a level conversion function and a data holding function. Level conversion function is transistor 401
, 404, 301, 302, and the data holding function is achieved by transistors 402, 403, 301, 302. These functions are selectively activated by transistors 422 and 423.

Next, the operation of the embodiment shown in FIG. 1 will be explained.

When the input signal Vin is at the "H" level, the transistor 102 is turned on and the transistor 103 is turned off. Therefore, the output signal a (OR1g output) goes to the "H" level, and the output signal a (NOR output) goes to the "L" level.

Conversely, if the input signal Vin is "L" level, the transistor 102 is turned off and the transistor 103 is turned on.As a result, the output signal a becomes "L'" level and the output signal terminal becomes "H" level. Become.

When clock signal CLK is at "L" level and clock signal CLK is at "H" level, transistor 422 is turned on and transistor 423 is turned off. Therefore, no current flows through the transistors 402 and 403. Therefore, transistors 402, 403, 301
, 302 is lost, and the level conversion function achieved by transistors 401, 404, 301, 302 is activated.

Output signal a is at “H” level and output signal a
When the level is "L", the transistor 401 is turned off and the transistor 404 is turned on.

Therefore, the output signal is at "H" level (ground voltage Vcc
), and the output signal becomes the "L" level negative voltage VEI.

Conversely, when output signal a is at "L" level and output signal T
is at "H" level, transistor 401 is turned on and transistor 404 is turned off. Therefore, the output signal is "L" level negative voltage V. 0), and the output signal becomes "H" level (ground voltage Vce).

In this way, the transistors 401, 404° 301
．． 302, the level conversion function achieved by E.
CL level output signals a, a are converted into MOS level output signals s, b.

When the clock signal CLK is at the "H" level and the clock signal CLK>("L" level), the transistor 422 is turned off and the transistor 423 is turned on.

Therefore, no current flows through the transistors 401 and 404. Therefore, transistors 401, 404, 301
, 302 is lost, and the data holding function achieved by transistors 402, 403, 301, and 302 is activated.

As a result, the state of output signals a and a is at node Nl.

It is not transmitted to N2, and the states of output signals S and B are maintained.

FIG. 2 is a circuit diagram showing the configuration of a second embodiment of the invention.

The ECL buffer circuit 10 shown in FIG. 2 is different from the ECL buffer circuit shown in FIG. and that a bipolar transistor 107 and a constant current source 905 are further provided.

The collector of transistor 104 is connected to ground terminal 11 via resistor 210, the emitter is connected to constant current source 902, and the base receives clock signal CLK. Here, the "H" level of the clock signal CLK is set higher than the "H" level of the base voltage of the transistor 102,
The “L” level of the clock signal CLK is the reference voltage VBB.
is set lower.

The collector of the transistor 107 is connected to the ground terminal 11, the emitter is connected to the power supply terminal 12 via the constant current source 905, and the base is connected to the collector of the transistor 104. A control signal e is taken out from the emitter of transistor 107.

The difference between the level conversion circuit 20 shown in FIG. 2 and the level conversion circuit 20 shown in FIG.
2 is removed and the sources of transistors 401 and 404 are directly connected to ground terminal 11. A control signal e having an opposite phase to the clock signal CLK is applied to the gate of the transistor 423.

When clock CLK is at "L" level, transistor 104 is turned off. As a result, the control signal e becomes "H" level. Therefore, transistor 423 is turned off,
No current flows through transistors 402 and 403. Therefore, the data retention function achieved by transistors 402, 403, 301, and 302 is lost. As a result,
In the same way as in the embodiment of FIG. 1, the output signals a, a
is converted into MOS level output signals S and B by the level conversion function of the level conversion circuit 20.

When the clock CLK is at "H" level, the transistor 104 is turned on. As a result, the control signal e becomes "L" level, and the transistor 423 is turned on. In addition, the output signals a and a are both at "H" level regardless of the state of the input signal Vin, and the transistors 401 and 40
2 turns off. As a result, transistors 402, 403
, 301.302 is activated, and the transistors 401, 404, 301.30
The level conversion function achieved by 2 is lost. Therefore, the states of output signals S and B are maintained.

Since the ECL buffer circuit 10 in the embodiments of FIGS. 1 and 2 does not have a data holding circuit constituted by an ECL circuit, the output signal a,
The delay time to a is small, and the level conversion circuit 2
It becomes possible to obtain the amplitude of the output signals a and a that are sufficient to operate 0 at high speed. Also, Figures 1 and 2
In the level conversion circuit 20 shown in the figure, since level conversion is performed using the potential amplification function of the data holding circuit, there is no increase in delay time due to the data holding function.

3 to 8 are circuit diagrams showing modified examples of the level conversion circuit 20.

The level conversion circuit of FIG. 3 includes a bipolar transistor 10 in the level conversion circuit 20 shown in FIGS. 1 and 2.
7.108 and resistors 203 and 204 are added. The base of transistor 107 is transistor 40
1, its collector is connected to the ground terminal, and its emitter is connected to the drain of transistor 402.

Resistor 203 is connected between the base and emitter of transistor 107. The base of transistor 108 is connected to the drain of transistor 404, the collector is connected to the ground terminal, and the emitter is connected to the drain of transistor 403. Resistor 204 is connected between the base and emitter of transistor 108.

In the level conversion circuit of FIG. 3, the transistor 10
7.108 and the resistors 203 and 204 make the switching of the output signals S and τ faster, and the
The load driving capacity of b increases.

The level conversion circuit shown in FIG. 4 includes a PMO8) transistor 409°410.42
4.425 is added.

The source of the transistor 424 is connected to the ground terminal 11, the drain is connected to the sources of the transistors 405 and 407, and the gate receives the clock signal CLK. Transistor 409 is connected between the drain of transistor 425 and the drain of transistor 304, and transistor 410 is connected between the drain of transistor 425 and the drain of transistor 305. The source of transistor 425 is connected to ground terminal 11, and the gate receives clock signal CLK. transistor 409.30
The gate of 4 is connected to the drain of transistor 410. The gate of transistor 410.305 is connected to the drain of transistor 409.

Transistors 409, 410, 304, 305 accomplish the data retention function. When the clock signal CLK is at the "H" level and the clock signal CLK is at the "L" level, the transistor 424 is turned off and the transistor 425 is turned off.
turns on. Therefore, output signals S and B are held by the data holding function constituted by transistors 409, 410, 304, and 305.

The level conversion circuit shown in FIG. 5 is obtained by adding NMOS transistors 307 and 308 to the level conversion circuit shown in FIG. Transistor 307 is transistor 10
9 and the drain of transistor 303, and transistor 308 is connected between the base of transistor 110 and the drain of transistor 306. An output signal T is applied to the gate of the transistor 307, and an output signal a is applied to the gate of the transistor 308.

In the level conversion circuit of FIG.
7,308 is controlled by output signals a and a. As a result, current flows transiently from the transistor 405 to the transistor 303 or the transistor 4
07, the current flowing transiently into the transistor 306 decreases. As a result, the switching of the output signals S and B becomes faster.

The level conversion circuit shown in FIG. 6 is obtained by removing the NMOS transistors 303 and 306 from the level conversion circuit shown in FIG. 4, and adding resistors 205 and 206. resistance 2
05 is connected between the base and emitter of transistor 109, and resistor 206 is connected between the base and emitter of transistor 110.

In the level conversion circuit of FIG. 6, the transistor 10
9 and 110 are controlled by transistors 304 and 305 via resistors 205 and 206, respectively.

The level conversion circuit shown in FIG. 7 includes a PMO8) transistor 412°413.42
6.427 is added.

The source of the transistor 426 is connected to the ground terminal 11, the drain is connected to the sources of the transistors 411 and 414, and the gate receives the clock signal CLK. Transistor 412 is connected between the drain of transistor 427 and the drain of transistor 309, and transistor 413 is connected between the drain of transistor 427 and the drain of transistor 310. The source of transistor 427 is connected to ground terminal 11, and the gate receives clock signal CLK. The gate of transistor 412 is connected to the drain of transistor 413, and the gate of transistor 413 is connected to the drain of transistor 412. Transistors 412, 413.309~
312 accomplishes the data retention function.

If the clock signal CLK is at “H” level and the clock signal CLK is at “L” level, the transistor 426
is turned off and transistor 427 is turned on. Therefore, output signals S and B are held by the data holding function.

The level conversion circuit shown in FIG. 8 is obtained by adding bipolar transistors 111 and 112 and resistors 207 and 208 to the level conversion circuit shown in FIG. The base of the transistor 111 is connected to the drain of the transistor 411, the collector is connected to the ground terminal 11, and the emitter is connected to the drain of the transistor 412. resistance 2
07 is connected between the base and emitter of transistor 111. The base of transistor 112 is connected to the drain of transistor 414, and the collector is connected to ground terminal 1.
1, and its emitter is connected to the drain of transistor 413. Resistor 208 is connected between the base and emitter of transistor 112.

In the level conversion circuit of FIG.
1 and 112 and resistors 207 and 208, the switching of the output signals S and B becomes faster, and the load driving ability of the output signals S and B increases.

In addition, by connecting the nodes to which the drains of transistors 422, 424, and 426 of the level conversion circuits shown in FIGS. 3 to 8 are connected to the ground terminal 11 and removing those transistors, the ECL circuit shown in FIG. It is also possible to apply the control signal e of the buffer circuit 10 to the gates of the transistors 423, 425, and 427.

In this way, the level conversion circuit 20 shown in FIG.
Even if the level conversion circuits shown in FIGS. 3 to 8 are replaced, the same effects as in the embodiments shown in FIGS. 1 and 2 can be obtained. Note that level conversion circuits with configurations other than those shown in FIGS. 1 to 8 may be used as long as they have a level conversion function and a data retention function and can selectively activate these functions. A similar effect can be obtained.

Further, in the above embodiment, the present invention is applied to a case where BiCMO8 technology is applied to a STRAM having an ECL interface, but the present invention is not limited to a STRAM, and input or output signals are controlled by an internal synchronization signal. It can be applied to all synchronous semiconductor integrated circuits.

[Effects of the Invention] As described above, according to the present invention, the level conversion means has a level conversion function and a signal holding function, and either one of these functions is activated in response to an internal synchronization signal. Therefore, it is possible to obtain a semiconductor integrated circuit that can perform a level conversion operation at high speed without increasing delay time due to having a data holding function.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a semiconductor integrated circuit according to a first embodiment of the present invention. FIG. 2 is a circuit diagram showing the configuration of a semiconductor integrated circuit according to a second embodiment of the invention. Figure 3, Figure 4, Figure 55! ! FIG. 6, FIG. 7, and FIG. 8 are circuit diagrams each showing a modification of the level conversion circuit. FIG. 9 is a block diagram showing the configuration of STRAM. Figure 10 shows an S with an ECL interface.
1 is a circuit diagram showing an example of a conventional configuration from an ECL buffer circuit to a decoder when BiCMO8 technology is applied to TRAM; FIG. FIG. 11 is a circuit diagram showing another example of the conventional configuration from an ECL buffer circuit to a decoder when BiCMO3 technology is applied to a STRAM having an ECL interface. FIG. 12 is a specific circuit diagram of the inverter. Figures 13, 14 and 1
FIG. 5 is a specific circuit diagram of the level conversion circuit shown in FIGS. 10 and 11. In the figure, 10 is an ECL buffer 7 circuit, 20 is a level conversion circuit, 11 is a ground terminal, 12 is a power supply terminal, 10
1 to 106 are bipolar transistors, 201, 202
is a resistor, 301.302 is an NMO8) transistor, 40
1 to 404,422°423 are PMOS transistors,
901 to 905 are constant current sources, CLK is a clock signal, Vcc is a ground voltage, VEI! is a negative voltage, vBB is a reference voltage, V-in is an input signal, a and a are ECL level output signals, and b and b are MOS level output signals. Note that the same reference numerals in each figure indicate the same or corresponding parts. Figure Figure Figure Bow Figure 10 Figure 10 To the memory cell array Figure 13 Figure 14 Figure 15

Claims (1)

[Scope of Claims] A semiconductor integrated circuit comprising means for generating an internal synchronization signal, comprising input buffer means for receiving an input signal of a first logic level, and receiving an output signal of the input buffer means and outputting the output signal. It has a level conversion function that converts the level of a signal to a signal of a second logic level, and a signal holding function that holds the level converted signal, and the level conversion function and the signal holding function are performed in response to the internal synchronization signal. A semiconductor integrated circuit equipped with level conversion means for selectively activating one of the functions.