JPH0448819A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To contrive a high-speed level conversion by providing a level conversion function and a signal holding function on a level conversion means and switching the level conversion function and the signal holding function based on the state of an output signal of an input buffer means. CONSTITUTION:A level conversion circuit 20 is provided with PMOS transistors(TRs) 401-404 and NMOS TRs 301, 302. For example, when an input signal Vin is at an H level, a TR 102 is turned on and a TR 103 is turned off. Thus, an output signal (a) goes to an H level and an output signal a' goes to an L level. Thus, the TR 401 is turned off and the TR 404 is turned on in the level conversion circuit 20. Conversely, when the input signal Vin is at an L level, the TRs are turned on/off opposite to the above-mentioned operation. Thus, the state of output signals (b), b' is held by the data holding function composed of the TRs 402, 403, 301, 302.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit, and in particular, to a BiCMO8
Related to synchronous semiconductor integrated circuits to which technology can be applied.

[Prior Art] Synchronous semiconductor integrated circuits in which input and output signals are controlled by internal synchronization signals have been developed. On the other hand, in order to obtain a semiconductor integrated circuit capable of high-speed operation and low power consumption, bipolar transistors and M
A composite integration technology has been developed in which OSFETs are integrated on the same chip. This composite integration technology is BjCMO
This is called 3 techniques.

As an example of a synchronous semiconductor integrated circuit, a self-time random access memory (hereinafter referred to as STRAM) is shown in FIG. This STRAM is, for example,
It is disclosed in No. 9-124075 and Japanese Patent Application Laid-Open No. 175286/1986.

STRAM is a synchronous RAM whose input and output signals are controlled by a clock signal, and is commonly used in that the write operation is initiated by the clock signal and the write pulse is automatically generated internally. It is different from asynchronous RAM.

In actual memory systems, skew occurs in input signals such as addresses, so it is necessary to lengthen the cycle time to prevent malfunctions.

In contrast, in STRAM, the input and output signals are held in a data holding circuit, and the input and output operations are controlled by a clock signal, so even if the input signal is skewed, there is no problem with signal skinny at the system level. There is no need to consider.

In FIG. 9, STRAM receives an address signal ADD and input data DIN applied from the outside.

Write enable signal WE and chip select signal C
8, and an output data holding circuit 3 that temporarily holds output data from the multiplexer 2.

The STRAM also includes an internal clock generation circuit 4 and a write pulse generation circuit 5. Internal clock generation circuit 4
receives an external clock signal CLKO and generates an internal clock signal CLKI that controls data acquisition and retention in the input data holding circuit 1 and the output data holding circuit 3. The write pulse generation circuit 5 receives an internal clock signal C.
A predetermined write pulse is generated at a predetermined timing in response to LKi, write enable signal WE, and chip select signal C8.

Address signal ADD held in input data holding circuit 1
is applied to row decoder 6a and column decoder 6b at a predetermined timing in response to internal clock signal CLKI. Memory cell array 7 includes a plurality of memory cells arranged in a matrix in a plurality of rows and columns. Row decoder 6a and column decoder 6b select memory cells in memory cell array 7 in response to address signals. Input data DIN held in input data holding circuit 1 is provided to sense amplifier/write driver 8 and multiplexer 2 in response to internal clock signal CLKI. During writing, in response to a write pulse from the write pulse generation circuit 5,
Sense amplifier/write driver 8 is controlled, and data is written into the selected memory cell. When reading,
Sense amplifier/write driver 8 is controlled in response to a write pulse from write pulse generation circuit 5, and data is read from the selected memory cell. The data amplified by the sense amplifier is provided to an output data holding circuit 3 via a multiplexer 2. Output data holding circuit 3 temporarily holds data and outputs the data to the outside as output data DOUT in response to internal clock signal CLKI.

When a system is configured using a plurality of STRAMs, even if there is a skew in input signals such as address signals, data is simultaneously loaded into the plurality of STRAMs in response to an external clock signal.

Therefore, it is possible to suppress variations in data output timing to variations in access time of a single RAM itself. In this way, by using STRAM, the system cycle time can be set without considering the skew of the input signal given to each STRAM.
The cycle time of the system can be reduced compared to when M is used.

It is conceivable to apply BiCMO8 technology to such STRAM. In this case, a bipolar circuit is used for the input/output circuit, and a CMO8 is used for the memory cell and its peripheral circuit.
Use circuits. This makes it possible to realize a large-capacity STRAM having an ECL (emitter-coupled logic) interface, which is difficult to realize using only bipolar technology.

Figure 10 shows a STRAM with an ECL interface.
FIG. 2 is a diagram showing an example of a configuration from an ECL buffer circuit to a decoder when BiCMO8 technology is applied to the system.

The ECL buffer circuit 10a receives an input signal Vin at an ECL level, and outputs complementary output signals a, a, and a signal at an ECL level.
Add a to a. The level conversion circuit 20 receives complementary 8-power signals a and a at ECL level and outputs complementary output signals a and a at MOS level. Normally, the load driving capability of the level conversion circuit 20 is small, so the level conversion circuit 20
A driver circuit 30 is connected to the output side of 0. The driver circuit 30 receives MOS level output signals S and b,
Complementary output signals C and C are outputted to drive a decoder 40 having a large load. Note that the decoder 40 is given signals from a plurality of ECL buffer circuits;
In FIG. 10, only one set of ECL manual buffer circuit 10a, Lebel conversion circuit 20 and driver circuit 30 are shown.

The ECL buffer circuit 10a includes bipolar transistors 101-103, 105, 106°113-116.
, resistors 201 and 202, and constant current sources 901 to 904. Transistor 101 and constant current source 901 constitute an input section. The base of the transistor 101 receives the ECL level input signal Vin, and the collector receives the ground voltage Vc.
c, and the emitter is connected to the ground terminal 11 which receives a negative voltage vEI! It is connected via a constant current source 901 to the power supply terminal 12 receiving the voltage.

Transistors 102 and 103 constitute an input current switch. The base of transistor 102 is connected to the emitter of transistor 101, and the collector is connected to resistor 201.
It is connected to the ground terminal 11 via. The base of transistor 1030 receives reference voltage VBB, and the collector is connected to ground terminal 11 via resistor 202. The emitters of transistors 102 and 103 are transistor 11
3 collectors in common. transistor 1
The base of 13 receives the clock signal CLK, and the emitter is connected to the power supply terminal 12 via a constant current source 902.

Transistor 105.106 and constant current source 903.9
04 constitutes the output section. The base of the transistor 105 is connected to the collector of the transistor 102, the collector is connected to the ground terminal 11, and the emitter is connected to the constant current source 903.
It is connected to the power supply terminal 12 via. The base of the transistor 106 is connected to the collector of the transistor 103, the collector is connected to the ground terminal 11, and the emitter is connected to the power supply terminal 12 via a constant current source 904.

Transistors 114 and 115 constitute a data holding current switch. The base of transistor 114 is connected to the emitter of transistor 105, and the collector is connected to the collector of transistor 103. The base of transistor 115 is connected to the emitter of transistor 106, and the collector is connected to the collector of transistor 102. The emitters of transistors 114 and 115 are commonly connected to the collector of transistor 116. The base of transistor 116 is connected to clock signal CL.
K, and its emitter is connected to a constant current source 902.

Complementary output signals 81 are taken from the emitters of transistors 105 and 106.

Note that the clock signals CLK and CLK are complementary signals and are generated from an internal clock generation circuit.

Normally, the ground voltage Vcc is set to OV, and the negative voltage VEE
is set to -4.5V or -5.2V. The “H” level of the ECL level input signal Vin is normally -0,9.
The "L" level is normally -1.7v. Reference voltage VBB is set to be an intermediate voltage between the "H" level and "L" level of the base voltage of transistor 102.

Next, the operation of the ECL buffer circuit shown in FIG. 10 will be explained.

When clock signal CLK is at "L" level and clock signal CLK is at "H" level, transistor 1
13 is turned on and transistor 116 is turned off. As a result, the input current switch composed of transistors 102 and 103 operates, and transistors 114 and 1
The data holding current switch consisting of 15 does not operate.

In this case, if the input signal Vin is at “H” level,
Transistor 102 is turned on and transistor 103 is turned off. As a result, the base voltage of transistor 105 becomes "L" level, and the base voltage of transistor 106 becomes "H" level. As a result, the output signal a (O
R output) becomes “d” level, and a force signal a (NOR
output) becomes "L" level.

Conversely, when the input signal Vjn is at the "L" level, the transistor 102 is turned off and the transistor 103 is turned on. As a result, the base voltage of the transistor 105 is “H”.
” level, and the base voltage of the transistor 106 becomes “
As a result, the output signal a becomes the "L" level, and the output signal D becomes the "H" level.

When clock signal CLK is at "H" level and clock signal CLK is at "L" level, transistor 113 is turned off and transistor 116 is turned on. As a result, the input current switch composed of transistors 102 and 103 does not operate, and the transistor 11
The data holding current switch consisting of 4.115 operates. As a result, the states of the output signals a, a are held regardless of the state of the input signal Vin.

In this way, the ECL buffer circuit 10a shown in FIG. 10 outputs the output signals a,
The clock signals CLK, C
It has a data holding circuit that is selectively switched in response to LK.

FIG. 11 shows a STRAM with an ECL interface.
ECL Jin Kabaka 8 when applying BiCMO8 technology to
It is a diagram showing another example.

The ECL buffer circuit 1ob shown in FIG. 11 differs from the ECL buffer circuit 10a shown in the first CI in that a data holding circuit consisting of transistors 114 to 116 is not provided. Therefore, ECL
The human buffer circuit 10b derives complementary output signals a, a according to the input signal vin. Level conversion circuit 2
A CMOS data holding circuit 50 is connected between 0 and the driver circuit 30.

The CMOS cheater holding circuit 50 includes NMo5 transistors 313, 314 and a PMOS transistor 41.
CMO consisting of 5, 416 and inverter 23
8) Includes transfer gates and cross-coupled inverters 21,22. CMO8) The transfer gate receives the output signals S and b of the level conversion circuit 20,
Controlled by clock signal CLK. Output signals d, d of cross-coupled inverters 21 and 22 are provided to a driver circuit 30.

Note that the clock signal CLK is generated from an internal clock generation circuit.

When the clock signal CLK is at the "H" level, the output signals -b, b of the level conversion circuit 20 are transferred to the inverter 21 cross-coupled via the CMOS transfer gate.
．． 22 will be informed. Therefore, the output signal d of the CMOS data holding circuit 50.

d changes according to the input signal Vin.

When the clock signal CLK is at the "L" level, the output signals S and B of the level conversion circuit 20 are not transmitted to the cross-coupled inverters 21 and 22. Therefore, the CLK
The states of the output signals d, d of the MOS data holding circuit 50 are held regardless of the state of the input signal Vin. The driver circuit 30 receives the output signals d and d, outputs an output signal C1τ, and drives the decoder 40 having a large load.

Each of the inverters 21 and 22 includes a PMOS transistor 417 and an NMOS transistor 315 connected between the ground terminal 11 and the power supply terminal 12, as shown in FIG.

For example, the level conversion circuit 20 is shown in FIGS. 13 and 14.
A circuit as shown in FIG. 1 and FIG. 15 has been proposed.

The level conversion circuit shown in FIG.
No. 6, Japanese Patent Application Laid-open No. 123825/1983, and the like.

The level conversion circuit shown in FIG. 13 includes first and second current mirror circuits connected between a ground terminal 11 and a power supply terminal 12. The first current mirror circuit is a PMO
S) transistors 418,419 and NMOS) transistors 316,317. The second current mirror circuit consists of PMOS transistors 420, 421 and NMO
S) Contains transistors 318 and 319. transistor 4
The output signal i is given to the gates of ECL person kabaka 8fufufu 421 to the gates 19 and 420. MOS from the connection point between transistor 421 and transistor 319
An output signal S at the level is taken out, and an output signal S at the MOS level is taken out from the connection point between the transistor 419 and the transistor 317.

The "H" level of the output signals S and b is the ground voltage VcC, and the "L" level is the negative voltage vEE.

For example, if the output signal a becomes H" level and the output signal i
becomes “L” level, transistors 418 and 421
turns on, and transistors 419 and 420 turn off. As a result, the transistor 317 is turned on and the transistor 319 is turned off. Therefore, the output signal becomes "H" level (ground voltage vcc), and the output signal becomes "L" level (negative voltage v, 2).

The level conversion circuit shown in FIG. 14 consists of 1. Fukushi
et, al, : A 256Kbit
ECLRAM with redundancy1
988 l5SCC, pp, 134-135 (F e
b, 1988).

The level conversion circuit in Fig. 14 consists of PMO8) transistor 4
05-408, NMOS transistors 303-306 and bipolar transistors 109, 110. A transistor 405 is connected between the ground terminal 11 and the power supply terminal 12.
, 406 are connected in series. Further, transistors 407 and 408 are connected in series between the ground terminal 11 and the power supply terminal 12.

The output signal i
are applied to the gates of transistors 405 and 408.

A connection point between transistors 405 and 406 is connected to the base of transistor 109, and is also connected to power supply terminal 12 via transistor 303. The connection point between transistor 407 and transistor 408 is connected to the base of transistor 110, and
06 to the power supply terminal 12.

The collector of the transistor 109 is connected to the ground terminal 11, and the emitter is connected to the power supply terminal 1 via the transistor 304.
Connected to 2. The collector of transistor 110 is connected to ground terminal 11, and the emitter is connected to power supply terminal 12 via transistor 305. Further, the emitter of transistor 109 is connected to the gates of transistors 305 and 306, and the emitter of transistor 110 is connected to the gates of transistors 303 and 304. An output signal S is taken from the emitter of transistor 109, and an output signal S is taken from the emitter of transistor 110.

Output signal a becomes “H” level and output signal i becomes “
When it becomes L” level, the transistor 405.

408 is turned on and transistors 406 and 407 are turned off. As a result, transistor 109 starts to turn on and transistor 110 starts to turn off.

Then, the emitter of transistor 109 is rapidly charged, the gate voltage of transistors 305 and 306 rises, and these transistors are turned on. Therefore, transistor 110 and transistors 303 and 304 are turned off.

The output signal is "H" level (ground voltage Vc
c Vr), and the output signal S becomes "L" level (negative voltage v0.).

Here, Vr represents the base-emitter voltage of a bipolar transistor when almost no current flows through the transistor.

The level conversion circuit shown in FIG. 15 is based on the previously filed patent application No.
-127113.

The level conversion circuit in FIG. 15 consists of a PMOS transistor 4
11,414 and NMO8) transistors 309-31
Contains 2. Transistor 411.

309 constitutes a first CMO3 inversion circuit, and transistors 414 and 310 constitute a second CMO3 inversion circuit. ECL Jin Kabaka 8 Fufufu No. a is transistor 414,
The output signal i is applied to the gates of transistors 411 and 309. transistor 4
The connection point between 11 and transistor 309 is transistor 3
The connection point between the transistor 414 and the transistor 310 is connected to the gate of the transistor 311. The sources of transistors 411.414 are connected to ground terminal 11, and the sources of transistors 311.3
12 sources are connected to the power supply terminal 12. A MOS level output signal is taken out from the connection point between transistor 411 and transistor 309, and a MOS level output signal is output from the connection point between transistor 414 and transistor 310.

Output signal a is “H” level and output signal i is “L”
When the level is reached, transistors 411 and 310 are turned on and transistors 309 and 414 are turned off. As a result, the transistor 312 is turned on and the transistor 311 is turned off. Therefore, the output signal is “H” level (
The ground voltage becomes V0°), and the output signal ■ goes to “L” level (
becomes a negative voltage (VEE).

In this case, since the potential of the output signal a is approximately -0.8V, the transistor 414 is sufficiently non-conductive. Therefore, no through current flows through the second CMO8 inversion circuit constituted by the transistors 414 and 310. Also, since the potential of the output signal i is -1.8V,
Transistor 309 is not completely non-conductive.

However, at this time, since the potential under the output signal has dropped to the negative voltage v0°, the transistor 311 is completely non-conductive. Therefore, transistor 411.30
No through current flows through the first CMO3 inversion circuit constituted by 9.

[Problems to be Solved by the Invention] In the ECL buffer circuit 10a shown in FIG.
Transistor 114.1 in the output part consisting of 03.904
A data holding current switch consisting of 15 is connected. Therefore, the load capacitance of the output node from which the output signals a and a are derived is large. As a result, the delay time from the input signal Vin to the output signals a and a is the first
There is a problem that the ECL buffer circuit 10b is larger than the ECL buffer circuit 10b shown in FIG.

Furthermore, in order to operate the level conversion circuit at high speed while maintaining its sensitivity, it is necessary to increase the amplitude of the input signal to the level conversion circuit to some extent. However, the 10th
In the ECL buffer circuit 10a shown in the figure, a transistor 11 constituting a current switch for data retention.
To avoid saturation of 4,115, the output signal a, a
It is not possible to increase the amplitude very much. Therefore, the delay time from the output signals a, a to the output signals S, ■ in the level conversion circuit 20 shown in FIG.
This is larger than the delay time in the level conversion circuit 20 shown in FIG.

On the other hand, the ECL buffer circuit 10 shown in FIG.
Since the circuit b does not have a data holding current switch, the delay time from the input signal Vin to the output signals a and a is small. Furthermore, since saturation of the transistors does not need to be considered, the amplitude of the output signals a, a of the ECL buffer circuit 10b can be increased. Therefore, the level conversion circuit 20 can be operated at high speed.

However, the level conversion circuit 20 and the driver circuit 30
Since the CMOS data holding circuit 50 is connected between the output signals of the level conversion circuit 20,
There will be a delay time until the output signals d and d of the MOS data holding circuit 50 are reached.

This delay time is calculated by the ECL manual power 8 shown in Fig. 10.
This is even greater than the increased delay time due to having a 7-titch.

As described above, in the circuit configurations shown in FIGS. 10 and 11, a delay time occurs from the input signal Vjn applied to the ECL buffer circuit to the output signal applied to the driver circuit 30.

An object of the present invention is to convert an input signal of a first logic level to a second logic level.
In a semiconductor integrated circuit that has a function of converting the signal to a logic level signal and a holding function of holding the level-converted signal, the signal holding function eliminates the delay time and enables high-speed level conversion operation. That's true.

[Means for Solving the Problems] A semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit equipped with means for generating an internal synchronization signal, and includes input buffer means and level conversion means.

The input buffer means receives an input signal at a first logic level and has an output signal controlled in response to an internal synchronization signal. The level conversion means receives the output signal of the input buffer means,
It has a level conversion function that converts the level of the output signal into a signal of a second logic level, and a signal holding function that holds the level converted signal, and has a level conversion function based on the state of the output signal of the input buffer means. and signal holding function.

[Function] In the semiconductor integrated circuit according to the present invention, the level converting means has a level converting function and a signal holding function, and the level converting function and the signal holding function are switched based on the state of the output signal of the input buffer means. It will be done. When the level conversion means is switched to the level conversion function, the output signal of the input buffer means is level converted to a signal at the second logic level.

When the output signal of the input buffer means reaches a predetermined state, the function of the level conversion means is switched to a signal holding function. Thereby, the level-converted signal is held.

In this way, the function of the level conversion means is switched based on the state of the output signal of the input buffer means, so there is no increase in delay time due to the signal holding function, and it is possible to perform the level conversion operation at high speed. Become.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of a first embodiment of the present invention.

In FIG. 1, ECL person Kabaka 3 is connected to Fufufu 0. Driver circuit 30 is connected to decoder 40. What is different from the ECL Jin Kabaka 3 fufufu circuit 10b is the internal clock generation circuit (9th
The difference is that a bipolar transistor 104 that receives a clock signal CLK from (see figure) is further provided.

The collector of transistor 104 is connected to ground terminal 11, the emitter is connected to constant current source 902, and the base receives clock signal CLK.

Here, the "H" level of the clock signal CLK is set higher than the "H" level of the base voltage of the transistor 102, and the "L" level of the clock signal CLK is set higher than the reference voltage vB.
It is set lower than B.

The level conversion circuit 20 includes PMOS transistors 401 to 401.
404 and NMO8) transistors 301 and 302. The sources of transistors 401 and 402 are ground terminal 1
1, and its drain is connected to node N1. The drain of transistor 301 is connected to node N1,
The source is connected to power supply terminal 12. transistor 40
The source of 3.404 is connected to ground terminal 11, and the drain is connected to node N2. The drain of the transistor 302 is connected to the node N2, and the source is connected to the power supply terminal 12.
connected to. Transistor 402.

The gate of transistor 301 is connected to node N2, and the gate of transistor 403.302 is connected to node N1. An output signal is applied to the gate of the transistor 401 and to the gate of the ECL transistor 404. An output signal is taken from node N1 and output to node N2.
An output signal is taken from.

Transistors 402, 403, 301, and 302 constitute a data holding circuit having a level conversion function and a data holding function, and transistors 401 and 404 switch these functions.

Next, the operation of the embodiment shown in FIG. 1 will be explained.

When the clock signal CLK is at L" level, transistor 104 is turned off. As a result, transistor 1
A current switch consisting of 02 and 103 operates.

Therefore, the output signals a and a change according to the input signal Vin at the ECL level. Input signal Vin is “H”
If the level is the same, transistor 102 is turned on and transistor 103 is turned off. Therefore, the output signal a
(OR output) becomes “H” level, and the output signal a
(NOR output) becomes "L" level. As a result, in the level conversion circuit 20, the transistor 401 is turned off and the transistor 404 is turned on. Therefore, the output signal becomes "H" level (ground voltage Vcc), and the output signal becomes "L" level negative voltage Vl! ):)become.

Conversely, if the input signal Vin is at the "L" level, the transistor 102 is turned off and the transistor 103 is turned on. As a result, the output signal a becomes "L" level and the output signal i becomes "H" level.

As a result, transistor 401 is turned on and transistor 404 is turned off. Therefore, the output signal becomes "L" level (negative voltage Vl!), and the output signal becomes "H'" level (ground voltage cc).

In this way, the transistors 401, 404° 301
．． By the level conversion function consisting of 302, EC
L-level output signals a, a are converted into MOS-level output signals s, b.

When the clock signal CLK is at the "H" level, the transistor 104 is turned on and the transistors 102 and 103 are turned off. Therefore, the current switch composed of transistors 102 and 103 does not operate. Therefore, regardless of the state of the input signal Vin, the output signals a,
Both a become "H" level. As a result, in the level conversion circuit 20, the transistors 401 and 404
are both turned off. Therefore, the transistor 402,
The state of the output signals s and b is held by the data holding function composed of 403, 301, and 302.

FIG. 2 is a circuit diagram showing the configuration of a second embodiment of the invention.

The ECL buffer circuit 10 shown in FIG. 2 is different from the ECL buffer circuit 10 shown in FIG.
Instead of providing the transistor 104 shown in FIG. 1, a clock signal CLK from an internal clock generation circuit is provided.
The point is that transistors 118 and 119 that receive the signal are provided. The collector of r transistor 118 is ground terminal 1
1, and its emitter is connected to a constant current source 903.

The collector of transistor 119 is connected to ground terminal 11, and the emitter is connected to constant current source 904. A clock signal CLK is applied to the bases of transistors 118 and 119.

In the ECL buffer circuit 10 shown in FIG. 2, the base voltage of the transistor 105 and the clock signal C
A wired OR with LK and a wired OR between the base voltage of the transistor 106 and the clock signal CLK are taken out as output signals a, a.

Note that the configuration of the level conversion circuit 20 is similar to the configuration of the level conversion circuit 20 shown in FIG.

When clock signal CLK is at "L" level, transistors 118 and 119 are turned off. Therefore, the output signals a, a change according to the input signal Vin. As a result, in the same way as in the embodiment of FIG.
, a are MO by the level conversion function of the level conversion circuit 20.
It is converted into S level output signals S and B.

When clock signal CLK is at "H" level, transistors 118 and 119 are both turned on.

Therefore, both output signals a and a are at the "H" level regardless of the state of the input signal Vin. As a result, the data holding function of the level conversion circuit 20 holds the states of the output signals S and B.

Since the ECL buffer circuit 10i and the data holding circuit constituted by the tECL circuit in the embodiments of FIGS. 1 and 2 are not provided, the output signal a is input from the input signal Vin.
, a is small, and the output signal a is sufficient to operate the level conversion circuit 20 at high speed.
It becomes possible to take the amplitude of a. Furthermore, in the level conversion circuit 20 shown in FIGS. 1 and 2, level conversion is performed using the potential amplification function of the data holding circuit, so the increase in delay time due to the data holding function is do not have.

3 to 8 are circuit diagrams showing modified examples of the level conversion circuit 20.

The level conversion circuit of FIG. 3 includes a bipolar transistor 10 in the level conversion circuit 20 shown in FIGS. 1 and 2.
7, 108 and resistors 203, 204 are added. The base of transistor 107 is transistor 40
1, its collector is connected to the ground terminal, and its emitter is connected to the drain of transistor 402.

Resistor 203 is connected between the base and emitter of transistor 107. The base of transistor 108 is connected to the drain of transistor 404, the collector is connected to the ground terminal, and the emitter is connected to the drain of transistor 403. Resistor 204 is connected between the base and emitter of transistor 108.

In the level conversion circuit of FIG. 3, the transistor 10
7, 108 and resistors 203 and 204, the switching of the output signals S and b becomes faster, and the output signals S and B switch faster.
The load driving capacity of b increases.

The level conversion circuit shown in FIG. 4 is obtained by adding PMO3) transistors 409 and 410 to the level conversion circuit shown in FIG. Transistor 409 is connected between ground terminal 11 and the drain of transistor 304, and transistor 410 is connected between ground terminal 11 and the drain of transistor 305. Transistor 409.3
The gate of 04 is connected to the drain of transistor 410. The gates of transistors 410 and 305 are connected to the drain of transistor 409.

Transistors 409, 410, 304, 305 accomplish the data retention function. If output signals a and a of the ECL buffer circuit are both at "H" level, transistors 405 to 408 are turned off. Therefore, the output signal S,b is
The data is held by the data holding function configured by 5.

The level conversion circuit shown in FIG. 5 is obtained by adding NMO8) transistors 307 and 308 to the level conversion circuit shown in FIG. Transistor 307 is transistor 10
9 and the drain of transistor 303, and transistor 308 is connected between the base of transistor 110 and the drain of transistor 306. An output signal i is applied to the gate of the transistor 307, and an output signal a is applied to the gate of the transistor 308.

In the level conversion circuit of FIG.
7,308 is controlled by output signals a and a. As a result, current flows transiently from the transistor 405 to the transistor 303 or the transistor 4
07, the current flowing transiently into the transistor 306 decreases. As a result, the switching of the output signals S and B becomes faster.

The level conversion circuit shown in FIG. 6 is obtained by removing the NMOS transistors 303 and 306 from the level conversion circuit shown in FIG. 4, and adding resistors 205 and 206. resistance 2
05 is connected between the base and emitter of transistor 109, and resistor 206 is connected between the base and emitter of transistor 11O.

In the level conversion circuit of FIG. 6, the transistor 10
9 and 110 are controlled by transistors 304 and 305 via resistors 205 and 206, respectively.

The level conversion circuit shown in FIG. 7 is obtained by adding PMOS transistors 412 and 413 to the level conversion circuit shown in FIG. 15. Transistor 412 is connected between ground terminal 11 and the drain of transistor 309, and transistor 413 is connected between ground terminal 11 and the drain of transistor 310. The gate of transistor 412 is connected to the drain of transistor 413, and the gate of transistor 413 is connected to the drain of transistor 412. Transistor 41.2, 413.30
9 to 312 accomplish the data retention function.

If the output signals a and a of the ECL buffer circuit are both at “H” level, the transistors 411 and 41
4 is turned off, and transistors 309 and 310 are turned on.

Therefore, output signals S and B are held by the data holding function.

The level conversion circuit shown in FIG. 8 is obtained by adding bipolar transistors 111 and 112 and resistors 207 and 208 to the level conversion circuit shown in FIG. The base of the transistor 111 is connected to the drain of the transistor 411, the collector is connected to the ground terminal 11, and the emitter is connected to the drain of the transistor 412. resistance 2
07 is connected between the base and emitter of transistor 111. The base of transistor 112 is connected to the drain of transistor 414, and the collector is connected to ground terminal 1.
1, and its emitter is connected to the drain of transistor 413. Resistor 208 is connected between the base and emitter of transistor 112.

In the level conversion circuit of FIG.
1 and 112 and resistors 207 and 208, the switching of the output signals S and B becomes faster, and the load driving ability of the output signals S and B increases.

In this way, even if the level conversion circuit 20 shown in FIGS. 1 and 2 is replaced with the level conversion circuits shown in FIGS. 3 to 8, the same result as in the embodiment shown in FIGS. The effect of this can be obtained. Note that level conversion circuits with configurations other than those shown in FIGS. 1 to 8 will have the same effect as long as they have a level conversion function and a data retention function and can switch these functions. can get.

Further, in the above embodiment, the present invention is applied to a STRAM having an ECL interface when BiCMO3 technology is applied, but the present invention is not limited to STRAM, and the invention is not limited to STRAM. The method can be applied to all types of semiconductor integrated circuits.

[Effects of the Invention] As described above, according to the present invention, the level conversion means has a level conversion function and a signal holding function, and these functions are switched based on the state of the output signal of the input buffer means. Therefore, a semiconductor integrated circuit that can perform a level conversion operation at high speed without increasing delay time due to having a data holding function can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a semiconductor integrated circuit according to a first embodiment of the present invention. FIG. 2 is a circuit diagram showing the configuration of a semiconductor integrated circuit according to a second embodiment of the invention. Figures 3, 4, 5, 6, 7 and 8
Each figure is a circuit diagram showing a modification example of the level conversion circuit. FIG. 9 is a block diagram showing the configuration of STRAM. Figure 10 shows STRAM with ECL interface.
ECL Jin Kabaka 3 when applying BiCMO3 technology to
It is a circuit diagram showing fufufu. FIG. 11 is a circuit diagram showing another example of the conventional structure up to ECL Kabaka 3 Fufufuda when BiCMO8 technology is applied to STRAM having an ECL interface. FIG. 12 is a specific circuit diagram of the inverter. FIGS. 13, 14, and 15 are specific circuit diagrams of the level conversion circuits shown in FIGS. 1θ and 11. In the figure, 10 is an ECL buffer circuit, 20 is a level conversion circuit, 11 is a ground terminal, 12 is a power supply terminal, 10
1 to 106 are bipolar transistors, 201, 202
is a resistor, 301.332 is an NMO8) transistor, 40
1 to 404 are PMOS transistors, 901 to 904 are constant current sources, CLK is a clock signal, vcc is a ground voltage,
v and yu are negative voltages, VBB is a reference voltage, Vin is an input signal, a and a are ECL level output signals, and b and b are MOS level 8-power signals. Note that the same reference numerals in each figure indicate the same or corresponding parts. Figure Figure ＼ Figure Figure 8 Figure 10 Figure 13 Figure 14 To the memory cell array

Claims (1)

[Scope of Claims] A semiconductor integrated circuit comprising means for generating an internal synchronization signal, the input buffer receiving an input signal of a first logic level and having an output signal controlled in response to the internal synchronization signal. and a level conversion function for receiving the output signal of the input buffer means and converting the level of the output signal into a signal of a second logic level, and a signal holding function for holding the level-converted signal, A semiconductor integrated circuit comprising level converting means for switching between the level converting function and the signal holding function based on the state of the output signal of the input buffer means.