JPH0448872A - Digital gradation signal thinning circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a digital gradation signal thinning circuit for reproducing an image.

[Conventional technology]

Halftone dot method as a method for correcting digital tone signals when reproducing an image from digital tone signals Figure 7 is an example of analog halftone dot conversion. This method subdivides the dimensional image data space into constant areas and replaces the data values within the divided areas with the size of the point. Figure 7 shows four dots. FIG. 8 is an example of digital halftone dot formation, in which halftone dot formation is realized by outputting input data while comparing it with a reference table. That is, if the value of the input data at the corresponding position is greater than the data value at each position in the reference table, the output is a black dot, and conversely, when the value is equal to or smaller than the value, the output is a white dot. As in the example in Figure 8,
If each data value in the reference table is set to a value that is the smallest at the center of the table and increases in sequence in a spiral manner, the output data becomes a halftone dot if the value of the input data is constant. The size of the halftone dot changes depending on the value of the input data, and when the input data is 1, the output data is 1, and when the input data is 2, the output data is 2. As described above, when digital gradation signals are halftone-formed to perform gradation reproduction, unlike reproduction of digital binary signals, the output image has the characteristic that even if the input digital gradation signals are thinned out to a certain extent, the output image does not deteriorate much. . Taking advantage of this characteristic, thinning processing of input digital gradation signals has been conventionally performed for reasons such as simplifying the configuration of the gradation correction circuit and increasing processing speed. By the way, in this case, a simple thinning circuit has the disadvantage that the output image is affected by variations in the non-uniformity of the input image itself, non-uniformity due to noise components, etc., and the image quality is likely to deteriorate. Therefore, conventionally, thinning processing of digital gradation signals has been performed. Averaging processing is performed later. FIG. 9 shows an example of this type of conventional circuit, and FIG. 10 is its timing chart. In this example, the thinning cycle is one type of 3. In this example, a digital gradation signal Sl (FIG. 10A) consisting of data Sll, SI2, SI3, . . . input from the signal input terminal 11 is supplied to the thinning circuit 12 every three data periods A thinning process is performed in which one piece of data is thinned out. The output signal S2 (B in the figure) of the thinning circuit 12 is latched by the latch circuit 14 by the latch timing signal S3 (C in the figure) synchronized with the thinning period from the terminal 13. The output S4 (D in the figure) of this latch circuit 14 is supplied to the averaging circuit 15, and the thinning circuit 12
The output signal S2 of (S2
+S4)/2 is performed, and from this star equalization circuit 15, an output signal S5 consisting of Yl, Y4, Yl, . . . is obtained. Here, if Yl - (SI4 + 511) / 2 Y4 - (17 + SI4 ) / 2, then even for a constant gradation change that is not affected by non-uniformity of the input image itself or non-uniformity due to noise components. , there is a drawback that fluctuations appear in the output. This invention aims to eliminate the above drawbacks. becomes.

[Question S that the invention seeks to solve]

However, as described above, when the averaging process is performed after the digital gradation signal thinning process, the process in the averaging circuit 15 becomes the averaging of the data sampled in the thinning circuit 12,
Data not sampled in is not involved in averaging. For this reason, there is a drawback that periodic gradation fluctuations specific to the input signal cannot be offset to the maximum extent among non-uniformities of the input image itself, non-uniformities due to noise components, etc. In addition, two types of thinning cycles in the thinning circuit are mixed.

[Means to solve the problem]

The digital gradation signal thinning circuit according to the present invention corresponds to the embodiment shown in FIG. It consists of an averaging circuit 24 that averages the delayed signal and the input digital gradation signal, and a thinning circuit 25 that thins out the output signal of the averaging circuit 24. The delay time is selected to be different from the thinning cycle of the thinning circuit 25. Further, in the case where the thinning cycle in the thinning circuit 25 is a mixture of two types of cycles, a certain cycle and a cycle that is one data cycle different from the certain cycle, the delay time of the delay means 22 is one of the thinning cycles. is selected equally to one of the two.

[Effect]

In this invention, before the thinning process, the input digital gradation signal and the signal delayed by the delay means 22 are averaged. In this case, the delay time in the delay means 22 is set to a period different from the thinning period. therefore,
Before this averaging, the averaging circuit 24 averages the data that would not be sampled when the thinning process was first performed and the data that would be sampled. After this averaging, thinning processing is performed.

【Example】

FIG. 1 shows an embodiment of a digital gradation signal thinning circuit according to the present invention, and FIG. 2 is a timing chart thereof. In this example, the thinning cycle is one type of 3, and the delay time in the delay means is one data cycle longer than the thinning cycle. In FIG. 1, 21 is an input terminal, and this input terminal 21
The digital gray scale signal Di (FIG. 2A) that continues through the data INI, IN2, IN3, . . . is supplied to the delay circuit 22. In this example, the delay circuit 22 includes four latch circuits 22 a s 22 b and 22 c. It consists of 22d. Then, through the terminal 23, a latch dimming signal D2 (B in the figure) synchronized with the signal input timing of the input digital gradation signal D1 is transmitted to each latch circuit 22a.
, 22b, 22c, 22d, and the digital grayscale signal DI is sequentially supplied to latch circuits 22A, 22b, 22c, 2
2d, and the outputs D3 to D6 of the respective latch circuits 22a to 22d become as shown in FIG. 2C-F. Therefore, the output D6 of the latch circuit 22d becomes a digital gradation signal four data points earlier than the input digital gradation signal D1. Then, the output D6 of this latch circuit 22d, that is,
The output of the delay circuit 22 and the input digital gradation signal D1 are supplied to an averaging circuit 24, where both outputs are averaged. The output D7 of this averaging circuit 24 becomes data X1, X2, X3, etc. as shown in FIG. X3-(lN7+1N3)/2, and when the input digital gradation signal D1 is directly thinned out at one type of thinning cycle 3, unsampled data is also included in the averaging process. The output D7 of this averaging circuit 24 is supplied to a thinning circuit 25, and the data is thinned out from the output D7 according to a predetermined thinning pattern.
, X4, . . . successive outputs D8 are obtained. FIGS. 3 and 4 are diagrams for comparison between the circuit system of the present invention and the conventional circuit system. Figure 3 shows the input digital gradation signal D1, where the broken line is the ideal source analog signal, and the solid line is due to the non-uniformity of the input image itself and noise components during conversion from the analog signal to the digital signal. This is a digital gradation signal with non-uniformity added. In this case, the number of input gradations was 16 gradations (0 to 15). In addition, in the same figure, 01. is the input signal point,
is the sampling point of the thinning circuit, and the thinning period is one of three types. FIG. 4 shows the difference between the output signal after the input digital gradation signal shown in FIG. In Fig. 4, . . . are the outputs of the inventive circuit. Xl, X4, . . . correspond to the output D8 of the decimation circuit 25. This is the output according to the conventional circuit example. 口... The 口 is the output according to the conventional circuit example that performs averaging after thinning. Yl, Y4 . . . are the outputs of the averaging circuit 15 in FIG. It corresponds to output S5. Note that in the case of the present invention circuit and the conventional circuit example that performs averaging after thinning, the timing is delayed by one sampling point due to the circuit configuration.Each of the above When comparing the output signals of the circuits, it can be seen that in the section A shown in Fig. 4, the output signal of the circuit of the present invention is the closest to the ideal source analog signal. When the thinning circuit 25 uses a mixed cycle of two types of thinning cycles, for example, when the thinning cycle is a repeat of 3, 3, and 4, the delay circuit 22 has three latch circuits, or Thereby, the output that is not sampled when the input digital signal is directly thinned out can be used for averaging in the averaging circuit 24, and the object of the present invention can be achieved. , and is a diagram for comparison between the circuit system of the present invention and the conventional circuit system. FIG. In this example, the number of input gradations is 22 gradations (0 to 21). 01. is the input signal point, . is the sampling point of the thinning circuit, and the thinning period is 3.3. 4 is repeated. FIG. 6 shows the difference between the output signals of the thinning circuit of the present invention and the conventional thinning and averaging circuit for the input digital gradation signal of FIG. 5. In Figure 6, . . . is the output of the circuit of this invention. Low... is the output of the averaging circuit after thinning out. As is clear from the diagram, the output of the circuit of this invention is the same as the input signal, However, fluctuations appear in the output of the conventional thinning and averaging circuit.As described above, by employing the circuit of the present invention, the source analog signal can be thinned out in a more effectively averaged form. It is possible to obtain a digital gradation signal output with high reproduction accuracy. In addition, in this invention, since the signal that is not sampled and does not participate in averaging when the thinning process is performed first and the sampled signal are averaged,
By selecting the amount of delay in the delay circuit, it is possible to select such that an optimal output can be obtained during averaging. In other words, by changing the delay amount (corresponding to the number of latch circuits in the above example) to match the characteristic conditions of input signal non-uniformity, it is possible to obtain the optimal output. For example, the optimal output can be obtained by changing the delay amount, the number of latch circuits, and the thinning pattern to suit the difference in linear density between input and output, the unique periodic gradation fluctuations of input and output, etc. is possible.

【Effect of the invention】

As described above, according to the present invention, it is possible to average the output sampled when the input digital gradation signal is directly thinned out and the output that is not sampled. In addition, when performing the t1 dot processing, there is an effect that a high quality output with high reproducibility can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of a digital gradation signal thinning circuit according to the present invention, FIG. 2 is a timing chart for explaining the same, and FIGS. 3 and 4 are one embodiment of the present invention. 5 and 6 are diagrams for comparing the output signal of another embodiment of the present invention and the output signal of the conventional circuit. 7 is a diagram for explaining analog halftone dot processing, FIG. 8 is a diagram for explaining digital halftone dot processing, FIG. 9 is a block diagram of a conventional circuit, and FIG. The figure is a timing chart for explaining this. 22; Delay circuits 22a, 22b, 22c, 22d; Latch circuit 24;
Averaging circuit 25; thinning circuit

Claims (2)

[Claims] (1) a delay means for delaying an input digital gradation signal by a predetermined times the data cycle; an averaging circuit for averaging the delayed signal from the delay means and the input digital gradation signal; and the averaging circuit. 1. A decimation circuit for digital gradation signals, comprising a decimation circuit that performs decimation processing on an output signal of the gradation circuit, the delay time of said delay means being selected to be different from the decimation cycle of said decimation circuit. (2) The thinning period in the thinning circuit is a certain period,
Claim 1 (1) In the case where two types of cycles coexist, one data cycle different from the other, and the delay time of the delay means is selected to be equal to one of the thinning cycles.
) The digital gradation signal thinning circuit described in ).