JPH0449246B2 - - Google Patents
Info
- Publication number
- JPH0449246B2 JPH0449246B2 JP61053258A JP5325886A JPH0449246B2 JP H0449246 B2 JPH0449246 B2 JP H0449246B2 JP 61053258 A JP61053258 A JP 61053258A JP 5325886 A JP5325886 A JP 5325886A JP H0449246 B2 JPH0449246 B2 JP H0449246B2
- Authority
- JP
- Japan
- Prior art keywords
- dielectric
- multilayer capacitor
- capacitance
- dielectric constant
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Description
【発明の詳細な説明】
(a) 技術分野
この発明は、セラミツクからなる誘電体内に複
数の電極膜を埋設した積層コンデンサに関する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field The present invention relates to a multilayer capacitor in which a plurality of electrode films are embedded in a dielectric made of ceramic.
(b) 従来技術とその欠点
積層コンデンサの誘電体は、小型で大きな容量
を得るために高い誘電率のものが使用される。と
ころが、従来は、間に誘電体層を介して重合わせ
て形成された電極膜のさらに外層を覆う誘電体
も、容量に影響しないにもかかわらず製造の便宜
上のために、内層の誘電体と同じ素材のものを使
用していたので、同様に高い誘電率を示すことに
なり、このため実装時の容量が部品単体で測定し
た場合と異なるという欠点が生じていた。(b) Prior art and its disadvantages A dielectric material of a multilayer capacitor has a high dielectric constant in order to obtain large capacitance in a small size. However, conventionally, the dielectric covering the outer layer of the electrode film, which is formed overlappingly with a dielectric layer in between, is also separated from the inner layer dielectric for manufacturing convenience, even though it does not affect the capacitance. Since they were made of the same material, they also exhibited a high dielectric constant, which resulted in the drawback that the capacitance when mounted was different from when measured as a single component.
これは、例えば第3図に示すように、積層コン
デンサ1をプリント基板2に実装した場合、プリ
ント基板2の裏面側に配線パターン3が形成され
ているようなときには、最下層の誘電体4の誘電
率が高いためにその上に埋設された最下段の電極
膜5の配線パターン3との間で生じる浮遊容量が
無視できない値となり、積層コンデンサ1の見掛
け上の容量が設定値より大きくなるためである。
また、このような従来の積層コンデンサ1を、第
4図に示すように、電極膜5が平行に位置するよ
うに複数並べて配置して実装したような場合に
も、各積層コンデンサ間に浮遊容量が生じて見掛
け上の容量が設定値と相違することがある。 For example, as shown in FIG. 3, when a multilayer capacitor 1 is mounted on a printed circuit board 2 and a wiring pattern 3 is formed on the back side of the printed circuit board 2, the lowermost dielectric layer 4 is Due to the high dielectric constant, the stray capacitance generated between the lowermost electrode film 5 and the wiring pattern 3 buried thereon becomes a value that cannot be ignored, and the apparent capacitance of the multilayer capacitor 1 becomes larger than the set value. It is.
Furthermore, even when a plurality of such conventional multilayer capacitors 1 are mounted side by side so that the electrode films 5 are located in parallel as shown in FIG. 4, stray capacitance is generated between each multilayer capacitor. may occur and the apparent capacity may differ from the set value.
(c) 発明の目的
この発明は、このような事情に鑑みなされたも
のであつて、外層の誘電体の低誘電率のもので構
成することにより、埋設した電極膜と外部との間
に生じる浮遊容量を影響のない程度に低減するこ
とができる積層コンデンサを提供することを目的
とする。(c) Purpose of the Invention This invention has been made in view of the above circumstances, and by constructing the outer layer of dielectric material with a low dielectric constant, it is possible to reduce the amount of heat generated between the buried electrode film and the outside. An object of the present invention is to provide a multilayer capacitor that can reduce stray capacitance to an insignificant level.
(d) 発明の構成および効果
この発明の積層コンデンサは、誘電体内に複数
の電極膜を埋設した積層コンデンサにおいて、表
裏両面に形成される外層のセラミツク層を内層の
セラミツク層よりも低誘電率にしたことを特徴と
する。(d) Structure and Effects of the Invention The multilayer capacitor of the present invention is a multilayer capacitor in which a plurality of electrode films are embedded in a dielectric, and the outer ceramic layer formed on both the front and back surfaces has a dielectric constant lower than that of the inner ceramic layer. It is characterized by what it did.
この発明を上記のように構成すると、積層コン
デンサの実装時に、両端の電極膜と外部の配線パ
ターン等とが接近して向かい合うような場合に、
間に位置する外層の誘電体の誘電率が内層の誘電
体より低いことからあまり大きな容量は生じな
い。このため、外層の誘電体の誘電率を十分に低
くしておけば浮遊容量を設定された容量に影響を
与えない程度に低減することできる。したがつ
て、この発明は、実装条件によつて容量が変動す
るようなことなく使い易い積層コンデンサを提供
することができる。 When the present invention is configured as described above, when the electrode films at both ends and the external wiring pattern etc. are close to each other and face each other when mounting a multilayer capacitor,
Since the dielectric constant of the outer layer dielectric located between the two is lower than that of the inner layer dielectric, a very large capacitance does not occur. Therefore, if the dielectric constant of the outer layer dielectric is made sufficiently low, the stray capacitance can be reduced to an extent that does not affect the set capacitance. Therefore, the present invention can provide a multilayer capacitor that is easy to use and whose capacitance does not vary depending on mounting conditions.
(e) 実施例
第1図はこの発明の実施例である積層コンデン
サの縦断面図である。(e) Embodiment FIG. 1 is a longitudinal sectional view of a multilayer capacitor which is an embodiment of the present invention.
この実施例の積層コンデンサ1は、三層の誘電
体4とこれらの間に埋設された二段の電極膜5と
外部電極6とで構成される。誘電体4は、セラミ
ツクからなり、三層のうち中央に配置される誘電
体4bは誘電率の高い素材が使用される。また、
三層の表裏両端に形成される最外層の誘電体4
a,4cは、中央の誘電体4bよりも十分に低誘
電率の素材が使用される。電極膜5は、誘電体4
の各層間に埋設されて、上段の電極膜5が端を一
方の側面のみに露出し、下段の電極膜5が端を対
向する他方の側面にのみ露出するようにしてい
る。これらの誘電体4a,4b,4cと電極膜
5,5の形成は、例えば第2図に示すように、セ
ラミツクのグリーンシート7を3枚用意し、その
うち2枚の表面にのみ銀−パラジウムペースト8
等をプリントした後に互いに重ね合わせて、焼成
することにより形成される。通常はこのように重
ね合めされたものにさらに電極膜を付与していな
いグリーンシートが適当枚数重ね合わされる。な
お、このときのグリーンシート7は、最外層のも
ののみ誘電率が低い素材のものを使用する。外部
電極6,6は、このようにして形成された積層体
の両側面およびその周囲を覆うように形成された
導電体である。したがつて、一方の側面側に形成
された外部電極6は上層の電極膜5と導通し、他
方の側面側に形成された外部電極6は下層の電極
膜5と導通することになる。 The multilayer capacitor 1 of this embodiment is composed of a three-layer dielectric 4, a two-stage electrode film 5 and an external electrode 6 buried therebetween. The dielectric 4 is made of ceramic, and the dielectric 4b placed in the center of the three layers is made of a material with a high dielectric constant. Also,
Outermost dielectric layer 4 formed on both front and back ends of the three layers
For a and 4c, a material having a sufficiently lower dielectric constant than the center dielectric 4b is used. The electrode film 5 is the dielectric material 4
The upper electrode film 5 has an end exposed only on one side surface, and the lower electrode film 5 has an end exposed only on the other opposing side surface. To form these dielectrics 4a, 4b, 4c and electrode films 5, 5, for example, as shown in FIG. 2, three ceramic green sheets 7 are prepared, and only the surfaces of two of them are coated with silver-palladium paste. 8
etc., are stacked on top of each other, and fired. Usually, an appropriate number of green sheets to which no electrode film is provided are further superimposed on the thus-superposed green sheets. Note that the green sheet 7 at this time uses a material having a low dielectric constant only for the outermost layer. The external electrodes 6, 6 are conductors formed to cover both side surfaces and the periphery of the thus formed laminate. Therefore, the external electrode 6 formed on one side is electrically connected to the upper electrode film 5, and the external electrode 6 formed on the other side is electrically connected to the lower electrode film 5.
上記のように構成されたこの実施例の積層コン
デンサ1と従来の積層コンデンサ1との実装時の
容量変化の程度の違いを示す。ここで、従来例に
おける誘電体4およびこの実施例における中層の
誘電体4bの誘電率εを10000とし、この実施例
の最外層の誘電体4a,4cの誘電率ε′を10とし
て比較する。 The difference in the degree of capacitance change during mounting between the multilayer capacitor 1 of this embodiment configured as described above and the conventional multilayer capacitor 1 is shown. Here, the dielectric constant ε of the dielectric 4 in the conventional example and the middle layer dielectric 4b in this example is assumed to be 10,000, and the dielectric constant ε' of the outermost layer dielectrics 4a and 4c in this example is assumed to be 10.
これらの積層コンデンサ1を、第3図に示すよ
うにプリント基板2に実装した場合、最下層の誘
電体4cの厚さd1とプリント基板2のベークライ
トの厚さd2との比が1:1のときで、この実施例
は従来例に比べ浮遊容量の影響を約1/2に抑える
ことができた。 When these multilayer capacitors 1 are mounted on a printed circuit board 2 as shown in FIG. 3, the ratio of the thickness d 1 of the lowermost layer dielectric 4c to the thickness d 2 of Bakelite of the printed circuit board 2 is 1: 1, this embodiment was able to suppress the influence of stray capacitance to about 1/2 compared to the conventional example.
また、これらの積層コンデンサ1をそれぞれ2
つずつ第4図に示すようにプリント基板2に並べ
て実装した場合には、お互いに向かい合う最外層
の誘電体4a,4cの厚さをそれぞれd3,d4と
し、2つの積層コンデンサ1,1間の距離をd3+
d4としたときで、この実施例は従来例に比べ浮遊
容量の影響を約1/3に抑えることができた。 In addition, each of these multilayer capacitors 1 is
When the two multilayer capacitors 1 and 1 are mounted side by side on the printed circuit board 2 as shown in FIG. The distance between d 3 +
When d was 4 , this example was able to suppress the influence of stray capacitance to about 1/3 compared to the conventional example.
以上説明したように、この実施例は、外層の誘
電体4a,4bの誘電率が十分に低いことから、
外部の配線パターン3等との間で生ずる浮遊容量
の影響を十分に小さくすることができる。このた
め、実装時の配置によつて容量が許容範囲を越え
るというようなおそれがなくなり、使い勝手のよ
い積層コンデンサ1となる。 As explained above, in this embodiment, since the dielectric constants of the outer layer dielectrics 4a and 4b are sufficiently low,
The influence of stray capacitance generated between the external wiring pattern 3 and the like can be sufficiently reduced. Therefore, there is no fear that the capacitance will exceed the allowable range due to the arrangement during mounting, and the multilayer capacitor 1 becomes easy to use.
第1図はの発明の実施例である積層コンデンサ
の縦断面正面図、第2図は同積層コンデンサの形
成手順を示すための斜視図、第3図および第4図
は積層コンデンサの実装時における正面図および
平面図である。
1…積層コンデンサ、4…誘電体、5…電極
膜。
Fig. 1 is a vertical cross-sectional front view of a multilayer capacitor which is an embodiment of the invention, Fig. 2 is a perspective view showing the steps for forming the multilayer capacitor, and Figs. They are a front view and a plan view. 1... Multilayer capacitor, 4... Dielectric, 5... Electrode film.
Claims (1)
デンサにおいて、表裏両面に形成される外層のセ
ラミツク層を内層のセラミツク層よりも低誘電率
にしたことを特徴とする積層コンデンサ。1. A multilayer capacitor in which a plurality of electrode films are embedded in a dielectric material, characterized in that an outer ceramic layer formed on both the front and back surfaces has a dielectric constant lower than that of an inner ceramic layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5325886A JPS62210612A (en) | 1986-03-11 | 1986-03-11 | Laminated capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5325886A JPS62210612A (en) | 1986-03-11 | 1986-03-11 | Laminated capacitor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62210612A JPS62210612A (en) | 1987-09-16 |
| JPH0449246B2 true JPH0449246B2 (en) | 1992-08-11 |
Family
ID=12937754
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5325886A Granted JPS62210612A (en) | 1986-03-11 | 1986-03-11 | Laminated capacitor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62210612A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3233090B2 (en) * | 1998-02-06 | 2001-11-26 | 株式会社村田製作所 | High voltage multilayer capacitors |
| JP3275818B2 (en) | 1998-02-12 | 2002-04-22 | 株式会社村田製作所 | Multilayer capacitors |
| KR101376843B1 (en) * | 2012-11-29 | 2014-03-20 | 삼성전기주식회사 | Multi-layered ceramic capacitor, mounting structure of circuit having thereon multi-layered ceramic capacitor and packing unit for multi-layered ceramic capacitor |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5643716A (en) * | 1979-09-18 | 1981-04-22 | Tdk Electronics Co Ltd | Solid*layerrbuilt electronic circuit parts |
-
1986
- 1986-03-11 JP JP5325886A patent/JPS62210612A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62210612A (en) | 1987-09-16 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |