JPH0449399U - - Google Patents
Info
- Publication number
- JPH0449399U JPH0449399U JP1990090448U JP9044890U JPH0449399U JP H0449399 U JPH0449399 U JP H0449399U JP 1990090448 U JP1990090448 U JP 1990090448U JP 9044890 U JP9044890 U JP 9044890U JP H0449399 U JPH0449399 U JP H0449399U
- Authority
- JP
- Japan
- Prior art keywords
- prom
- write
- read
- address
- write operation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Storage Device Security (AREA)
- Semiconductor Memories (AREA)
Description
第１図は本考案に係るＥ２ＰＲＯＭのライトプ
ロテクト装置の一実施例を示す回路構成図、第２
図はステート毎の信号の状態を示す図である。
１……Ｅ２ＰＲＯＭ、１１……メモリ部、１２
……書き込み許可信号制御回路。
FIG. 1 is a circuit configuration diagram showing an embodiment of an E 2 PROM write protection device according to the present invention, and FIG.
The figure is a diagram showing signal states for each state. 1... E2 PROM, 11...Memory part, 12
...Write permission signal control circuit.
Claims (1)
ライトプロテクト装置において、 前記Ｅ２ＰＲＯＭに接続されたアドレスバス、
データバス及びリードライト信号線が接続されて
いて、Ｅ２ＰＲＯＭへの最初の書き込み動作が完
了したところでＥ２ＰＲＯＭを読みだしのみが可
能にし、その後最初の書き込みと同じアドレス及
び同じデータでＥ２ＰＲＯＭへの書き込み動作が
行われた場合に、Ｅ２ＰＲＯＭを読み書き可能に
する書き込み許可制御回路を有することを特徴と
するＥ２ＰＲＯＭのライトプロテクト装置。[Claims for Utility Model Registration] In an E 2 PROM write protect device that protects the contents of an E 2 PROM, an address bus connected to the E 2 PROM;
Once the data bus and read/write signal lines are connected and the first write operation to the E 2 PROM is completed, the E 2 PROM can only be read, and then the E 2 PROM can be read only at the same address and with the same data as the first write. A write protection device for an E 2 PROM, comprising a write permission control circuit that makes the E 2 PROM readable and writable when a write operation to the PROM is performed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990090448U JPH0449399U (en) | 1990-08-29 | 1990-08-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990090448U JPH0449399U (en) | 1990-08-29 | 1990-08-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0449399U true JPH0449399U (en) | 1992-04-27 |
Family
ID=31825212
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990090448U Pending JPH0449399U (en) | 1990-08-29 | 1990-08-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0449399U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62245353A (en) * | 1986-04-18 | 1987-10-26 | Hitachi Ltd | Prevention circuit for data rewriting of eeprom |
| JPS6443897A (en) * | 1987-08-10 | 1989-02-16 | Nec Corp | Non-volatile semiconductor memory device capable of being erased and written electrically |
-
1990
- 1990-08-29 JP JP1990090448U patent/JPH0449399U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62245353A (en) * | 1986-04-18 | 1987-10-26 | Hitachi Ltd | Prevention circuit for data rewriting of eeprom |
| JPS6443897A (en) * | 1987-08-10 | 1989-02-16 | Nec Corp | Non-volatile semiconductor memory device capable of being erased and written electrically |
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