JPH0449444A - Address allocating system for memory space - Google Patents

Abstract

PURPOSE:To attain address allocation having high programming efficiency by controlling a selection means by an output from a comparing means for comparing the contents of a reference register with that of a pointer to select a specific bank register. CONSTITUTION:When an address value 'addc' is stored in a CA register 17 for storing the upper limit address of a common memory area independent of memory banks 10 to 12, addresses in the common memory area independent of the banks 10 to 12 are '0' to 'addc'. An output signal 2 from a comparator 18 for comparing addresses 'add', 'addc' set up in the pointer 14 goes non-active when the 'add' is larger than the 'addc' and goes active when the 'add' is less than the 'addc'. The bank to be selected by the bank register 15 is specified and a multiplexer 16 is controlled by the value of the register 15 to select one of the banks 10 to 12. Consequently, address allocation having high programming efficiency can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory space address allocation method, and more particularly to a memory space address allocation method in a microcomputer incorporating a random access memory.

[Conventional technology]

A conventional address allocation method for random access memory (hereinafter referred to as RAM) space will be explained using the drawings. FIG. 4 shows an example of a conventional RAM space address allocation method, in which a pointer 44 consisting of n bits,
A large number of memory banks 40 to 43 and a bank register 45
and a selection circuit 46. The RAM is composed of one word with m bits (hereinafter, a unit composed of m bits of RAM is referred to as a word), and the pointer 44
``One word's worth of addressing can be specified.The memory space of 2n words' worth of memory space is referred to as a memory bank 40, 41, 42,...43 as one unit.The bank register 45 is used to specify a memory bank. If the bank register 45 has a bit configuration, it is possible to specify 2 memory banks, so it is possible to specify addresses for 2n+3 words. .

This method uses (n+k) without the concept of memory banks.
Compared to a method in which addresses are specified using only bit pointers, the size of the address space that can be specified is the same, but it is advantageous in terms of hardware configuration. i.e. pointer 4
If the configuration shown in Fig. 4 is adopted, n signal lines (hereinafter referred to as buses) for carrying address information are sufficient, but if a memory bank is not used and a pointer of (n + k) bits is configured, ( n+k) buses are required. When configured with n buses, address information cannot be stored in a pointer in one process, but requires multiple processes, making control complicated. This difference becomes more noticeable as the address space becomes larger.

[Problem to be solved by the invention]

The conventional address allocation method described above is advantageous in terms of hardware configuration, but has several disadvantages in terms of software. Especially when developing software, software designers must constantly be aware of which memory bank to select.
This often causes unnecessary confusion. For example, if you temporarily need data from another memory bank while selecting a certain memory bank, you must switch memory banks several times, perform processing, and then reset to the original memory bank again. This results in poor programming efficiency.

Furthermore, when performing operations such as accessing RAM by frequently switching memory banks, there is a drawback that the process of switching memory banks alone takes time and operational efficiency deteriorates.

Therefore, an object of the present invention is to provide an address allocation method that has a memory bank structure and is efficient in programming and operation.

[Means to solve the problem]

The present invention divides a memory space of a random access memory into a plurality of memory banks, causes a bank register to hold information specifying one of the memory banks, and selects a memory bank specified by the information held in the bank register by a selection means. Address allocation of the memory space that specifies the address in the selected memory bank described above by the contents of the pointer for specifying the address in the memory bank = 6 Criteria for specifying a specific address in the allocation method Address allocation in a memory space characterized by comprising a register and a comparison means for comparing the contents of the reference register with the contents of a pointer, and controlling the selection means by the output of the comparison means to select only a specific bank register. provide a method.

Preferably, the upper or lower limit address of the common memory area is held in the reference register as the specific address, and the output of the comparing means is set when the contents of the pointer are smaller than the upper limit address or larger than the lower limit address. An area of addresses less than the upper limit address or an area of addresses greater than the lower limit address in a specific memory bank is used as a common memory area.

More preferably, a control means is provided which converts the output of the pointer according to the contents of the bank register and is capable of specifying an address of a predetermined group of memory banks.

In another aspect of the present invention, in a microcomputer having a built-in random access memory in which a memory space is divided into a large number of memory banks, a first register for specifying a memory bank, and a memory according to the contents of the first register are provided. A selection circuit for selecting a bank, a pointer for specifying an address within the memory bank, and an address conversion circuit that is controlled by the contents of the first register and converts the output of the pointer to specify the address within the memory bank. and a second register for specifying a specific address different from the address specified by the pointer, and a selection circuit that compares the magnitude of the address specified by the pointer and the address specified by the second register. A microcomputer is provided having a comparator for controlling the method.

According to the present invention, a common memory space independent of memory banks can be arbitrarily set without impairing the hardware advantages of the conventional memory bank switching type address allocation method. For example, by storing data that is frequently accessed during program development in a common memory space that does not depend on memory banks, the data can be accessed immediately without switching memory banks, regardless of which memory bank is currently selected. I can do it. Furthermore, since the number of times memory banks are switched is reduced, operational efficiency is also improved compared to the conventional method.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 1, the first embodiment of the present invention is illustrated in FIG.
It includes a memory bank 10, 11, 12 (generally consisting of a number of memory banks), only one of which is shown, and a pointer 14 which specifies with its output signal 1 the address of a word within the memory bank.

The address value stored in the pointer 14, ie, its output signal 1, is hereinafter written as (add). In the present invention, a register 17 is provided to store the upper limit address of a common memory area independent of memory banks. Hereinafter, this will be referred to as a CA register, and the address value stored in the CA register 17 will be described as (addc). CA register] 7 has a value (
addc), the addresses of the common memory area independent of memory banks will be from address 0 to (addc). In the present invention, the pointer 1
Address (add) set to 4 and CA register 17
Comparator 1 that compares the size with the address (addc) in
8 will be provided. The output signal 2 of the comparator 8 is the pointer 14
When the address value (add) set in is equal to or greater than the address value (addc) of the CA register 17, it becomes inactive, and when it is less than (add) or (addc), it becomes active. As in the prior art, a bank register 15 is provided to specify which memory bank to select, and a multiplexer 16 is controlled by the value of the bank register 15 to select one of memory banks 10-12. In the present invention, the multiplexer 16 is also controlled by the output signal 2 of the comparator 18, and when the output signal 2 is inactive, it remains as it is, but when the output signal 2 is active, it forcibly selects the memory bank 10. is configured to do so.

Next, the operation shown in FIG. 1 will be explained. After setting the upper limit address (addc> of the common memory area in the CA register 17, the address (add) is set in the pointer 14. Furthermore, the memory bank register 15 is set in the memory bank 1.
It is assumed that 1 is selected. First, the comparator 18 (ad
The magnitude of d) and (addc) is determined, and the output signal 2 is made active or inactive according to the result.

Here, if (add)l; (addc), output signal 2 is inactive, so multiplexer 1
6 selects the current memory bank, that is, memory bank 11. Therefore, the memory to be accessed is address (add) of memory bank 11. Generally, it refers to the (add) address of the currently selected memory bank.

On the other hand, if (add) < (addc), the output signal 2
becomes active, forcing multiplexer 16 to select memory bank 10. The memory accessed is therefore memory bank 10.

Generally, when (add)<(addc), it always points to the memory bank 10 regardless of the value of the bank register 15. From the above operation address O (addc)
This shows that the area up to the address can be regarded as a common memory area independent of memory banks. It goes without saying that if the CA register 17 is set to 0, there will be no common memory area and the configuration will return to the same as before.

In the configuration shown in FIG. 1, the area from address 0 to address (addc) in memory banks 11 and 12 other than memory bank 10 becomes a wasted area that will never be accessed. . The second embodiment solves this problem as well.

Referring to FIG. 2, the basic operation of the second embodiment of the present invention is the same as that of the first embodiment, but from address 0 of memory bank 11 and memory bank 12 in FIG.
) memory banks 23, each having a different area up to address. It can be used as a memory bank 24. This point will be explained in particular. In FIG. 2, memory bank 10
, pointer 14, comparator 18, CA register 17 and output signal 2 of comparator 18 are similar to those in FIG.

Memory banks 21.22 are memory banks 11.22 in FIG.
This is the remaining part from 12 except for the above-mentioned memory banks 23 and 24. When setting the upper limit address (addC) of the common memory area in the CA register 17, memory bank 1
In order to use the area from address 0 to address (addc) of other memory banks other than 0 as a new separate memory bank 23.24, the bank register 25 and the multiplexer 26 It has been expanded so that you can select. Memory bank 23. Each memory bank 24 has a memory bank 21 . This is the area from address O to address (addc) of the memory bank 22.

Bank register 25 is a normal memory bank, i.e., memory bank 10. Memory bank 21. When the memory bank 22 is selected, the control circuit 29 activates its output 3.
The configuration is such that output 4 is made inactive, switch 31 is closed, and switch 33 is opened. At this time, the first
The configuration is similar to that shown in the figure, and the operation is also the same. When the bank register 25 selects the memory bank 23 or the memory bank 24, the control circuit 29 makes its output 3 inactive and its output 4 active, and opens the switch 31 and closes the switch 33. As a result, the conversion circuit 30 becomes active, each bit of the output 1 of the pointer 14 is inverted by the inverter 32, and the memory banks 23 and 24 are set to the value (((
addc) to the final address of the memory bank can be used as a new memory bank that has a memory area. For example, each memory bank
If the area is from address to FFFFH, set address FFFFH to pointer 14, and set memory bank 2 to memory bank 2.
If 3 is selected, 0 of memory bank 21 is actually selected.
The address is accessed, but from the Coza side, memory bank 2
This means that address 3 FFFFH is being accessed.

In the above embodiment, an arbitrary value is set in the CA register 17, but if a common memory area is to be used in a fixed manner, the CA register 17 in FIG.
It is possible to fix the value of 7 by mask option on the IC chip. An example of that case is shown in FIG.

In FIG. 3, each bit of the CA register 17 is configured with a pair of fuses 34 and 35, one end of which is connected in common and the other end connected to ground 36 or power supply potential 37, and the upper limit address of the common memory area is set bit by bit. Fuse 34.3
This can be set by cutting either one of 5. The fuse may be made of, for example, polycrystalline silicon, and a known method such as laser cutting using a mask may be used. This method has the advantage of reducing the area occupied by the chip.

〔Effect of the invention〕

As explained above, the present invention can arbitrarily set a common memory area that does not depend on memory banks.
This has the effect of reducing the burden during software development and further increasing the processing efficiency during actual operation without sacrificing the advantages of the memory bank type address allocation method.

[Brief explanation of drawings]

FIG. 1 shows a first embodiment of the present invention, FIG. 2 shows a second embodiment of the invention, FIG. 3 shows an example of the configuration of a CA register, and FIG. FIG. 2 is a diagram for explaining a conventional technique. 10.11 12,21 22 23 2440.41
．． 42.43・Memory bank, 4, 44...Pointer, 1...Pointer output signal, 30...Address conversion circuit, 18...Comparator, 17...Stores the upper limit address of the common memory area register, 2... Comparator output signal line, 15, 25.45... Bank register, 1
6, 26.46...Multiplexer, 29...Control circuit, 31.33...Switch, 32...Inverter, 3.4...Control signal, 3435...Fuse, 3
6...ground potential, 37...power supply potential. -11- uJ

Claims (1)

[Claims] 1. A memory space of a random access memory is divided into a plurality of memory banks, information specifying one of the memory banks is held in a bank register, and the memory specified by the information held in the bank register is A reference register for specifying a specific address in a memory space address allocation method in which a bank is selected by a selection means and the address within the selected memory bank is specified by the contents of a pointer for specifying an address within the memory bank. and a comparison means for comparing the contents of the reference register and the contents of the pointer, and the selection means is controlled by the output of the comparison means to select only a specific bank register. Address allocation method. 2. An upper or lower limit address of the common memory area is held in the reference register as the specific address, and when the contents of the pointer are smaller than the upper limit address or larger than the lower limit address, the comparing means 2. The memory space according to claim 1, wherein an area of addresses less than the upper limit address or an area of addresses greater than the lower limit address in the specific memory bank is used as a common memory area. address allocation method. 3. The address allocation method according to claim 1, further comprising a control means that converts the output of the pointer according to the contents of the bank register so as to specify an address of a predetermined group of memory banks. . 4. In a microcomputer incorporating a random access memory in which a memory space is divided into certain units, a first register for specifying the unit, and a selection for selecting the unit based on the contents of the first register. a pointer for specifying an address within the unit; an address conversion circuit that is controlled by the contents of the first register and converts the output of the pointer to specify an address within the unit; a second register for specifying a specific address different from the address specified by the pointer, and a comparison between the address specified by the pointer and the address specified by the second register to control the selection circuit; A microcomputer comprising a comparator.