JPH0449460A - Dma controller - Google Patents

Abstract

PURPOSE:To drive respective DMA controllers by the priority order of the DMA controllers without using a CPU by connecting between the DMA controllers and allocating the priority order to rewritable registers in respective controllers. CONSTITUTION:In addition to the control of priority order to DMA requests among peripheral controllers connected to the DMA controller, the DMA controller discriminates the priority order between respective DMA controllers in accordance with the value of the register 9 built in the DMA controller itself. Namely, the DMA controller for executing plural peripheral controllers in the priority order set up in respective controllers is constituted of the register 9 for determining the priority order between respective DMA controllers, a means 7 for generating an output signal 13 indicating the reception of a DMA request to each DMA controller and a discriminating circuit 8 for discriminating the priority order of the DMA controllers based upon the output of the register 9. Consequently, the DMA controller can be driven in parallel with the other DMA controller without using a CPU.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a DMA controller, and particularly to a DMA controller that controls a plurality of DM controllers.
D suitable for systems configured using A controller
Regarding MA controller.

[Conventional technology]

Conventionally, when performing a DMA operation on more peripheral controllers than can be controlled by one DMA controller, a host CPU checks open DMA channels each time and assigns them to DMA channels. When using multiple DMA controllers in the above case, the C of the host controlling the DMA controllers must be set in advance.
In consideration of competition between DMA controllers on the PU side, control is performed by checking each time the bus is controlled in response to a DMA request, or lower level data transfer is performed via the CPU (host).

[Problem to be solved by the invention]

As mentioned above, in conventional DMA transfer, when performing I) MA transfer to more peripheral controllers than can be controlled by one DMA controller, some form of intervention by the host Cl) is required. There was a problem in that the efficiency of the Naruname transfer deteriorated and the control block of the host CPU became complicated. For this reason, independent parallel operation of each peripheral is extremely inconvenient. Therefore, an object of the present invention is to provide an MA controller that can operate in parallel with other DMA controllers without requiring the intervention of a CPU. be.

[Means to solve the problem]

The DMA controller of the present invention not only controls the priority order of I) MA requests between each peripheral controller connected to the DMA, but also controls the priority order between the DMA controller 1 and the controller using a built-in register. The feature is that the judgment is made according to the value of .

In other words, the present invention provides a DMA controller that controls a plurality of peripheral controllers according to priorities set for each, a register that determines the priority among the DMA controllers, and an output that indicates that each DMA controller has accepted a DMA request. The present invention is characterized in that it includes means for generating a signal, and a determination circuit that determines the priority order between DMA controllers based on each other's output signals using the output of a register.

[Embodiments] Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a DMA controller according to an embodiment of the present invention. Referring to FIG. 1, the DMA controller of this embodiment controls writing/reading to its own DMA controller, and also controls writing/reading to memory and peripheral controllers.
a W control circuit 1, an address register 2 for storing the start address, end address, or number of data for DMA;
A command register 3 for setting the state of the DMA controller from the CPU, a status register 4 for the CPU to monitor the state of the DMA controller, an address buffer 5, a data buffer 6, and each peripheral connected to the DMA controller. A channel priority control circuit 7 that assigns and controls priorities for DMA requests between the controller 1 and the controller (each channel) and also controls the bus during DMA to the CPU, and controls the DMA operation between each DMA controller. A priority determination circuit 8 that controls the priority, a priority register 9 that stores the priority assigned to the DMA controller, and other D
A priority input port 10 for inputting a DMA request acceptance signal from the MA controller, and an internal data bus 1
1, and a DMA permission signal output line 12 that allows DMA operation.
, a DMA request acceptance signal output line 13 indicating that a DMA request from each peripheral controller has been accepted, and a DMA request acceptance signal (pRro, I, respectively) from each other DMA controller RI 1. terminals 1'4, 15 and 16 for receiving PH10), an output terminal 17 for outputting a DMA request signal (DMB) to another DMA controller, a connection terminal 18 for the address bus, and one connection terminal for the data bus. , terminals 20, 21, 22, and 23 for receiving the RESET signal, C8 signal, R, EADY signal, and CLOCK signal that control the DMA controller, and terminals 24, 25 for outputting the MEMR signal, MEMW signal, IOR signal, and IOW signal, respectively. .26 and 27 and DM
Input or output terminals 28, 29 for the DRQ signal, DACK signal, HRQ signal, and HLDA signal that control the A operation
．． 30 and 31. Here D
The RQ signal and DACK signal become a plurality of input and output signals depending on the number of controllable peripheral controllers (usually about four).

FIG. 2 shows extracted parts of the circuit shown in FIG. 1 that are particularly relevant to the present invention together with the internal circuit, and the reference numbers and symbols of each block and signal correspond to those in FIG. 1.

First, normal DMA operation will be explained using FIG. In a DMA operation, a command to the DMA controller is first written from the CPU to the command register 3, and the start address, end address, etc. of the DMA transfer for the DMA channel assigned to the peripheral controller performing the DMA transfer are written to the address register 2. Set.

Then, the DRQ signal from the peripheral controller is sent to the terminal 28.
When received, first, the HRQ signal from the terminal 30 is made active to CP tJ, requesting permission to use the bus line. Furthermore, when permission is received from the CPU by the HLDA signal to the terminal 31, a D ACK signal is returned to the peripheral controller from the terminal 29, and at the same time, depending on the direction of data write/read, the peripheral controller receives permission from the CPU. Activate write/read signals ■○R, /I○W from terminals 26.27, and activate memory write/read signals MEM R, /MEMW from terminals 24.25 for the memory. . Then, the start address bus in the address register 2 is output from the address bus terminal 18, and the DR to the terminal 28 is output.
C every time a data transfer request occurs when the Q signal becomes active.
The bus is confirmed by the PU, and the transfer is repeated until the final address written in address register 2 is reached. If request signals are active simultaneously between channels, a DACK signal is returned to the channel with a higher priority, and higher-order data is transferred to a channel with a lower priority. The contents of priority register 9 are 2-bit QI
Q2, and the priority order corresponding to the data of the 2 pins I~ held by it and the information from other DMA controllers.
The priority order of priority person capos 1-10 for PRI2 is as shown in the table below.

For example, in priority register 9, <Ql, Q2) = (0
,0), this device (DM
Controller A) has the highest priority, the controller connected to terminal 14 (which outputs PRIO) is number 2, the PRII of terminal 15 is number 3, and the PRI2 of terminal 16 is number 4.
It's my turn. Furthermore, if (1, 1) is written in the priority register 9, it is the fourth lowest priority.

Assuming that (0, 1) is currently written in the priority register 9, it will operate at priority 2, and when a DMA request (DRQ signal to terminal 28) becomes active, first the output line 13 is The DMA request acceptance signal becomes active, and the DMA request signal is activated at the output terminal 17 to the outside.
The B signal is activated and the priority determination circuit 8
At this point, it is checked whether there is a request signal from another DMA controller. For example, if the PR0 signal is active at that time, it has a higher priority than itself, so the combination of logic circuits in the priority determination circuit 8 shown in FIG. 2 allows DMA permission on the output line 12. The signal does not become active and remains in a pending state until the PRIO signal becomes inactive (the end of the DMA operation). Then, if the check is performed again and PRIO is inactive, the DMA permission signal becomes active on the output line 12'', and as before, the DMA permission signal is sent to the CPU (RQ).
The double signal is activated, the HLDA signal is received, and the DMA operation is started.

On the other hand, if the PRIO signal is inactive and the PRI] signal is active, this device has a higher priority, so the DMB signal is output to the output terminal 17 when the DMA request acceptance signal becomes active. At the same time, the priority determination circuit 8 makes the DMA permission signal active on the output line 12. Then, it obtains bus permission from the CPU and starts DMA data transfer.

〔Effect of the invention〕

As described above, according to the present invention, parallel operation of a plurality of DMA controllers is enabled by connecting DMA controllers and assigning ranks to rewritable registers in each controller. Therefore, it is possible to operate according to the priority order among the MA controllers without the intervention of the CPU, and the system efficiency is not degraded even when controlling a large number of peripheral controllers.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a DMA controller according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of some blocks in FIG. 1. In the figure, 1 is an R/W control circuit, 2 is an address register, 3 is a command register, 4 is a status register,
5 is an address buffer, 6 is a data buffer, 7 is a channel priority control circuit, 8 is a priority judgment circuit, 9 is a priority register, 10 is a priority input port, 11 is an internal data bus, 12 is a DMA permission signal output line , 13 is a DMA request acceptance signal output line, 14, 15
．． 16 is a DMA request acceptance signal (PRIO, PRII, P
RI2) receiving terminal, 17 is a DMA request signal (DMB)
18 is an address bus, 19 is a data bus, 20, 21, 22.23 are control signals (RESET, C8, READY, CLO) that control the DMA controller.
CK signal) input terminals 24, 25, 26.27 are memory read/write instruction signals MEMR, MEMW and read/write signal l0 to the peripheral controller.
R1IOW) terminals, 28, 29, 30.31 are DM
Control signals (DRQ, DACK, HR (
l HLDA signal) terminal.

Claims (1)

[Claims] a register that determines the priority order among the plurality of DMA controllers; a means for generating an output signal indicating that a DMA request has been received; 1. A DMA controller, further comprising: a determination circuit that determines the priority order of the DMA controller using the output of the register.