JPH0449781B2 - - Google Patents

Info

Publication number
JPH0449781B2
JPH0449781B2 JP58179845A JP17984583A JPH0449781B2 JP H0449781 B2 JPH0449781 B2 JP H0449781B2 JP 58179845 A JP58179845 A JP 58179845A JP 17984583 A JP17984583 A JP 17984583A JP H0449781 B2 JPH0449781 B2 JP H0449781B2
Authority
JP
Japan
Prior art keywords
chip
pattern
circuit
circuit board
molding agent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58179845A
Other languages
Japanese (ja)
Other versions
JPS6071980A (en
Inventor
Kunio Sakuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP58179845A priority Critical patent/JPS6071980A/en
Priority to CH694183A priority patent/CH660551GA3/fr
Publication of JPS6071980A publication Critical patent/JPS6071980A/en
Priority to US06/891,084 priority patent/US4644445A/en
Publication of JPH0449781B2 publication Critical patent/JPH0449781B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/681—Shapes or dispositions thereof comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H10W72/01308—Manufacture or treatment of die-attach connectors using permanent auxiliary members, e.g. using alignment marks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07311—Treating the bonding area before connecting, e.g. by applying flux or cleaning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H10W72/07353—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/331—Shapes of die-attach connectors
    • H10W72/334—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/856—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electric Clocks (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 本発明は、腕時計用回路ブロツク等に用いられ
る回路実装構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit mounting structure used in a circuit block for a wristwatch or the like.

ICチツプを回路基板に接続する手段としては、
ワイヤーによるワイヤボンデイング法、回路基板
上のパターンを穴部外周よりオーバーハングさせ
てインナーリードとし、それによつてICチツプ
との接続をするギヤングボンデイング法、及び回
路基板上に配設したパターンにICチツプのバン
プを直接接続するフエイスダウンボンデイング法
とがある。本発明は特にフエイスダウンボンデイ
ング法による回路実装構造の改良に関する。 As a means of connecting an IC chip to a circuit board,
Wire bonding method using wire, Guiang bonding method in which the pattern on the circuit board is made to overhang from the outer periphery of the hole and used as an inner lead to connect to the IC chip, and There is a face-down bonding method that directly connects bumps on a chip. The present invention particularly relates to improvements in circuit mounting structures using face-down bonding methods.

第１図は、従来の回路ブロツクの構造を示して
いる。１がMOSIC、２が水晶ユニツト、３が回
路基板、４が回路パターンである。５，６はそれ
ぞれ回路パターン４ａ，４ｂ部において、電池端
子から導通をとりICに入力を奢なうプラスパツ
ドとマイナスパツドである。７は回路パターン４
ｃ部がアースされることによりリセツトがかかる
リセツトパツドである。８，９は水晶振動子のゲ
ートパツド、ドレインパツドである。また１０，
１１は回路パターン４ｄ，４ｅ部においてコイル
リード基板と導通をとりコイルにパルス信号を出
力するO1パツド、O2パツドである。また、この
ほかにICパツドには、水晶振動子自身、ICの内
部回路あるいは回路パターンの銅箔による容量等
により奏ずる歩度ずれをIC外部で調整する論理
緩急用パツド１２〜１７がある。これらのパツド
には電池電圧入力の回路パターンが図のように配
列されている。 FIG. 1 shows the structure of a conventional circuit block. 1 is a MOSIC, 2 is a crystal unit, 3 is a circuit board, and 4 is a circuit pattern. Reference numerals 5 and 6 denote positive pads and negative pads in the circuit patterns 4a and 4b, respectively, which establish continuity from the battery terminals and provide input to the IC. 7 is circuit pattern 4
This is a reset pad that is reset by grounding the c part. 8 and 9 are gate pads and drain pads of a crystal resonator. Also 10,
Reference numerals 11 denote O 1 pads and O 2 pads that establish conduction with the coil lead board and output pulse signals to the coils in the circuit patterns 4d and 4e. In addition, the IC pads include logic adjustment pads 12 to 17 for adjusting rate deviations caused by the crystal resonator itself, the internal circuit of the IC, or the copper foil capacitance of the circuit pattern, etc., outside the IC. These pads have battery voltage input circuit patterns arranged as shown in the figure.

第１図におけるＡ−Ａ断面を第２図に示す。 FIG. 2 shows the AA cross section in FIG. 1.

フエイスダウン法によりICチツプと基板上の
パターンを接続した場合は、モールド剤がICチ
ツプと基板の間に侵入しにくいため、基板３の
ICチツプと対向する位置にモールド剤を注入す
る注入穴３ａを設け、基板下面よりモールド剤１
９を注入して充填させている。この際、基板３が
リジツド板の場合、熱膨張率の影響によつてバン
プの剥離が発生する惧れがあるので、バンプの高
さを大きくして影響を少なくする。ICチツプの
外周にはモールド剤の流れ止めのために、流れ出
し防止枠１８が配置されている。しかしこの流れ
出し防止枠１８は部品数を増加させ小型化に逆行
するものである。 When the IC chip and the pattern on the board are connected using the face-down method, it is difficult for the molding agent to penetrate between the IC chip and the board, so
An injection hole 3a for injecting the molding agent is provided at a position facing the IC chip, and the molding agent 1 is inserted from the bottom surface of the substrate.
9 is injected and filled. At this time, if the substrate 3 is a rigid plate, there is a risk that the bumps will peel off due to the effect of the coefficient of thermal expansion, so the height of the bumps is increased to reduce the effect. A flow-out prevention frame 18 is arranged around the outer periphery of the IC chip to prevent the molding agent from flowing. However, this outflow prevention frame 18 increases the number of parts and goes against the trend of miniaturization.

またIC機能としては同一仕様であるが、時計
の形状が変化すると電子素子の配置が異なるた
め、パターンの位置が規制され、統一ICを用い
ることが困難なことがある。第３図は、第１図の
リセツト用のパターン４ｃ，４ａを、基板の反対
側４c′，４a′に持つてきた場合であり、第１図と
同一のICチツプを用いるためにはICチツプの外
周でパターンを引き回さなければならないが、ス
ペース上不可能といつて良い。このような問題を
解決する１つの手段は、パターン４c′，４a′をIC
チツプと重ねて配置することである。これが第３
図に点線で示されている部分４c″，４a″である。
しかし、かかる構成の問題点は、第４図のA′−
A′断面図に示されているように、IC下面を引き
回されるパターン４c″，４a″がモールド剤の流れ
を止めてしまう惧れがあることである。従来はこ
の問題を解決するために止むを得ず、ICチツプ
と基板面の隙間を大きくしていたが、これは回路
ブロツクを厚くし、ひいては腕時計の厚型化をも
たらすという新たな問題を惹き起した。 Furthermore, although the IC functions have the same specifications, when the shape of the watch changes, the arrangement of electronic elements changes, which restricts the position of the pattern, making it difficult to use a unified IC. FIG. 3 shows a case where the reset patterns 4c and 4a of FIG. 1 are placed on opposite sides 4c' and 4a' of the board. The pattern would have to be routed around the outer periphery, but this would be impossible due to space considerations. One way to solve this problem is to convert patterns 4c' and 4a' into ICs.
It should be placed on top of the chip. This is the third
These are portions 4c'' and 4a'' indicated by dotted lines in the figure.
However, the problem with this configuration is that A'--
As shown in the cross-sectional view A', there is a risk that the patterns 4c'' and 4a'' routed around the lower surface of the IC may stop the flow of the molding agent. In the past, in order to solve this problem, it was unavoidable to increase the gap between the IC chip and the board surface, but this created a new problem of making the circuit block thicker, which in turn led to thicker watches. I woke up.

本発明は、以上の問題点を解決し、回路ブロツ
クを薄型小型化し、しかもICチツプの共通使用
を可能にする構造を提供するものである。 The present invention solves the above-mentioned problems and provides a structure that allows the circuit block to be made thinner and smaller, and also allows common use of IC chips.

本発明の回路実装構造は、フレキシブル基板の
上面に配設した複数のパターンの上面にICチツ
プのバンプを直接接続してなる回路実装構造にお
いて、前記ICチツプの半田バンプ内部にはスペ
ーサとしての金属芯が設けられており、且つ前記
ICチツプと対向するフレキシブル基板にモール
ド剤を注入する注入穴が設けられており、前記
ICチツプの前記金属芯を前記パータン上面と当
接させてモールドを行うことにより、前記モール
ド剤を前記ICチツプの外周で停止させるよう構
成し、且つ前記ICチツプの下面に配置される前
記パターンはすべて前記注入穴を横切るよう構成
したことを特徴とする一実施例を第５図、第６図
に示す。第５図は、ICチツプ周辺は第３図と同
一の回路構成をもつが、ICチツプと重なる部分
に引き回されるパターン４a″，４c″の位置が、モ
ールド剤を注入する注入穴３ａと平面的に重なる
よう配置されている。また回路基板３はフレキシ
ブルテープで形成される。ICチツプ１のバンプ
は第７図に示されるように、ICチツプの取り出
し電極の位置にバンプNi芯１０ａ，１４ａを固
着し、ついで、半田バンプ１０，１４がその周囲
に固着されている。尚、第７図ではバンプ１０，
１４について記載したが、すべてのバンプにNi
芯（５ａ〜１７ａ）がほどこされている。 The circuit mounting structure of the present invention is a circuit mounting structure in which the bumps of an IC chip are directly connected to the upper surface of a plurality of patterns arranged on the upper surface of a flexible substrate. A core is provided, and the
An injection hole for injecting a molding agent is provided in the flexible substrate facing the IC chip.
The molding agent is configured to be stopped at the outer periphery of the IC chip by bringing the metal core of the IC chip into contact with the upper surface of the pattern, and the pattern disposed on the lower surface of the IC chip is An embodiment characterized in that all of the injection holes are configured to cross the injection holes is shown in FIGS. 5 and 6. In Fig. 5, the circuit configuration around the IC chip is the same as that in Fig. 3, but the positions of patterns 4a'' and 4c'' routed in the area overlapping with the IC chip are the injection holes 3a for injecting the molding agent. They are arranged so that they overlap in a plane. Further, the circuit board 3 is formed of flexible tape. As shown in FIG. 7, the bumps of the IC chip 1 are made by fixing bump Ni cores 10a and 14a at the positions of the lead-out electrodes of the IC chip, and then fixing solder bumps 10 and 14 around them. In addition, in FIG. 7, bumps 10,
14, but Ni is applied to all bumps.
Cores (5a to 17a) are provided.

かかる回路ブロツクの製造工程は次の通りであ
る。第１にフレキシブルテープ３にモールド剤を
注入する注入穴３ａを穿設し、ついで銅箔膜をフ
レキシブルテープの全面に接着しもしくは蒸着
し、その後エツチングにより不要な銅箔を除去
し、必要なパターン４を形成する。その際、IC
チツプと対向するテープ面上を引き回されるパタ
ーンについては、必ずモールド注入穴３ａを横切
るよう形成される。このようにして形成された回
路基板に、ICチツプのバンプの位置を所望のパ
ターンと一致させてフエイスダウンボンデイング
を行う。この際、半田バンプが隔溶したときバン
プNi芯（１０ａ，１４ａ……）がパターン上面
に当接するまで押圧することにより、ICチツプ
下面とテープの間の隙間の均一が簡単に得られる
ものである。尚この際、第８図に示すように、半
田バンプの溶融ハンダが、当接するバンプNi芯
とパターンを包囲するので、接続が確実になる。
最後に注入穴からモールド剤を注入してICチツ
プ下面と、回路基板の間にモールド剤を充填させ
る。 The manufacturing process for such a circuit block is as follows. First, an injection hole 3a for injecting a molding agent is made in the flexible tape 3, then a copper foil film is adhered or vapor deposited on the entire surface of the flexible tape, and then unnecessary copper foil is removed by etching to create the required pattern. form 4. At that time, IC
The pattern routed on the tape surface facing the chip is always formed so as to cross the mold injection hole 3a. Face-down bonding is performed on the circuit board thus formed by aligning the bumps of the IC chip with the desired pattern. At this time, by pressing the bump Ni cores (10a, 14a...) until they come into contact with the top surface of the pattern when the solder bumps are separated, uniformity of the gap between the bottom surface of the IC chip and the tape can be easily obtained. be. At this time, as shown in FIG. 8, the molten solder of the solder bumps surrounds the bump Ni core and pattern that are in contact with each other, so that the connection is ensured.
Finally, inject molding agent through the injection hole to fill the space between the bottom surface of the IC chip and the circuit board.

本実施例によれば、回路基板がフレキシブルテ
ープによつて形成されているので、ICチツプと
回路基板の隙間を小さくしても熱膨張係数差によ
るバンプの剥離が発生しにくい利点を持ち、また
ICチツプ下面を引き回されるパターンのすべて
が回路基板の注入穴を横切るので、モールド剤の
注入に際してパターンがモールド剤の流れを遮断
するといた問題は全く解消される。また、ICチ
ツプの電極取り出し部に設けたバンプNi芯を回
路基盤のパターンと当接させるという簡単な手段
により、ICチツプと回路基板の隙間を保つこと
が可能であり、更にICチツプと回路基板の隙間
が小さいのでモールド剤が表面張力によりICチ
ツプ周辺から流れ出ていかないため、従来必要で
あつたモールド剤流れ止め枠を不要なものとし
て、回路基板全体を薄型小型化することができ
る。 According to this embodiment, since the circuit board is made of flexible tape, it has the advantage that even if the gap between the IC chip and the circuit board is made small, the bumps are less likely to peel off due to the difference in thermal expansion coefficients.
Since all of the patterns routed around the bottom surface of the IC chip cross the injection holes of the circuit board, the problem of the patterns blocking the flow of the molding agent when injecting the molding agent is completely eliminated. In addition, it is possible to maintain the gap between the IC chip and the circuit board by simply bringing the bump Ni core provided at the electrode extraction part of the IC chip into contact with the pattern on the circuit board. Since the gap is small, the molding agent does not flow out from around the IC chip due to surface tension, making the molding agent flow prevention frame that was previously necessary unnecessary, and the entire circuit board can be made thinner and smaller.

尚、実験的に、ICチツプと回路基板の隙間が
10μ〜20μのときに、モールド剤の流れ止め機能
が有効に作用することが認められた。更に本実施
例ではバンプNi芯を用いたが、銅等の他の金属
芯を用いても良いことはいうまでもない。 In addition, experimentally, the gap between the IC chip and the circuit board was
It was found that the molding agent's flow prevention function was effective when the thickness was 10μ to 20μ. Furthermore, although a bump Ni core is used in this embodiment, it goes without saying that other metal cores such as copper may also be used.

以上の如く本発明によれば、ICチツプ下面に
引き回される回路基板のパターンのすべてが、注
入穴を横切るよう構成し、しかもICチツプと回
路基板の隙間がバンプ内の金属芯とパターンとの
当接により保たれるよう構成したので、次のよう
な効果を有する。 As described above, according to the present invention, all of the circuit board patterns routed under the IC chip are configured to cross the injection hole, and the gap between the IC chip and the circuit board is between the metal core inside the bump and the pattern. Since it is constructed so as to be maintained by contact between the two, it has the following effects.

(a) パターンがICチツプ下面に引き回される構
成をとることにより、時計の機能が異なり電子
素子の配置が変つても、パターンの配置により
共通のICを用いることができるので、量産メ
リツトがある。(a) By adopting a configuration in which the pattern is routed on the bottom surface of the IC chip, even if the function of the watch differs and the layout of the electronic elements changes, a common IC can be used due to the layout of the pattern, which has the advantage of mass production. be.

(b) ICチツプ下面のパターンの引き回しが、す
べて注入穴を横切る構成により、ICチツプと
回路基板の隙間を小さくすることができ、しか
も回路基板がフレキシブルテープによつて形成
されるため、ICチツプと回路基板の隙間が小
さくなつても熱膨張係数差によるバンプの剥離
等の問題が無い利点をもつ。(b) The arrangement in which all the patterns on the bottom of the IC chip cross the injection holes makes it possible to reduce the gap between the IC chip and the circuit board, and since the circuit board is formed of flexible tape, the IC chip It has the advantage that even if the gap between the circuit board and the circuit board becomes small, there is no problem such as bump peeling due to the difference in thermal expansion coefficient.

(c) ICチツプの半田バンプ内に形成される金属
芯が回転基板のパターンと当接することによ
り、ICチツプと回路基板の隙間を保つ構成な
ので、操作が容易であり、接続が確実に得られ
るメリツトを持つ。何故なら、ハンダバンプが
溶融時に金属芯とパターンを包囲するからであ
る。(c) The metal core formed inside the solder bump of the IC chip comes into contact with the pattern on the rotating board to maintain a gap between the IC chip and the circuit board, making it easy to operate and ensuring a secure connection. have merits. This is because the solder bumps surround the metal core and pattern when melted.

(d) ICチツプと回路基板の隙間が少なく、ICチ
ツプ外周でモールド剤が停止するので、モール
ド剤流れ止め枠を不要にして、回路ブロツクの
薄型小型化をもたらすことができる。(d) Since the gap between the IC chip and the circuit board is small and the molding agent stops at the outer periphery of the IC chip, there is no need for a molding agent flow stopper frame, and the circuit block can be made thinner and smaller.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の一実施例を示す平面図、第２図
は第１図のＡ−Ａ断面図、第３図は従来の他の一
実施例を示す平面図、第４図は第３図のA′−
A′断面図、第５図は本発明の平面図、第６図は
第５図のＢ−Ｂ断面図、第７図は第５図に用いら
れるICチツプのＢ−Ｂ断面図。第８図は第５図
に用いられるICチツプのＣ−Ｃ断面図。 １……ICチツプ、３……回路基板（フレキシ
ブルテープ）、３ａ……注入穴、５〜１７……バ
ンプ、５ａ〜１７ａ……金属芯、４ａ，４ｃ……
パターン。 Fig. 1 is a plan view showing a conventional embodiment, Fig. 2 is a sectional view taken along the line A-A in Fig. 1, Fig. 3 is a plan view showing another conventional embodiment, and Fig. 4 is a 3-3 A′− in the diagram
5 is a plan view of the present invention, FIG. 6 is a sectional view taken along line BB in FIG. 5, and FIG. 7 is a sectional view taken along line BB of the IC chip used in FIG. FIG. 8 is a sectional view taken along the line CC of the IC chip used in FIG. 1...IC chip, 3...Circuit board (flexible tape), 3a...Injection hole, 5-17...Bump, 5a-17a...Metal core, 4a, 4c...
pattern.

Claims (1)

【特許請求の範囲】[Claims] １ フレキシブル基板の上面に配設した複数のパ
ターンの上面にICチツプのバンプを直接接続し
てなる回路実装構造において、前記ICチツプの
半田バンプ内部にはスペーサとしての金属芯が設
けられており、且つ前記ICチツプと対向するフ
レキシブル基板にモールド剤を注入する注入穴が
設けられており、前記ICチツプの前記金属芯を
前記パターン上面と当接させてモールドを行うこ
とにより、前記モールド剤を前記ICチツプの外
周で停止させるよう構成し、且つ前記ICチツプ
の下面に配置される前記パターンはすべて前記注
入穴を横切るよう構成したことを特徴とする回路
実装構造。1. In a circuit mounting structure in which the bumps of an IC chip are directly connected to the top surface of a plurality of patterns arranged on the top surface of a flexible substrate, a metal core as a spacer is provided inside the solder bumps of the IC chip, Further, an injection hole for injecting a molding agent is provided in the flexible substrate facing the IC chip, and by performing molding by bringing the metal core of the IC chip into contact with the upper surface of the pattern, the molding agent is injected into the flexible substrate. A circuit mounting structure characterized in that the circuit is configured to be stopped at the outer periphery of an IC chip, and all of the patterns arranged on the lower surface of the IC chip are configured to cross the injection holes.
JP58179845A 1982-12-27 1983-09-28 Circuit mounting structure Granted JPS6071980A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP58179845A JPS6071980A (en) 1983-09-28 1983-09-28 Circuit mounting structure
CH694183A CH660551GA3 (en) 1982-12-27 1983-12-27
US06/891,084 US4644445A (en) 1982-12-27 1986-07-31 Resin mounting structure for an integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58179845A JPS6071980A (en) 1983-09-28 1983-09-28 Circuit mounting structure

Publications (2)

Publication Number Publication Date
JPS6071980A JPS6071980A (en) 1985-04-23
JPH0449781B2 true JPH0449781B2 (en) 1992-08-12

Family

ID=16072904

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58179845A Granted JPS6071980A (en) 1982-12-27 1983-09-28 Circuit mounting structure

Country Status (1)

Country Link
JP (1) JPS6071980A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63139589U (en) * 1987-03-05 1988-09-14
KR100598032B1 (en) * 2003-12-03 2006-07-07 삼성전자주식회사 Tape wiring board, semiconductor chip package using the same, and display panel assembly using the same

Also Published As

Publication number Publication date
JPS6071980A (en) 1985-04-23

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