JPH0449870A - Semiconductor output circuit - Google Patents

Semiconductor output circuit

Info

Publication number
JPH0449870A
JPH0449870A JP2160177A JP16017790A JPH0449870A JP H0449870 A JPH0449870 A JP H0449870A JP 2160177 A JP2160177 A JP 2160177A JP 16017790 A JP16017790 A JP 16017790A JP H0449870 A JPH0449870 A JP H0449870A
Authority
JP
Japan
Prior art keywords
transistor
overcurrent detection
high voltage
load
output circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2160177A
Other languages
Japanese (ja)
Inventor
Takeshi Tateyama
立山 剛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2160177A priority Critical patent/JPH0449870A/en
Publication of JPH0449870A publication Critical patent/JPH0449870A/en
Pending legal-status Critical Current

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  • Stopping Of Electric Motors (AREA)
  • Inverter Devices (AREA)

Abstract

PURPOSE:To prevent the breakdown of a MOS transistor or a lead wire by overcurrents by providing an overcurrent detection means between the low voltage power terminal of a H-type bridge connection and the low voltage power source, and inputting the signal detected by the overcurrent detection means so as to clamp a gate control signal and break the transistor on high voltage side. CONSTITUTION:In case that load RL goes wrong and the division between output terminals M and N shorts, or that excessive voltage adds to a power terminal 7 and excessive currents flows to load resistance RL or a power terminal 9, the detection voltage VR at overcurrent detection resistance 16 rises. The current flows to an NPN transistor base, too, and turnes on transistors 5 and 6, and lowers the voltages of gate control signals S1 and S3 on high voltage side, and turns off the MOS transistors 1 and 3 on high voltage side, and prevents the excessie currents which flow to the load resistance RL of output. Hereby, the breakage of a MOS transistor and the fusion of a lead wire which connects it with the lead frame of a chip can be prevented.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体出力回路に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to semiconductor output circuits.

〔従来の技術〕[Conventional technology]

ステッピングモータを駆動する集積回路は、出力回路に
MOSトランジスタを用いたいわゆるH型ブリッジ構成
を用いているものが多い。
Many integrated circuits that drive stepping motors use a so-called H-bridge configuration using MOS transistors in their output circuits.

第3図は従来の半導体出力回路のH型ブリッジ出力部の
一例の回路図である。
FIG. 3 is a circuit diagram of an example of an H-type bridge output section of a conventional semiconductor output circuit.

H型ブリッジ出力部は、nチャネルMOSトランジスタ
1.3の高圧側対及び2.4の低圧側対をブリッジ構成
し、共通ドレイン点18を高圧電源端子7に、また共通
ソース点8を接地端子9に接続している。
The H-type bridge output section has a high-voltage side pair of n-channel MOS transistors 1.3 and a low-voltage side pair of n-channel MOS transistors 2.4 in a bridge configuration, with a common drain point 18 connected to the high voltage power supply terminal 7, and a common source point 8 connected to the ground terminal. Connected to 9.

制御信号は斜めに対応するSlと82が同相で、それら
の逆相の制御信号S3と84がそれぞれ対応する制御端
子11〜14に入力する。
The diagonally corresponding control signals S1 and 82 have the same phase, and the control signals S3 and 84 having opposite phases are input to the corresponding control terminals 11 to 14, respectively.

ステッピングモータ等の負荷RLは、ブリッジ出力端子
M、N間に接続される。
A load RL such as a stepping motor is connected between bridge output terminals M and N.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の半導体出力回路は、負荷が短絡事故を起
した場合に発生する過電流によりMOSトランジスタや
リード線などを破壊してしまうという欠点があった。
The above-mentioned conventional semiconductor output circuit has a drawback in that the MOS transistor, lead wire, etc. are destroyed by an overcurrent generated when a short-circuit accident occurs in the load.

また、負荷がモータの場合、事故時にも慣性で回転が続
くという欠点があった。
Furthermore, when the load is a motor, there is a drawback that it continues to rotate due to inertia even in the event of an accident.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体出力回路は、2個のMOSトランジスタ
対を有するブリッジ構成の一方のトランジスタ対のゲー
ト端にそれぞれゲート制御信号を入力してブリッジ出力
端子対間に負荷を接続するH型ブリッジ出力部を有する
半導体出力回路において、前記ブリッジ結線の低圧電源
端子と低圧電源間に過電流検出手段を設け、該過電流検
出手段の出力する検出信号を入力して前記ゲート制御信
号をクランプして前記高圧側トランジスタを遮断状態に
する手段とを有して構成されている。
The semiconductor output circuit of the present invention has an H-type bridge output section in which a gate control signal is input to the gate end of one transistor pair of a bridge configuration having two MOS transistor pairs, and a load is connected between the bridge output terminal pair. In the semiconductor output circuit, an overcurrent detection means is provided between the low voltage power supply terminal of the bridge connection and the low voltage power supply, and a detection signal output from the overcurrent detection means is inputted to clamp the gate control signal to detect the high voltage. and means for turning off the side transistor.

そして本発明の半導体出力回路は、前記H型ブリッジ出
力部の他方のトランジスタ対のゲート端がインバータを
介して前記一方のトランジスタのゲート端に対応してそ
れぞれ接続されて構成されている。
The semiconductor output circuit of the present invention is configured such that the gate ends of the other transistor pair of the H-type bridge output section are respectively connected to the gate ends of the one transistor via an inverter.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例の回路図である。FIG. 1 is a circuit diagram of an embodiment of the present invention.

半導体出力回路は、第3図に示した従来のH型ブリッジ
出力部10の共通ソース点8と接地端子9との間に過電
流検出部15を付加したものである。
The semiconductor output circuit has an overcurrent detection section 15 added between the common source point 8 and the ground terminal 9 of the conventional H-type bridge output section 10 shown in FIG.

過電流検出部15は、共通ソース点8と端子9との間に
過電流検出抵抗16を設け、その電圧VRをベースに入
力しコレクタを高圧側のゲート制御端子11.13に接
続し共通エミッタ点を接地端子9に接続するNPNトラ
ンジスタ5,6を有している。
The overcurrent detection unit 15 has an overcurrent detection resistor 16 provided between the common source point 8 and the terminal 9, inputs the voltage VR to the base, connects the collector to the gate control terminal 11.13 on the high voltage side, and connects the common emitter to the overcurrent detection resistor 16. It has NPN transistors 5 and 6 which connect the point to the ground terminal 9.

もし、負荷RLが何らかの理由で故障して出力端子M、
N間がショートしたり、また過剰の電圧が電源端子7に
加わって負荷抵抗RLや電源端子9に過剰の電流が流れ
た場合、過電流検出抵抗16の検出電圧VRが0.7V
以上上昇しNPNトランジスタベースにも電流が流れト
ランジスタ5.6がオンして高圧側のゲート制御信号S
1と83の電圧を下げ、高圧側のMOSトランジスタ1
.3の対をオフさせ、出力の負荷抵抗RLに流れる過剰
の電流を防ぐ。
If load RL fails for some reason and output terminal M,
If there is a short circuit between N and N, or if excessive voltage is applied to the power supply terminal 7 and excessive current flows to the load resistor RL or the power supply terminal 9, the detection voltage VR of the overcurrent detection resistor 16 will be 0.7V.
The voltage rises above the current level, current also flows to the base of the NPN transistor, transistor 5.6 turns on, and the gate control signal S on the high voltage side
1 and 83 and lower the voltage of MOS transistor 1 on the high voltage side.
.. 3 is turned off to prevent excessive current flowing through the output load resistor RL.

なお、電流検出抵抗16による損失を防ぎ、かつ通常時
にはNPN)ランリスタがオンしないようにするために
、抵抗値は十分小さくする。
Note that the resistance value is made sufficiently small in order to prevent loss due to the current detection resistor 16 and to prevent the NPN (Npn) run lister from being turned on under normal conditions.

第2図は本発明の第2の実施例の回路図である。FIG. 2 is a circuit diagram of a second embodiment of the invention.

第1の実施例で説明した過電流検出部15のNPN)ラ
ンリスタ5.6のコレクタと低圧側のトランジスタ24
のゲート間にインバータ18゜1つを追加している。
The collector of the NPN) run lister 5.6 of the overcurrent detection unit 15 described in the first embodiment and the low voltage side transistor 24
One 18° inverter is added between the gates.

この実施例では、過剰電流がH型ブリッジに流れたとき
、H型ブリッジ出力部10aを構成する二つのMOSト
ランジスタ対のうち高圧電源端子7側のMOSトランジ
スタ1.3の対を共にオフさせると同時に接地端子8側
のMOS)ランデスタ2,4対をオンさせ負荷RLとト
ランジスタ2.4とで閉ループを構成する。
In this embodiment, when an excessive current flows through the H-type bridge, both of the pair of MOS transistors 1.3 on the high-voltage power supply terminal 7 side of the two MOS transistor pairs forming the H-type bridge output section 10a are turned off. At the same time, the pair of MOS Landestors 2 and 4 on the ground terminal 8 side is turned on to form a closed loop with the load RL and the transistor 2.4.

これにより過剰電流を検出した時、駆動中のモータにブ
レーキをかけて停止させる機能をもつという効果がある
This has the effect of having a function of applying a brake to the driving motor to stop it when excess current is detected.

上述の実施例でMOS)ランリスタとしてNチャネルM
O5FET、バイポーラトランジスタとしてNPNトラ
ンジスタを用いたが5、極性を選べば他のトランジスタ
の組合せでも同裸な効果が得られる。
In the above embodiment, N-channel M is used as a MOS) run lister.
Although NPN transistors were used as O5FETs and bipolar transistors5, the same effect can be obtained by combining other transistors as long as the polarity is selected.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明では、2個のMOSトランジ
スタ対より成るH型ブリッジ出力部を有する半導体出力
回路において、回路の過剰負荷電流を検出して制御信号
をクランプさせてH型ブリッジを構成する一部のMOS
)ランリスタをオフさせることによりMOSトランジス
タを破壊したり、チップのリードフレームを結ぶリード
線を溶断させてし才うということを防ぐことができる効
果がある。
As explained above, in the present invention, in a semiconductor output circuit having an H-type bridge output section consisting of a pair of two MOS transistors, an H-type bridge is configured by detecting an excessive load current of the circuit and clamping the control signal. Some MOS
) By turning off the run lister, it is possible to prevent damage to the MOS transistor or melting down of the lead wires connecting the lead frame of the chip.

また、モータ負荷の場合に一部のMOSトランジスタを
オンさせて、モータを含む閉回路を構成してモータを制
動する効果もある。
Further, in the case of a motor load, some MOS transistors are turned on, forming a closed circuit including the motor, and braking the motor.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の第1の実施例の回路図、第2図は本発
明の第2の実施例の回路図、第3図は従来の半導体出力
回路の一例の回路図である。 1〜4・・・nチャネルMO3)ランリスタ、5゜6・
・・NPN)ランリスタ、7・・・高圧電源端子、8・
・・共通ソース点、9・・・接地端子、10・・・H型
ブリッジ、11〜14・・・制御信号端子、15・・・
過電流検出部、16・・電流検出抵抗、17.18・・
・インバータ。
FIG. 1 is a circuit diagram of a first embodiment of the present invention, FIG. 2 is a circuit diagram of a second embodiment of the present invention, and FIG. 3 is a circuit diagram of an example of a conventional semiconductor output circuit. 1 to 4...n channel MO3) run lister, 5°6.
・・NPN) run lister, 7・High voltage power supply terminal, 8・
...Common source point, 9...Ground terminal, 10...H-type bridge, 11-14...Control signal terminal, 15...
Overcurrent detection section, 16...Current detection resistor, 17.18...
・Inverter.

Claims (1)

【特許請求の範囲】 1、2個のMOSトランジスタ対を有するブリッジ構成
の一方のトランジスタ対のゲート端にそれぞれゲート制
御信号を入力してブリッジ出力端子対間に負荷を接続す
るH型ブリッジ出力部を有する半導体出力回路において
、前記ブリッジ結線の低圧電源端子と低圧電源間に過電
流検出手段を設け、該過電流検出手段の出力する検出信
号を入力して前記ゲート制御信号をクランプして前記高
圧側トランジスタを遮断状態にする手段とを有すること
を特徴とする半導体出力回路。 2、前記H型ブリッジ出力部の他方のトランジスタ対の
ゲート端がインバータを介して前記一方のトランジスタ
のゲート端に対応してそれぞれ接続されていることを特
徴とする請求項1記載の半導体出力回路。
[Claims] An H-type bridge output section in which a gate control signal is input to each gate end of one transistor pair of a bridge configuration having one or two MOS transistor pairs, and a load is connected between a pair of bridge output terminals. In the semiconductor output circuit, an overcurrent detection means is provided between the low voltage power supply terminal of the bridge connection and the low voltage power supply, and a detection signal output from the overcurrent detection means is inputted to clamp the gate control signal to detect the high voltage. 1. A semiconductor output circuit comprising means for turning off a side transistor. 2. The semiconductor output circuit according to claim 1, wherein the gate ends of the other transistor pair of the H-type bridge output section are respectively connected to the gate ends of the one transistor via an inverter. .
JP2160177A 1990-06-19 1990-06-19 Semiconductor output circuit Pending JPH0449870A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2160177A JPH0449870A (en) 1990-06-19 1990-06-19 Semiconductor output circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2160177A JPH0449870A (en) 1990-06-19 1990-06-19 Semiconductor output circuit

Publications (1)

Publication Number Publication Date
JPH0449870A true JPH0449870A (en) 1992-02-19

Family

ID=15709508

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2160177A Pending JPH0449870A (en) 1990-06-19 1990-06-19 Semiconductor output circuit

Country Status (1)

Country Link
JP (1) JPH0449870A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005303969A (en) * 2004-03-17 2005-10-27 Nec Electronics Corp Overcurrent detecting circuit
CN109602551A (en) * 2018-11-21 2019-04-12 韩雪 The self-actuating brake circuit and control method of brush motor electric wheel-chair vehicle
CN114695319A (en) * 2020-12-28 2022-07-01 万国半导体国际有限合伙公司 Semiconductor package with smart power stage and electronic fuse solution

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005303969A (en) * 2004-03-17 2005-10-27 Nec Electronics Corp Overcurrent detecting circuit
CN109602551A (en) * 2018-11-21 2019-04-12 韩雪 The self-actuating brake circuit and control method of brush motor electric wheel-chair vehicle
CN114695319A (en) * 2020-12-28 2022-07-01 万国半导体国际有限合伙公司 Semiconductor package with smart power stage and electronic fuse solution

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