JPH0450751B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device using dynamic memory cells and a method for manufacturing the same.

[Technical background of the invention and its problems]

2. Description of the Related Art Conventionally, as a semiconductor memory device, a device in which a dynamic memory cell is integrated, consisting of one transistor element 1 and one capacitor element 2 as shown in FIG. 1, has been widely used. In the figure, 3 indicates a word line, and 4 indicates a pit line.

The capacitive element 2 of this type of memory cell is often composed of a MOS capacitor, and the gate insulating film of the capacitor part is, for example, 300 to 500 [〓] in a 64K-bit D-RAM, and about
It is said that the film thickness for a 1M bit D-RAM is 100 [〓] or less. When such a thin insulating film is used, its breakdown voltage is a major factor determining the yield of the product.

The causes of breakdown voltage failures in insulating films in MOS capacitors are often due to impurity contamination during the formation of the insulating film or defects in the insulating film itself, but defects due to electrostatic discharge damage that occur during the manufacturing process are also important. . In particular, reactive ion etching (RIE) is an etching process using charged particles.
As etching techniques that are unreliable for microfabrication, such as etching and sputter etching, have come to be used, electrostatic breakdown of the insulating film during the etching process has become an important failure mode. There is also the problem that electrostatic discharge damage occurs due to noise entering the power supply line during circuit operation, and this problem becomes particularly pronounced as the gate insulating film becomes thinner, such as 100 to 200 Å.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor memory device that can prevent electrostatic breakdown of a thin insulating film constituting a MOS capacitor during the manufacturing process and circuit operation, and that can improve element reliability and manufacturing yield. It is about providing.

Another object of the present invention is to provide a method for manufacturing a semiconductor memory device that can easily realize a semiconductor memory device that can improve the device reliability and manufacturing yield described above without requiring special processes. be.

[Summary of the invention]

The gist of the present invention is to bring a part of the conductive film constituting the memory capacitor into direct contact with a region of the opposite conductivity type provided on the surface of the semiconductor substrate to create a place for abnormal charges generated in the conductive film to escape. There is a particular thing.

That is, the present invention provides a semiconductor memory device in which a plurality of dynamic memory cells each consisting of a transistor element and a capacitor element are integrated. It is composed of a conductive film serving as a common electrode, and a part of the conductive film is directly connected to a region of a conductivity type opposite to that of the semiconductor substrate provided on the surface of the semiconductor substrate.

Further, in manufacturing the semiconductor memory device of the present invention, an insulating film for configuring the capacitive element of the memory cell is formed on the semiconductor substrate so that a portion of the substrate surface is exposed, and then a common electrode is formed on the entire surface. Forming a conductive film, then selectively etching the conductive film using a desired mask, leaving a part of the conductive film on the exposed substrate surface, and creating a conductivity type opposite to that of the substrate on the exposed substrate surface. This method involves doping with impurities.

〔Effect of the invention〕

According to the present invention, even if an abnormal charge is generated in a conductive film constituting a capacitive element of a memory cell, this charge can be quickly released through an opposite conductivity type region formed on the surface of a semiconductor substrate. For this reason,
It is possible to significantly reduce the defectiveness rate due to electrostatic breakdown of the thin insulating film of the memory capacitor portion during the manufacturing process and circuit operation, and therefore to significantly improve device reliability and manufacturing yield.

[Embodiments of the invention]

FIGS. 2a to 2e are cross-sectional views showing the manufacturing process of a semiconductor memory device according to an embodiment of the present invention. In addition,
This figure shows a case where a large number of memory capacitors are formed, and for the sake of simplicity, the step of forming a switch transistor element is omitted. Figure 2a
For example, after forming a field oxide film 12 for element isolation on a P-type silicon substrate 11, a thin gate insulating film 13 for a capacitor is formed with a thickness of about 100 Å. Here, the gate insulating film 13 may be a thermal oxide film, a thermal nitride film, or any other insulating film.

A mask is applied to the sample in the state shown in FIG. 2a, and a portion of the gate insulating film 13 is removed by etching. Next, as shown in FIG. 2B, a polycrystalline silicon film 14, which will become a gate electrode material, is deposited over the entire surface. Thereafter, phosphorus is diffused into the polycrystalline silicon film 14 by diffusion in POC ₃ , and the layer resistance of this polycrystalline silicon film 14 is lowered to 20 to 50 [Ω/□]. At this time, on the substrate surface from which the gate insulating film 13 has been removed, an N ⁺ diffusion layer 15 is formed by phosphorus diffusion as shown in FIG. 2c. In other words, the P-type silicon substrate 11 and the N ⁺ diffusion layer 15 on a part of the surface thereof.
A PN junction is formed by this.

Next, as shown in FIG. 2d, the polycrystalline silicon film 1
A photoresist 16 is formed in a desired pattern on 4, and the polycrystalline silicon film 14 is selectively etched using this resist 16 as a mask. For this etching, for example, an RIE method using a gas containing C such as C ₂ or C _x F _y C _z may be used. Then,
After removing the resist 16, as shown in FIG.
A wiring film 18 is formed. Furthermore, a dynamic memory cell is created by forming a switch transistor element (not shown). Note that a power supply voltage (for example, 5V) is applied to the A wiring film 18, or a ground potential is applied thereto.

FIG. 3 is a plan view showing an example of the arrangement of the dynamic memory cells prepared above, in which the polycrystalline silicon film 14 is formed to completely cover the N ⁺ diffusion layer 15. This is to prevent the silicon substrate 11 from being etched when the polycrystalline silicon film 14 is etched by the RIE method. As can be seen from FIG. 4, the polycrystalline silicon film 14 forms a common electrode commonly connected to a plurality of cells, and the N ⁺ diffusion layer 15 is formed outside the element region.

Thus, according to this embodiment, dielectric breakdown of the gate insulating film 13 during the manufacturing process can be prevented. That is, in the conventional method, when etching the polycrystalline silicon film 14 into a predetermined shape, C ⁺ , C ₂ ⁺ ,
Ions such as F ⁺ accumulate in the polycrystalline silicon film 14,
A large electric field is generated in the gate insulating film 13. Further, when the etching is completed and the gate electrode is formed, the gate electrode is completely electrically separated from the substrate 11, so that the charges in the gate electrode have nowhere to escape. Normally, 30 to 50
Over-etching of [%] is required, and during this over-etching, the electric field in the gate insulating film 13 increases more and more, eventually causing electrostatic breakdown and causing insulation failure of the gate insulating film 13. In fact, since the charge in the gate electrode flows in a concentrated manner to a portion of the insulating film 13 where the breakdown voltage is low, this portion is significantly deteriorated and the manufacturing yield is significantly reduced.

However, in this embodiment, as shown in FIG. 2d, a part of the gate electrode made of the polycrystalline silicon film 14 is in contact with the P-type silicon substrate 11 via the N ⁺ diffusion layer 15. The generated charge easily flows to the substrate 11. Therefore, problems such as the electric field in the gate insulating film 13 becoming abnormally large and causing dielectric breakdown of the gate insulating film 13 do not occur.

Furthermore, in this embodiment, since the gate electrode made of the polycrystalline silicon film 14 is connected to the N-type region of the PN junction, when the gate electrode is negatively charged with respect to the substrate 11, the PN junction is biased in the forward direction. The charged charges easily flow to the substrate 11. Conversely, when the gate electrode is charged with respect to the substrate 11, the PN junction is biased in the opposite direction, but a current of about 10 ^-2 to 10 ^-3 [A] flows in the opposite direction even with a small bias voltage. Therefore, it is sufficient to flow the charges generated during etching to the substrate 11. However, in order to further improve the reliability of the etching process, the
The reverse breakdown voltage of PN may be set to a value lower than the breakdown voltage of the gate insulating film 13. For example, when a thermal oxide film with a thickness of 100 [Å] is used as the gate insulating film 13, the breakdown voltage of this oxide film is about 10 [V], so the reverse breakdown voltage of the PN junction is set to 10 [V] or less. , for example, 8 [V]. This level of breakdown voltage characteristic is well within the achievable range by reducing the junction depth of the PN junction when forming the N ⁺ diffusion layer 15.

FIG. 4 and FIG. 5 are sectional views showing the main structure of other embodiments, respectively. Note that the same parts as in FIGS. 2a to 2e are denoted by the same reference numerals, and detailed explanation thereof will be omitted. In the embodiment shown in FIG. 4, the gate electrode polycrystalline silicon film 14 is etched to expose a part of the N ⁺ diffusion layer 15.
The A wiring film 18 is connected to the exposed portion of the insulating film 17 through a contact hole. Further, in the embodiment shown in FIG. 5, the polycrystalline silicon film 14 for gate electrode is formed so as to cover the entire surface of the N ⁺ diffusion layer 15, but this N ⁺ diffusion layer 15 is placed under the field oxide film 12. Provided N ⁺
provided on the surface of the substrate 11 via the diffusion layer 19
It is connected to the N ⁺ diffusion layer 20. And this N ⁺
The A wiring film 18 is connected to the diffusion layer 20 through a contact hole in the insulating film 17.
In this case, at least one mask alignment process is added before forming the gate electrode, and the diffusion layer 1 is
It is necessary to perform ion implantation or diffusion to form 9 and 20.

The embodiments shown in FIGS. 4 and 5 not only provide the same effects as the previously described embodiments, but also protect the memory capacitor section against surge voltages that come in from the outside on the power supply line. Dielectric breakdown of the gate insulating film 13 can be prevented. That is, A
If there is a contact resistance of r _c for the contact between the wiring film 18 and the N ⁺ diffusion layer 15, the A wiring film 18 is directly connected to the gate electrode in the previous embodiment, so the equivalent circuit is shown in FIG. As shown in
It is vulnerable to surge voltage from outside. On the other hand, in this embodiment, the A wiring film 18 is connected to the gate electrode via the contact resistor r _c , so the equivalent circuit is as shown in FIG. 6b, and the voltage applied to the gate electrode is connected to the PN junction. The reverse withstand voltage will not be exceeded. Therefore, if the reverse breakdown voltage of the PN junction made up of the N ⁺ diffusion layer 15 and the P-type silicon substrate 11 is set lower than the breakdown voltage of the gate insulating film 13, it can withstand surge voltage from the power supply line. Dielectric breakdown of the gate insulating film 13 is not caused.

Note that the present invention is not limited to the embodiments described above. For example, the formation of the N ⁺ diffusion layer does not need to be performed before etching the polycrystalline silicon film, and may be performed after the etching process. Further, the impurity doping method is not limited to diffusion in POC ₃ , but may be ion implantation or use of a crystalline silicon film doped with impurities in advance. Further, the memory cell structure is not limited to one having one transistor element and one capacitor element, and it goes without saying that the present invention can be applied to various types of memory cells that require a MOS capacitor. In addition, various modifications can be made without departing from the gist of the present invention.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing a conventional general dynamic memory cell, FIGS. 2 a to e are cross-sectional views showing the manufacturing process of a semiconductor memory device according to an embodiment of the present invention, and FIG. 3 is a diagram showing the above embodiment. A plan view showing the memory cell arrangement structure of the device, FIGS. 4 and 5 are cross-sectional views showing the main structure of other embodiments, and FIGS. 6 a and b.
FIG. 2 is an equivalent circuit diagram for explaining the operation of each of the above embodiments. 1... Transistor element, 2... Capacitive element, 3
...Word line, 4...Bit line, 11...
... silicon substrate (semiconductor substrate), 12 ... field oxide film, 13 ... gate insulating film, 14 ... polycrystalline silicon film (conductive film), 15 ... N ⁺ diffusion layer (opposite conductivity type region), 16 ... ...Resist, 17...Insulating film, 18...A wiring film, 19,20...N ⁺
Diffusion layer.

Claims (1)

[Scope of Claims] 1. In a semiconductor memory device in which a plurality of dynamic memory cells each consisting of a transistor element and a capacitive element are integrated, the capacitive element of the memory cell is provided on a semiconductor substrate and on the substrate with an insulating film interposed therebetween. A conductive film is formed to serve as a common electrode, and a portion of the conductive film is directly connected to a region of the opposite conductivity type to the semiconductor substrate, which is provided separately from the diffusion region of the transistor element of the semiconductor substrate. A semiconductor memory device characterized by the following. 2. A patent characterized in that the PN junction formed between the region of the opposite conductivity type on the surface of the semiconductor substrate and the semiconductor substrate has a reverse breakdown voltage set to be lower than the breakdown voltage of the insulating film. Claim 1
The semiconductor storage device described in 1. 3. In a method for manufacturing a semiconductor memory device by integrating a plurality of dynamic memory cells each consisting of a transistor element and a capacitive element, an insulating film for configuring the capacitive element of the memory cell is placed on a semiconductor substrate so that the surface of the substrate is the transistor element. A step of forming a conductive film to be partially exposed in a region different from the diffusion region of the substrate, a step of integrally forming a conductive film on the entire surface to become a common electrode and an electrode connected to the exposed substrate region, and a step of forming the conductive film using a desired mask. It is characterized by comprising the steps of selectively etching the film and leaving a part of the conductive film on the exposed substrate surface, and doping the exposed substrate surface with an impurity that creates a conductivity type opposite to that of the substrate. A method for manufacturing a semiconductor memory device.