JPH0450962B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to changes in the phase of a detection signal e ₀ output from a rotation angle detector such as a resolver used to detect mechanical rotational position and speed. This relates to a position/velocity detection circuit using a phase-locked loop circuit that tracks the phase of a position and velocity, and is characterized by a phase-locked loop operation with particularly high stability. It is related to.

[Conventional technology] Conventionally, in the fields of machine tools, robots, etc.
Position control and speed control require various position and speed detectors, and in particular, resolvers that detect rotation angles with high reliability in electromagnetic equipment are widely used for position and speed detection.

When using this resolver, for example, if a resolver with a number of magnetic pole pairs P is excited with two-phase excitation voltages e _x and e _y (e _x = sinωt, e _y = cosωt, where ω = 2π) at frequencies, the resolver rotation axis In response to changes in the mechanical rotation angle θ _n , a detection signal e ₀ [e ₀ −sin (ωt±P·θ _n )] is output from the output winding (also referred to as a detection winding) of the resolver. The change in phase ±P・θ _n of this detection signal e ₀ is processed by an electronic circuit, and various methods are used to convert the resulting pulse train signal, digital signal, and analog signal into the required position/velocity detection signal. Signal processing means have been devised. As an effective means for this signal processing, the detection signal e ₀
There is a PLL position/velocity detection method that uses a PLL circuit that performs a phase tracking operation according to changes in the phase ±P·θ _n , that is, a phase locked loop (hereinafter referred to as PLL) operation.

In order to explain the basic operation of the conventional PLL type position/velocity detection method, FIG. 8 shows a block diagram of a conventional PLL type detection circuit. In Figure 8, 1
is the aforementioned detection signal e ₀ [=sin(ωt±P・θ _n ±Δθ)]
and the feedback signal e _pa [=cos(ωt±
P・θ _n )] as input signals, two signals e ₀・
This is a phase detector that outputs a DC voltage signal E ₁ proportional to the phase difference ±Δθ of e _0a . Note that due to the characteristics of the phase detector 1 used here, as mentioned above, the phase difference between the sine wave signal e ₀ and the cosine wave signal e _0a (π/2) ±
Only changes in phase ±Δθ of Δθ are handled. Furthermore, when the change in phase ±P·θ _n is expressed by frequency Δ, it is given by the following equation (1). The symbol θ· _n is the speed of rotation θ _n , which has a unit of one revolution per second (rps).

Δ=P・θ・_n /2π (1) 2 in Fig. 8 is a proportional/integral amplifier (hereinafter referred to as PI amplifier) that amplifies the signal _E1 proportionally and integrally and outputs a DC voltage signal _E2 . , 3 is a voltage controlled oscillator (hereinafter referred to as VC oscillator) which uses the signal E ₂ as an input signal and outputs a pulse train signal P ₁ having a frequency proportional to the voltage value of the signal E ₂ , 4 is the pulse train signal P ₁ By counting the number of pulses _of
Δ) (K is a relatively large positive integer, for example 2 ⁸ ~
A binary counting circuit 5 outputs a pulse train signal P ₂ having a pulse train signal P ₂ having a signal D ₁ (2 ¹⁰ ); 6 is a memory circuit that stores digital values in advance and performs a signal conversion operation so as to output the digital signal D _{2 ;}
is the analog cosine wave feedback signal e _0a [=
cos(ωt±P·θ _n )] and outputs the converted signal (hereinafter referred to as a D/A converter).

To explain the operation of the above PLL method detection circuit,
First, in the phase detector 1, the two signals e ₀ ,
Multiplying e _0a to obtain the signal shown in equation (2), and removing the double frequency component of the first term of equation (2) using a low-pass filter, when the phase difference ±Δθ is a small value, a DC voltage proportional to ±Δθ is obtained. A value signal E ₁ is output. [Refer to formula (3)] e ₀ ×e _0a = sin (ωt±P・θ _n ±Δθ) ×cos (ωt±P・θ _n ) = (1/2)・sin {2 (ωt±P・θ _n ) ±Δθ) + (1/2)・sin (±Δθ) (2) E ₁ = (1/2)・sin (±Δθ) ≒ (1/2)・(±Δθ) (3) Next , the signal E1 is amplified by a PI amplifier 2 to obtain a signal _E2 . This signal E ₂ is converted into a pulse train signal P ₁ by the VC oscillator 3. The frequency of this signal P ₁ is proportional to the voltage value of signal E ₂ . Further, the explanation will be continued using the operational waveform diagram of each signal shown in FIG. When the pulse train signal P ₁ [Fig. 9a] output from the above VC oscillator 3 is input to the counting circuit 4,
The counting circuit 4 counts the number of pulses of the signal _P1 ,
Pulse train signal P ₂ with frequency K (+Δ) [Figure 9b]
At the same time, it outputs a digital signal D ₁ [Fig. 9 c] whose digital value repeatedly changes from zero to D _1a and has a period T ₀ [1/(±Δ)]. The digital signal _D1 is sent to a memory circuit 5 and a D/A converter 6.
Convert the signal through the cosine wave feedback signal
e _0a (dotted line in FIG. 9) is obtained, and the signal is fed back to the phase detector 1. The phase of the signal e _0a is tracked so as to maintain an electrical angle of π/2 with the signal e ₀ (solid line d in FIG. 9).

Next, the relationship between the changes in the signals of each part with respect to the changes in the phase difference Δθ will be shown.

Phase difference Δθ lead [lag] → signal +E ₁ [−E ₁ ] → signal E ₂ increase [decrease] → frequency increase [decrease] of signal P ₁
→Frequency K (+Δ) of signal P ₂ , [K (-Δ)]
→ Period T ₀ is small [large] → Frequency K (+Δ), [K (-Δ)] of signal e _0a → Δθ becomes zero.

In such a PLL operating state, the change in the phase ±P・θ _n of the signal e ₀ is expressed as (a) the change in the frequency K (±Δ) of the pulse train signal P ₂ (b) the change in the digital value of the digital signal D ₁ Change (c) It is possible to convert the digital signal D ₁ into a change in the period T ₀ and use these signals as position/speed detection signals corresponding to changes in the rotation angle θ _n .

[Problems to be Solved by the Invention] As explained above, in the PLL operation of the PLL method detection circuit shown in FIG.
Feedback signal for input signal e ₀ of Δ)
In order to improve the phase tracking characteristics of e _0a , the PLL operation can be stabilized by adjusting the circuit constants of the PI amplifier 2, and some results can be obtained.
However, in order to ensure the stability of the phase ±K・P・θ _n of the high frequency K (±Δ) signal D ₂ output from the counting circuit 4, it is necessary to stabilize it by adjusting the circuit constants of the conventional PI amplifier. Difficult in Law and PLL
There was a problem that position/speed detection signals with improved stability of operation could not be obtained.

An object of the present invention is to provide a PLL type position/velocity detection circuit characterized by highly stable PLL operation in PLL type position/velocity detection.

[Means for solving the problems] The structure of the present invention for solving the above problems is as follows:
The following description will be made using FIGS. 1 to 7 and 9, which correspond to embodiments.

First, the position/velocity detection circuit of the invention of claim 1 uses a sine wave detection signal of frequency ±Δ from the rotation angle detector and a feedback signal described _below .
a phase detector 1 which receives the signal E _0a and outputs a DC component signal E ₁ according to the phase difference Δθ between both signals;
an amplifier 2 that at least proportionally amplifies E ₁ and outputs a signal E ₂ ; a VC oscillator 3 that outputs a pulse train signal P ₁ with a frequency proportional to the voltage of the signal E ₂ ;
a counting circuit 4 that counts the number of pulses of the pulse train signal P ₁ and outputs a pulse train signal P ₂ of frequency K (± _{Δ) and a binary digital signal D 1 ;} a memory circuit 5 which outputs a cosine wave digital signal D ₂ ; and a memory circuit 5 which receives the digital signal D ₂ and outputs an analog cosine wave signal.
In a PLL position/velocity detection circuit comprising a D/A converter 6 which outputs e _0a and feeds the signal back to the phase detector 1, a pulse oscillator outputs at least one pulse train signal P _r1 having a constant frequency. 7, and a pulse train having a frequency equal to the frequency difference between the two signals from different output terminals in response to at least the pulse train signal P _r1 and the pulse train signal _P2 from the counting circuit 4, depending on the height relationship between the frequencies of the two signals. Frequency difference/pulse converter (hereinafter referred to as F/P) that outputs signal P ₃₁ or P ₃₂
converter) 8 _, and _a frequency/ _voltage converter ( _hereinafter referred to as A F/V converter) 9 receives the signal +E ₃ or -E ₃ and outputs a signal E ₄ having a differential component of the signal.
The differential amplifier 10 feeds _E4 back to the input side of the amplifier 2 or the VC oscillator 3.

Further, the position/velocity detection circuit of the invention of claim 2 includes the differential amplifier 10 of the invention of (1) above.
, two signals E ₄ and E ₆ having different differential components of the signal +E ₃ or -E ₃ are generated.
The signal _E4 is fed back to the input side of the amplifier 2, and the signal _E6 is fed back to the input side of the amplifier 2.
A differential amplifier 10 is provided on the input side of the VC oscillator 3 for feedback.

[Operation of the Invention] The present invention provides the above means of the invention (1), in which a sine wave detection signal with a frequency ±Δ from a rotation angle detector is used.
A PLL type detection circuit that receives e ₀ , phase detector 1,
The pulse train signal P 2 of frequency K (±Δ) output from the counting circuit 4 via the amplifier 2 and the VC oscillator ₃ is sent to the F/P converter 8 together with the pulse train signal P _r1 of constant frequency from the pulse oscillator 7. and outputs a pulse train signal P ₃₁ or P ₃₂ having a frequency K·Δ that is the frequency difference between the two pulse train signals from different output terminals of the F/P converter 8 according to the high-low relationship between the frequencies of the two pulse train signals. . Then, this signal P ₃₁ or P ₃₂ is input to the F/V converter 9 to output a DC positive voltage signal +E ₃ or negative voltage signal -E ₃ proportional to the frequency of the signal. Next, this signal +E ₃ or -E ₃ is sent to the differential amplifier 10.
A signal E ₄ having a differential component of the signal is obtained, and the signal E ₄ is fed back to the input side of the amplifier 2 or the VC oscillator 3. The feedback effect of such a signal increases the stability of the PLL operation of the PLL type detection circuit. Then, a change in the voltage of the signal +E ₃ or -E ₃ or the frequency of the pulse train signal P ₂ , or a change in the digital value or period of the digital signal D ₁ is used to detect the position/velocity according to the detection signal e ₀ . Used as a signal. This improves the accuracy of position/velocity detection.

Furthermore, in the means of the invention (2), the differential amplifier 1 inputs the signal +E ₃ or -E ₃ .
0, two signals E ₄ and E ₆ having different differential components of the input signal are output, and the signal E ₄ is fed back to the input side of the amplifier 2, and the signal E ₆ is fed back to the input side of the VC oscillator 3. feed back to the input side. The feedback effect of these two signals greatly increases the stability of the PLL operation of the PLL type detection circuit. This greatly improves the accuracy of position/velocity detection.

[Example] Hereinafter, an example of the present invention will be described based on the drawings. In FIG. 1, the same reference numerals as in FIG. 8 indicate parts that perform the same operations. In FIG. 1, reference numeral 7 denotes a pulse oscillator, which outputs a pulse train signal P _r1 of a constant frequency K· and a pulse train signal P _r2 of a constant frequency 2K·. 8 is an F/P converter, and this F/P converter receives the above signal.
P _r1 and P _r2 and the frequency K output from the counting circuit 4
(±Δ) as an input signal, the _{frequency difference between the signals P r1 and} P _r2 is ±K·Δ, and the frequency K·Δ is, depending on the polarity of the difference,
When the polarity is (+), the pulse train signal P ₃₁ is output, and when the polarity is (-), the pulse train signal P ₃₂ is output.

9 is an F/V converter, and this F/V converter takes the above signal P ₃₁ or P ₃₂ as an input signal and converts the signal
A signal +E ₃ (or −E ₃ ) having a DC voltage value proportional to the frequency K·Δ of P ₃₁ (or P ₃₂ ) is output. 10 is a differential amplifier, which takes the above signal +E ₃ (or -E ₃ ) as an input signal and generates two signals E ₄ and E ₆ consisting of differential components of the signal (both have different differential components). ) is output. 11 is a first adder provided on the signal line between the phase detector 1 and the PI amplifier 2, and this adder receives the above-mentioned signal.
_E1 and signal _E4 are added and subtracted, and the signal _E5 is differentially outputted so that the signal _E4 becomes a negative feedback signal. This signal _E5 is input to the PI amplifier 2. 1
2 is a second adder provided on the signal line between the PI amplifier 2 and the VC oscillator 3, and this adder adds and subtracts the signal E ₂ and the signal E ₆ , and the signal E ₆ is a negative feedback signal. It operates so that the signal _E7 is output. This signal E ₇ is input to the VC oscillator 3.

In the PLL type position/velocity detection circuit shown in FIG. 1, the stability of the PLL operation is extremely good due to the feedback effect of the above-mentioned signals E ₄ and E ₆ . As a result, it is possible to perform highly accurate position/velocity detection based on the voltage of the output signal ± _E3 with respect to the input detection signal _e0 , and also to detect the frequency change of the pulse train signal _P2 or the digital value of the digital signal D1. Highly accurate position/velocity detection can be performed based on changes in the period, etc.

FIG. 2 is a block diagram showing a specific example of the F/P converter 8, in which 8a is a non-alternative OR circuit (hereinafter referred to as
EXOR), 8b and 8c are D-type flip-flop circuits (hereinafter referred to as D-FF circuits), and 8d is a general quadrupling circuit. In Figure 2, when a signal P _r2 of frequency 2·K· is input to one terminal of EXOR8a and a signal P _r1 of frequency K·f is input to the other terminal, the output of EXOR8a is
A signal P ₂₁ with a frequency K· having a two-phase relationship with P _r1 is obtained. Further, the signal P _r1 is input to the D terminal of the D-FF circuit 8b, the signal P ₂₁ is input to the D terminal of the D-FF circuit 8c, and the signal P ₂ of the frequency K·(±Δ) is input to the D terminal.
-When input to each CP terminal of FF circuits 8b and 8c,
Output signals _P22 ( ₂₂ ) and _P23 ( ₂₃ ) are output from the output terminals Q() of the D-FF circuits 8b and 8c, respectively. Signals ₂₂ and ₂₃ are inverted versions of signals P ₂₂ and P ₂₃ , respectively.

3a to 3d show the above signals P _r2 , P _r1 , P ₂₁ ,
In the operation waveform diagram of P ₂ , each horizontal axis is time t,
The vertical axis shows the high level and low level states of each signal. In FIGS. 3a to 3d, the signals P _r1 and P ₂₁ have a two-phase relationship with a constant period T/K. The period T ₀ /K of the signal P ₂ does not change when the phase of the input signal e ₀ does not change (Δ=0) and is equal to the above period T/K, and the phase of the signal e ₀ is When it is changing (|Δ|>0), the period changes to become shorter (or longer) depending on the lead (or lag) of the phase.

Furthermore, when the frequency K (±Δ) of the signal P ₂ changes, the frequency difference with each frequency K of the signals P _r1 and P ₂₁ ± the period of K Δ 1/(K Δ) = 4 times T ₃ A two-phase pulse train signal P ₂₂ ( ₂₂ ) with a period of 4·T ₃ ,
_P23 ( ₂₃ ) is output from the Q() terminals of the D-FF circuits 8b and 8c. When the signals P ₂₂ and P ₂₃ are changing at the signal frequency +K・Δ (or −K・Δ), the signals P 22 and P 23 are as shown in FIG. 4 a, b [or FIG. 5 a, b]
As shown in , signal P22 leads (or lags) signal P23. In addition, signal ₂₂ ,
₂₃ is a signal obtained by inverting the signals P ₂₂ and P ₂₃ as described above, and although they have a two-phase relationship with each other, the above signals P ₂₂ , ₂₂ , P ₂₃ , which are not shown in FIGS. _{twenty three}
is input to the quadrupling circuit 8d, its output terminal 0
A signal P ₃₁ or P ₃₂ is output from 1 or 02. These signals P ₃₁ and P ₃₂ have a frequency difference of +
When K・Δ, as shown in Figure 4 c and d,
When the signal P ₃₁ is output and the signal P ₃₂ is not output, and the above frequency difference is −K・Δ, Fig. 5 c, d
As shown in FIG. 3, the signal P ₃₁ is not output, but the signal P ₃₂ is output.

FIG. 6 is a circuit diagram showing a specific example of the F/V converter 9, where R ₁ to R ₄ are resistors, C ₁ and C ₂ are capacitors, and A
is an amplifier. In the same figure, when the input signal P ₃₁ (or P ₃₂ ) is input as a pulse train signal of frequency K·Δ as shown in FIG. 4 c [or FIG. 5 d],
It is smoothed by a resistor-capacitor circuit (C ₁ R ₁ and C ₂ R ₂ circuits) and amplified by amplifier A, and a DC voltage signal +E3 (or -E ₃ ) is output.

Figure 7 shows the characteristics of the voltage value of the output signal ±E ₃ with respect to the frequency K and Δ of the input signals P ₃₁ and P _32. When the frequency difference is +K and Δ, the output signal is +E ₃ (curve A When the frequency difference is −K·Δ, the output signal becomes −E ₃ (represented by curve B).

Next, a modification of the embodiment shown in FIG. 1 will be described. In the above embodiment, a pulse train signal of frequency K (±Δ) is sent from the counting circuit 4 to the F/P converter 8.
P ₂ , and a pulse train signal P _r1 with a frequency of K· and a pulse train signal P _r2 with a frequency of 2·K· from the pulse oscillator 7, respectively, to generate a pulse train signal P ₃₁
Alternatively, P ₃₂ was obtained, but instead of the signal P _r2 , the pulse train signal P ₂ ' with a frequency of 2K (±Δ) was output from the counting circuit 4 separately from the signal P ₂ , and the signal P ₂ in FIG. , the above signal P _r1 in place of the signal P _r2 in FIG. 1, and the above signal P ₂ ' in place of the signal P r2 in FIG.
Even if the above signal P ₂ is used instead of P _r1 , the pulse train signal P ₃₁ or P ₃₂ can be obtained similarly to the above embodiment. In short, the F/P converter 8 is
The signal P ₃₁ or P ₃₂ is output based on the input of at least the above-mentioned signal P ₂ and signal P _r1 .

In the embodiment shown in FIG. 1, two adders 11,
12 is provided and different feedback signals are applied to each adder, however, highly stable PLL operation can be performed using either one of the adders and the feedback signal.

In addition, in the above embodiment, a PI amplifier is used as the amplifier 2, but even if a normal proportional amplifier is used instead, the same means as in the above embodiment can be used to achieve highly stable PLL operation. can be obtained.

Furthermore, if a multiplier type D/A converter is used, the phase detector 1 and the D/A converter 6 can be configured as an integrated circuit.

[Effects of the Invention] As explained above, according to the present invention, a sine wave detection signal e ₀ of frequency ±Δ is received from a rotation angle detector, and the phase of the signal e 0 is tracked by a change in the phase of the signal e ₀ .
In the PLL detection circuit, a pulse train signal P ₂ having a higher frequency K (±Δ) than the signal e ₀ described above
, the frequency K of the frequency difference between this signal and the signal _e0
A frequency difference/pulse converter converts the signal P ₃₁ or P ₃₂ into a pulse train signal P ₃₁ or P ₃₂ with Δ.
is converted into a DC voltage signal +E ₃ or -E ₃ using a frequency/voltage converter, and then the signal +E 3 or -E 3 is converted into a DC voltage signal +E ₃ or -E ₃ .
A signal E ₄ having a differential component of the signal is obtained by a _differential amplifier from The stability of the PLL operation of the PLL method detection circuit can be improved. Thereby, the accuracy of position/velocity detection can be improved.

According to the second aspect of the invention, the signal +E ₃ or -E ₃ is processed by a differential amplifier to generate two signals E 4 , having different differential components of the signal.
E ₆ is obtained, and the signal E ₄ is fed back to the input side of the amplifier after the phase detector, and the signal E ₆ is also fed back to the input side of the voltage controlled oscillator, so that the PLL method detection The stability of the circuit's PLL operation can be greatly improved. Thereby, the accuracy of position/velocity detection can be greatly improved.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a block diagram showing a specific example of an F/P converter used in the present invention, Figs. 3 a to d, and Figs. 4 a to d.
5a to 5d are signal waveform diagrams for explaining the operation of the F/P converter in FIG. 2, and FIG. 6 is a circuit diagram showing a specific example of the F/V converter used in the present invention.
Fig. 7 is a characteristic curve diagram for explaining the operation of the F/V converter shown in Fig. 6, Fig. 8 is a block diagram of a conventional PLL type detection circuit, and Figs. 9 a to d are the circuits shown in Fig. 8. FIG. 3 is a signal wave diagram for explaining the operation of FIG. 1... Phase detector, 2... PI amplifier, 3...
VC oscillator, 4... counting circuit, 5... memory circuit,
6...D/A converter, 7...Pulse oscillator, 8...
...F/P converter, 9...F/V converter, 10...
Differential amplifier, 11...first adder, 12...second adder.

Claims (1)

[Claims] 1. Receives a sine wave detection signal e ₀ of frequency ±Δ from a rotation angle detector and a feedback signal e _0a (described later), and generates a DC component signal E ₁ according to a phase difference Δθ between the two signals. a phase detector which outputs a signal E ₂ by at least proportionally amplifying said signal E ₁ ;
a voltage controlled oscillator that outputs a pulse train signal _P1 with a frequency proportional to the voltage of the signal _E2 , and a pulse train signal with a frequency K (±Δ) by counting the number of pulses of the pulse train signal _P1 . a counting circuit that outputs P ₂ and a binary digital signal D ₁ ; a memory circuit that outputs a cosine wave digital signal D ₂ corresponding to the digital value of the digital signal D ₁ ; and a memory circuit that receives the digital signal D ₂ . A phase-locked loop position/velocity detection circuit comprising: a digital/analog converter that outputs an analog cosine wave signal _e0a and feeds the signal back to the phase detector; a pulse oscillator that outputs a signal P _r1 ; and a pulse oscillator that receives at least the pulse train signal P _r1 and the pulse train signal P ₂ from the counting circuit and outputs the frequencies of the two signals from different output terminals according to the high-low relationship between the frequencies of the two signals. Pulse train signal P ₃₁ with difference frequency
or a frequency difference/pulse converter that outputs P ₃₂ and a frequency/voltage that receives the pulse train signal P ₃₁ or P ₃₂ and outputs a direct current positive voltage signal +E ₃ or negative voltage signal −E ₃ proportional to the frequency of the pulse train signal P 31 or P 32. a converter; and a differential amplifier that receives the signal + _E3 or _-E3 , outputs a signal _E4 having a differential component of the signal, and feeds the signal _E4 back to the input side of the amplifier or voltage controlled oscillator. A phase-locked loop position/velocity detection circuit. 2. A phase detector which receives a sine wave detection signal e ₀ of frequency ±Δ from the rotation angle detector and a feedback signal e _0a (described later) and outputs a DC component signal E ₁ according to the phase difference Δθ between the two signals. , amplify the signal _E1 at least proportionally to obtain a signal
an amplifier that outputs _E2 , a voltage controlled oscillator that outputs a pulse train signal _P1 with a frequency proportional to the voltage of the signal _E2 , and a voltage controlled oscillator that counts the number of pulses of the pulse train signal _P1 and calculates the frequency K (±Δ). a counting circuit that outputs a pulse train signal P ₂ and a binary digital signal D ₁ ; a memory circuit that outputs a cosine wave digital signal D ₂ corresponding to the digital value of the digital signal _{D 1} ; a digital/analog converter that outputs an analog cosine wave signal e _0a in response to the signal and feeds the signal back to the phase detector; a pulse oscillator that outputs _two pulse train signals _{P r1} ; A pulse train signal P ₃₁ with a frequency difference of
or a frequency difference/pulse converter that outputs P ₃₂ and a frequency/voltage that receives the pulse train signal P ₃₁ or P ₃₂ and outputs a direct current positive voltage signal +E ₃ or negative voltage signal −E ₃ proportional to the frequency of the pulse train signal P 31 or P 32. a converter; receiving the signal +E ₃ or -E ₃ and outputting signals E ₄ and E ₆ having different differential components of the signal; feeding back the signal E ₄ to the input side of the amplifier _; a differential amplifier that feeds back the voltage to the input side of the voltage controlled oscillator.