JPH0451042U - - Google Patents
Info
- Publication number
- JPH0451042U JPH0451042U JP9001590U JP9001590U JPH0451042U JP H0451042 U JPH0451042 U JP H0451042U JP 9001590 U JP9001590 U JP 9001590U JP 9001590 U JP9001590 U JP 9001590U JP H0451042 U JPH0451042 U JP H0451042U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- outputs
- circuit
- output
- sine wave
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 6
- 230000005856 abnormality Effects 0.000 claims description 5
- 230000003321 amplification Effects 0.000 claims description 4
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims 4
- 230000002159 abnormal effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Stand-By Power Supply Arrangements (AREA)
Description
第1図は本考案の実施例の概要を示すブロツク
図、第2図は本考案の他の実施例の要部を示すブ
ロツク図、第3図は第1図の実施例の動作説明用
信号波形図、第4図は第1図の実施例の要部の具
体的な構成例を示す結線図、第5図は従来のイン
バータ出力異常検出手段の例を示すブロツク図、
第6図は第5図の検出手段の動作説明用信号波形
図である。
3……インバータ回路、5……フイルタ回路、
6……切換スイツチ、12……基準正弦波電圧発
生回路、13……誤差増幅回路、14……搬送波
発生回路、15……PWM制御回路、16……ド
ライブ回路、17,17′……直流電圧加算回路
、18,18′……比較器、19……切換スイツ
チ制御回路。
FIG. 1 is a block diagram showing an outline of an embodiment of the present invention, FIG. 2 is a block diagram showing main parts of another embodiment of the present invention, and FIG. 3 is a signal for explaining the operation of the embodiment of FIG. 1. 4 is a wiring diagram showing a specific example of the configuration of the main part of the embodiment shown in FIG. 1, FIG. 5 is a block diagram showing an example of a conventional inverter output abnormality detection means,
FIG. 6 is a signal waveform diagram for explaining the operation of the detection means in FIG. 5. 3... Inverter circuit, 5... Filter circuit,
6... Selector switch, 12... Reference sine wave voltage generation circuit, 13... Error amplification circuit, 14... Carrier wave generation circuit, 15... PWM control circuit, 16... Drive circuit, 17, 17'... DC Voltage addition circuit, 18, 18'... Comparator, 19... Changeover switch control circuit.
Claims (1)
制御されてフイルタ回路5を通し正弦波交流電力
を出力する半導体開閉素子制御・インバータ回路
3と、 前記インバータ回路3の出力正常時には該出力
を負荷へ供給し、該出力の異常時には切換信号に
制御されて商用電源電力を負荷へ切換えて出力す
る切換スイツチ6と、 商用電源電圧に位相同期した基準正弦波電圧を
出力する基準正弦波電圧発生回路12と、 前記インバータ回路3の出力帰還電圧と前記基
準正弦波電圧との差に基づいて誤差増幅信号を出
力する誤差増幅回路13と、 商用電源周波数より所定の高周波の搬送波信号
を前記誤差増幅信号によりパルス幅変調したPW
M制御信号を出力して前記インバータ回路3の半
導体開閉素子を開閉制御するPWM制御回路15
とからなる無停電交流電力供給装置において、 前記基準正弦波電圧を入力として該電圧に所定
の大きさの正及び負の直流電圧をそれそれ加算・
重畳して前記誤差増幅信号に対し所定の大小関係
を持つ2つの参照信号を出力する直流電圧加算回
路17と、 前記誤差増幅信号を前記2つの参照信号と比較
して前記誤差増幅信号の大きさが前記2つの参照
信号により規定される所定の範囲を越えたときイ
ンバータ出力異常検出信号を出力する比較器18
と、 前記インバータ出力異常検出信号の入力により
前記切換スイツチ6へ切換信号を出力する切換ス
イツチ制御回路19とを具備することを特徴とす
る無停電交流電力供給装置。 (2) 直流電力が入力され、駆動信号により開閉
制御されてフイルタ回路5を通し正弦波交流電力
を出力する半導体開閉素子制御・インバータ回路
3と、 前記インバータ回路3の出力正常時には該出力
を負荷へ供給し、該出力の異常時には切換信号に
制御されて商用電源電力を負荷へ切換えて出力す
る切換スイツチ6と、 商用電源電圧に位相同期した基準正弦波電圧を
出力する基準正弦波電圧発生回路12と、 前記インバータ回路3の出力帰還電圧と前記基
準正弦波電圧との差に基づいて誤差増幅信号を出
力する誤差増幅回路13と、 商用電源周波数より所定の高周波の搬送波信号
を前記誤差増幅信号によりパルス幅変調したPW
M制御信号を出力して前記インバータ回路3の半
導体開閉素子を開閉制御するPWM制御回路15
とからなる無停電交流電力供給装置において、 前記基準正弦波電圧を入力として該電圧に所定
の大きさの正及び負の直流電圧をそれそれ加算・
重畳して前記インバータ回路3の出力帰還信号に
対し所定の大小関係を持つ2つの参照信号を出力
する直流電圧加算回路17′と、 前記基準正弦波電圧を同位相した前記インバー
タ回路3の出力帰還信号を前記2つの参照信号と
比較して前記出力帰還信号の大きさが前記2つの
参照信号により規定される所定の範囲を越えたと
きインバータ出力異常検出信号を出力する比較器
18′と、 前記インバータ出力異常検出信号の入力により
前記切換スイツチ6へ切換信号を出力する切換ス
イツチ制御回路19とを具備することを特徴とす
る無停電交流電力供給装置。[Claims for Utility Model Registration] (1) A semiconductor switching element control/inverter circuit 3 into which DC power is input, which is controlled to open and close by a drive signal and outputs sinusoidal AC power through a filter circuit 5; and the inverter circuit 3. When the output is normal, the output is supplied to the load, and when the output is abnormal, it is controlled by the switching signal to switch and output the commercial power supply power to the load. a reference sine wave voltage generation circuit 12 that outputs a reference sine wave voltage; an error amplification circuit 13 that outputs an error amplified signal based on the difference between the output feedback voltage of the inverter circuit 3 and the reference sine wave voltage; PW in which the carrier wave signal of is pulse width modulated by the error amplified signal.
A PWM control circuit 15 that outputs an M control signal to control opening and closing of the semiconductor switching elements of the inverter circuit 3.
An uninterruptible AC power supply device comprising: inputting the reference sine wave voltage and adding positive and negative DC voltages of predetermined magnitude to the reference voltage;
a DC voltage adder circuit 17 that outputs two reference signals that are superimposed and have a predetermined magnitude relationship with respect to the error amplified signal, and compares the error amplified signal with the two reference signals to determine the magnitude of the error amplified signal. a comparator 18 that outputs an inverter output abnormality detection signal when exceeds a predetermined range defined by the two reference signals;
and a changeover switch control circuit 19 that outputs a changeover signal to the changeover switch 6 in response to input of the inverter output abnormality detection signal. (2) A semiconductor switching element control/inverter circuit 3 into which DC power is input, which is controlled to open and close by a drive signal and outputs sinusoidal AC power through a filter circuit 5; and when the output of the inverter circuit 3 is normal, the output is a load. a changeover switch 6 that switches and outputs commercial power supply power to the load under the control of a switching signal when the output is abnormal, and a reference sine wave voltage generation circuit that outputs a reference sine wave voltage that is phase-synchronized with the commercial power supply voltage. 12; an error amplification circuit 13 that outputs an error amplification signal based on the difference between the output feedback voltage of the inverter circuit 3 and the reference sine wave voltage; PW modulated by pulse width
A PWM control circuit 15 that outputs an M control signal to control opening and closing of the semiconductor switching elements of the inverter circuit 3.
An uninterruptible AC power supply device comprising: inputting the reference sine wave voltage and adding positive and negative DC voltages of predetermined magnitude to the reference voltage;
a DC voltage adder circuit 17' that outputs two reference signals that are superimposed and have a predetermined magnitude relationship with respect to the output feedback signal of the inverter circuit 3; and an output feedback of the inverter circuit 3 that has the same phase as the reference sine wave voltage. a comparator 18' that compares the signal with the two reference signals and outputs an inverter output abnormality detection signal when the magnitude of the output feedback signal exceeds a predetermined range defined by the two reference signals; An uninterruptible AC power supply apparatus comprising a changeover switch control circuit 19 that outputs a changeover signal to the changeover switch 6 in response to an input of an inverter output abnormality detection signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9001590U JPH0451042U (en) | 1990-08-30 | 1990-08-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9001590U JPH0451042U (en) | 1990-08-30 | 1990-08-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0451042U true JPH0451042U (en) | 1992-04-30 |
Family
ID=31824416
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9001590U Pending JPH0451042U (en) | 1990-08-30 | 1990-08-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0451042U (en) |
-
1990
- 1990-08-30 JP JP9001590U patent/JPH0451042U/ja active Pending
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