JPH0451070B2 - - Google Patents

Info

Publication number
JPH0451070B2
JPH0451070B2 JP58174633A JP17463383A JPH0451070B2 JP H0451070 B2 JPH0451070 B2 JP H0451070B2 JP 58174633 A JP58174633 A JP 58174633A JP 17463383 A JP17463383 A JP 17463383A JP H0451070 B2 JPH0451070 B2 JP H0451070B2
Authority
JP
Japan
Prior art keywords
film
light
amorphous silicon
multilayer reflective
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58174633A
Other languages
Japanese (ja)
Other versions
JPS6066470A (en
Inventor
Fujio Okumura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP58174633A priority Critical patent/JPS6066470A/en
Publication of JPS6066470A publication Critical patent/JPS6066470A/en
Publication of JPH0451070B2 publication Critical patent/JPH0451070B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6729Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6732Bottom-gate only TFTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/674Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743Silicon
    • H10D30/6746Amorphous silicon

Landscapes

  • Liquid Crystal (AREA)

Description

【発明の詳細な説明】 本発明は薄膜トランジスタに関するものであ
る。薄膜トランジスタは液晶表示装置や密着型イ
メージセンサ等の大面積デバイスに使用される能
動素子であり、半導体膜としては硫化ガドミウ
ム,セレン化カドミウム,単結晶シリコン、多結
晶シリコン、非晶質シリコン等が使われている。
これらの半導体材料は程度の差はあるがいずれも
光導電体であり、薄膜トランジスタが光にさらさ
れる液晶表示装置等では遮光が必要である。この
遮光の方法としては従来は以下に述べる方法が取
られている。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to thin film transistors. Thin film transistors are active elements used in large-area devices such as liquid crystal displays and contact image sensors, and the semiconductor films used include cadmium sulfide, cadmium selenide, single crystal silicon, polycrystalline silicon, and amorphous silicon. It is being said.
All of these semiconductor materials are photoconductors to varying degrees, and light shielding is required in liquid crystal display devices and the like where thin film transistors are exposed to light. Conventionally, the method described below has been adopted as a method of blocking light.

第1図は遮光膜を金属とした従来素子の一例を
示している。図において1はガラス基板、2はゲ
ート電極、3はゲート絶縁膜、4はソース電極、
5はドレイン電極、6は半導体膜、7は半導体膜
と8の遮光用金属とを絶縁するための絶縁膜であ
る。この例では薄膜トランジスタのソース,ドレ
イン電極側へ入射してくる光を8の金属遮光膜で
阻止する構造になつている。たしかに金属の吸収
係数は大きく、数千オングストロームの膜厚で充
分な遮光能が得られるが、この方法には以下に述
べる欠点がある。
FIG. 1 shows an example of a conventional element in which the light-shielding film is made of metal. In the figure, 1 is a glass substrate, 2 is a gate electrode, 3 is a gate insulating film, 4 is a source electrode,
5 is a drain electrode, 6 is a semiconductor film, and 7 is an insulating film for insulating the semiconductor film and the light-shielding metal 8. In this example, the structure is such that light entering the source and drain electrodes of the thin film transistor is blocked by a metal light shielding film 8. It is true that metal has a large absorption coefficient, and a film thickness of several thousand angstroms can provide sufficient light-shielding ability, but this method has the following drawbacks.

第2図は第1図に示した薄膜トランジスタを液
晶表示装置に応用した場合の等価回路を示してい
る。図において9はドレイン電極、10はゲート
電極、11はソース電極、12は液晶の等価的な
容量、13はソース,ドレイン間容量である。該
ソース,ドレイン間容量は主に第1図における
4,5,8の金属と7の絶縁膜から構成されるも
のである。液晶表示装置においては第2図に示す
ようにドレインにパルスが加わるため液晶容量1
2とソース,ドレイン間容量13の分圧比に応じ
た電荷が液晶容量12に蓄積され、その画素の表
示コントラストを低下させる原因となる。薄膜ト
ランジスタには他に色々な構造がありそれに対す
る遮光膜の形成位置も様々であるが、いずれの場
合にも寄生容量は増加しコントラストは低下す
る。絶縁膜7を厚くすればこの影響を軽減するこ
とができるが、形成時間は増加し、基板を加熱す
る時間が長くなるため生じるアニール効果の増大
が素子に悪影響を与える。
FIG. 2 shows an equivalent circuit when the thin film transistor shown in FIG. 1 is applied to a liquid crystal display device. In the figure, 9 is a drain electrode, 10 is a gate electrode, 11 is a source electrode, 12 is an equivalent capacitance of the liquid crystal, and 13 is a capacitance between the source and the drain. The source-drain capacitance is mainly composed of metals 4, 5, and 8 and an insulating film 7 in FIG. In a liquid crystal display device, as shown in Figure 2, a pulse is applied to the drain, so the liquid crystal capacitance is 1.
2 and the source-drain capacitor 13 are accumulated in the liquid crystal capacitor 12, causing a decrease in the display contrast of the pixel. There are various other structures for thin film transistors, and the positions where the light shielding film is formed are also various, but in any case, the parasitic capacitance increases and the contrast decreases. This effect can be alleviated by increasing the thickness of the insulating film 7, but the formation time increases, and the increased annealing effect caused by the increased time to heat the substrate adversely affects the device.

次に遮光膜が非晶質半導体である場合の従来例
を第3図,第4図に示す。この場合半導体は非晶
質シリコン膜と限定されている。図において1
4,16は0.1%以上の不純物をドープした非晶
質シリコンからなる遮光膜、15は絶縁膜であ
る。この絶縁膜は非晶質シリコンに不純物をドー
プし吸収係数を増加させて遮光膜を増大させたも
のである。しかし実施例から分るように、不純物
をドーピングすると抵抗が低がり絶縁膜による分
離が必要である。このことは前記金属遮光膜の欠
点と同じ欠点があることを示している。またこの
ような膜でも吸収係数は可視光の範囲で103から
5×105cm-1程度であり、可視光全域にわたつて
透過光を入射光の0.01%とするのに約5μmの膜厚
が必要である。薄膜トランジスタの厚さが1μm
程度であることを考えるとこの値はかなり大き
い。
Next, FIGS. 3 and 4 show conventional examples in which the light shielding film is an amorphous semiconductor. In this case, the semiconductor is limited to an amorphous silicon film. In the figure 1
4 and 16 are light-shielding films made of amorphous silicon doped with impurities of 0.1% or more, and 15 is an insulating film. This insulating film is made by doping amorphous silicon with impurities to increase the absorption coefficient and thereby increase the light-shielding film. However, as can be seen from the examples, doping with impurities lowers the resistance and requires isolation by an insulating film. This indicates that the metal light shielding film has the same drawbacks as those of the metal light shielding film. In addition, even with such a film, the absorption coefficient is about 10 3 to 5 × 10 5 cm -1 in the visible light range, and it takes a film of about 5 μm to make the transmitted light 0.01% of the incident light over the entire visible light range. Thickness is necessary. Thin film transistor thickness is 1μm
This value is quite large considering that it is a small amount.

次に遮光膜としてアルゴンスパツタ法で形成し
た非晶質シリコンを用いた例と、それを逆スタガ
ード型の薄膜トランジスタに応用した例を第5
図、第6図に示す。図において14,16が遮光
膜である。この膜は非晶質シリコンにアルゴンを
ドープすることにより、その欠陥準位密度を大き
くし光吸収係数と抵抗率を増大させたものである
としている。しかしこの膜はスパツタ法で形成さ
れるため、例えば第6図に示した逆スタガード型
や第4図の逆コプレーナー型のように半導体膜と
遮光膜が直接接触する場合には界面がスパツタに
よつてダメージを受け、界面準位が増加し、オフ
リーク電流が大きくなるという欠点がある。これ
は半導体材料が非晶質シリコン以外のものである
場合やグロー放電法で形成された非晶質シリコン
である場合特に顕著である。
Next, we will discuss an example of using amorphous silicon formed by the argon sputtering method as a light-shielding film, and an example of applying it to an inverted staggered thin film transistor.
As shown in FIG. In the figure, 14 and 16 are light shielding films. This film is said to be made by doping amorphous silicon with argon to increase its defect level density and increase its light absorption coefficient and resistivity. However, since this film is formed by the sputtering method, when the semiconductor film and the light-shielding film are in direct contact, for example in the inverted staggered type shown in Figure 6 or the inverted coplanar type shown in Figure 4, the interface is formed by the sputtering method. This has the disadvantage that the interface level increases and off-leakage current increases. This is particularly noticeable when the semiconductor material is other than amorphous silicon or when it is amorphous silicon formed by a glow discharge method.

本発明の目的は上記従来構造の欠点を除去せし
め、寄生容量を増加させずしかも薄膜トランジス
タの特性を劣化させることのない遮光膜を備えた
薄膜トランジスタを提供することである。
An object of the present invention is to eliminate the drawbacks of the conventional structure described above and to provide a thin film transistor equipped with a light shielding film that does not increase parasitic capacitance or deteriorate the characteristics of the thin film transistor.

本発明によれば、絶縁基板と、該絶縁基板に設
けられたシリコン膜と、該シリコン膜のいずれか
一方の主面に所定の間隔をおいて設けられたソー
ス、ドレイン電極と、前記シリコン膜のいずれか
一方の主面にゲート絶縁膜を介して設けられたゲ
ート電極と、前記シリコン膜の少なくとも一方の
主面にゲート電極またはソース、ドレイン電極を
介して形成されるかあるいはゲート電極、ソー
ス、ドレイン電極がすべて前記主面の同じ側にあ
るときはその反対側の主面に形成される非晶質シ
リコン膜と絶縁膜を交互に積層した多層反射膜を
備えた薄膜トランジスタが得られる。
According to the present invention, an insulating substrate, a silicon film provided on the insulating substrate, source and drain electrodes provided at a predetermined interval on one of the main surfaces of the silicon film, and the silicon film a gate electrode provided on one main surface of the silicon film via a gate insulating film, and a gate electrode or a source or drain electrode provided on at least one main surface of the silicon film, or a gate electrode or a source When the drain electrodes are all on the same side of the main surface, a thin film transistor is obtained that includes a multilayer reflective film in which an amorphous silicon film and an insulating film are alternately laminated on the opposite main surface.

以下、本発明の薄膜トランジスタについて詳細
に説明する。
Hereinafter, the thin film transistor of the present invention will be explained in detail.

まず、本発明の中心をなす非晶質シリコンを使
つた絶縁性の多層反射膜について説明する。多層
反射膜自体については良く知られた技術である。
これは屈折率の異なる膜を交互に積層し、その屈
折率差による光の干渉を利用して反射増大膜とす
るものである。反射の中心波長は屈折率と膜厚に
よつて決まる。一般に、屈折率の差が大きい程薄
い膜で大きな反射率が得られる。多層反射膜に使
われる代表的な膜としては硫化亜鉛とフツ化マグ
ネシウム,酸化セリウムとフツ化マグネシウム,
二酸化硅素と二酸化チタニウムなどの組合せがあ
る。もちろんこれらの膜を本発明に適用すること
ができるが本発明では特に非晶質シリコンを半導
体膜とする薄膜トランジスタに適した多層反射膜
を用いる。非晶質シリコンに適した遮光膜の例と
しては、明導電率が10-7(Ωcm)-1以下の非晶質シ
リコン膜とSiO2やSiNx膜の組合せがある。SiO2
やSiNxは絶縁体であり、非晶質シリコンも条件
を選べば充分明導電率の低い膜を作ることができ
る。従つてこの多層反射膜は絶縁体であるとみな
してさしつかえない。この組合せによる多層反射
膜の特性を調べるために行つた実験を以下に示
す。第7図は実験に用いた多層反射膜の構造を示
している。図において17はガラス基板、18,
20,22,24は水素とSiF4のガス混合比
SiF4/H2が30,基板温度300℃,圧力0.1Torr
の条件でグロー放電法により形成したフツ素と水
素を含んだ非晶質シリコンで、膜厚はそれぞれ1
8が390Å,20が330Å,22が430Å,24が
5000Åである。19,21,23はSiH4,NH3
N2の混合比を3:4:60,基板温度300℃,圧力
0.1Torrでグロー放電法により形成したSiNx
で、膜厚はそれぞれ19が540Å,21が470Å,
23が610Åである。25は入射光、26は反射
光である。この場合それぞれの層の役割は24が
薄膜トランジスタの代りの下地であり、18,1
9の組が550nm,20,21の組が480nm,2
2,23の組が620nmの波長の光を中心に反射す
る反射増大膜である。屈折率は非晶質シリコンが
3.6,SiNxが2.53である。この多層反射膜の可視
域における反射率を第8図に示す。図から明らか
なように反射率は可視光全域にわたつてほぼ90%
以上となつており、膜厚が0.277μmと薄いにもか
かわらず良好な反射特性を示している。さらに、
この多層反射膜では非晶質シリコンが大きな吸収
係数を持つているため透過率がより減少するとい
う特長を持つている。図で点線で示したのが24
の非晶質シリコンに透過する光の割合を示したも
ので、非晶質シリコンの短波長での吸収係数が大
きいため500nm以下では1%以下の透過率となつ
ている。これよりこの多層反射膜に660nmを中心
波長とする反射増大膜を加えれば可視光全域にわ
たつて透過率を1%以下とすることが可能であ
る。このようにわずか0.μm以下の膜厚で充分な
遮光能を持つた絶縁性の多層反射膜が得れるわけ
である。ただし、寄生容量の増加をある程度許す
なら光導電性のよい非晶質シリコン膜を用いるこ
とも可能である。本実験より、室内光程度の照度
下での薄膜トランジスタにおいては、20,21
の480nmの反射膜は不要であることが分る。なぜ
ならば非晶質シリコンの短波長域での吸収係数は
極めて大きく、20,21の反射膜を除いても1
8,22の非晶質シリコンで短波長光が充分吸収
されるからである。また、該半導体膜を非晶質シ
リコンに限るならば長波長域の透過光が10%程度
あつても非晶質シリコン自体の吸収係数が小さい
ため問題とならない。もちろん入射光が強くなれ
ばそれだけ層数は必要である。
First, an insulating multilayer reflective film using amorphous silicon, which is the core of the present invention, will be explained. The multilayer reflective film itself is a well-known technology.
This is a method in which films with different refractive indexes are alternately laminated and light interference due to the difference in refractive index is used to create a reflection-enhancing film. The center wavelength of reflection is determined by the refractive index and film thickness. Generally, the greater the difference in refractive index, the greater the reflectance can be obtained with a thinner film. Typical films used for multilayer reflective films include zinc sulfide and magnesium fluoride, cerium oxide and magnesium fluoride,
There are combinations such as silicon dioxide and titanium dioxide. Of course, these films can be applied to the present invention, but the present invention particularly uses a multilayer reflective film suitable for thin film transistors using amorphous silicon as a semiconductor film. An example of a light-shielding film suitable for amorphous silicon is a combination of an amorphous silicon film with a bright conductivity of 10 -7 (Ωcm) -1 or less and a SiO 2 or SiN x film. SiO2
and SiN x are insulators, and amorphous silicon can also be used to form films with sufficiently low conductivity if conditions are chosen. Therefore, this multilayer reflective film can be regarded as an insulator. An experiment conducted to investigate the characteristics of a multilayer reflective film made of this combination is shown below. FIG. 7 shows the structure of the multilayer reflective film used in the experiment. In the figure, 17 is a glass substrate, 18,
20, 22, 24 are the gas mixture ratios of hydrogen and SiF 4
SiF 4 /H 2 is 30, substrate temperature is 300℃, pressure is 0.1Torr
Amorphous silicon containing fluorine and hydrogen was formed using the glow discharge method under the following conditions, each with a film thickness of 1.
8 is 390 Å, 20 is 330 Å, 22 is 430 Å, 24 is
It is 5000Å. 19, 21, 23 are SiH 4 , NH 3 ,
Mixing ratio of N2 : 3:4:60, substrate temperature: 300℃, pressure
The SiN x films were formed by the glow discharge method at 0.1 Torr, and the film thicknesses were 540 Å for 19, 470 Å for 21, and 470 Å for 21, respectively.
23 is 610 Å. 25 is incident light, and 26 is reflected light. In this case, the role of each layer is that 24 is a base instead of a thin film transistor, 18, 1
Group 9 is 550nm, Group 20, 21 is 480nm, 2
Groups 2 and 23 are reflection-enhancing films that mainly reflect light with a wavelength of 620 nm. The refractive index of amorphous silicon is
3.6, SiN x is 2.53. FIG. 8 shows the reflectance of this multilayer reflective film in the visible range. As is clear from the figure, the reflectance is approximately 90% over the entire visible light range.
Thus, despite the film thickness being as thin as 0.277 μm, it exhibits good reflection characteristics. moreover,
This multilayer reflective film has the feature that the transmittance is further reduced because amorphous silicon has a large absorption coefficient. The dotted line in the figure is 24
It shows the percentage of light that passes through amorphous silicon.Because amorphous silicon has a large absorption coefficient at short wavelengths, the transmittance is less than 1% below 500 nm. Therefore, by adding a reflection-enhancing film with a center wavelength of 660 nm to this multilayer reflective film, it is possible to reduce the transmittance to 1% or less over the entire visible light range. In this way, an insulating multilayer reflective film with sufficient light-shielding ability can be obtained with a film thickness of only 0.μm or less. However, if an increase in parasitic capacitance is allowed to some extent, it is also possible to use an amorphous silicon film with good photoconductivity. From this experiment, it was found that in a thin film transistor under illuminance comparable to indoor light, 20,21
It can be seen that the 480nm reflective film is not necessary. This is because the absorption coefficient of amorphous silicon in the short wavelength range is extremely large, and even excluding the reflective films 20 and 21, the absorption coefficient is 1.
This is because short wavelength light is sufficiently absorbed by amorphous silicon of No. 8 and No. 22. Furthermore, if the semiconductor film is limited to amorphous silicon, even if about 10% of the transmitted light in the long wavelength range is present, it will not be a problem because the absorption coefficient of amorphous silicon itself is small. Of course, the stronger the incident light, the more layers are required.

次に本発明の薄膜トランジスタのいくつかの実
施例を示す。第9図,第10図は前記非晶質シリ
コン膜とSiNx膜からなる絶縁性多層反射膜を遮
光に用いた、非晶質シリコンを半導体膜とする薄
膜トランジスタを示している。図において27は
ガラス基板、28,29,30はそれぞれMoか
らなるゲート,ソース,ドレイン電極、31はグ
ロー放電法により、基板温度300℃,圧力
0.3Torr,SiH4,NH3,N2の混合比2:1:9
で形成したSiNx膜、32は基板温度300℃,圧力
0.3Torr,でSiH4のグロー放電法により形成した
非晶質シリコン膜,33はガラス面から非晶質シ
リコン,SiNx,非晶質シリコン…という順に8
層重ね合せた絶縁性多層反射膜で、非晶質シリコ
ンは基板温度300℃,圧力0.1Torr,ガス混合比
SiF4/H2が30の条件でグロー放電法により形成
したもので、膜厚は順に390Å,330Å,430Å,
430Åである。またSiNxは基板温度300℃,圧力
0.1Torr,SiH4,NH3,N2の混合比3:4:60
でグロー放電法により形成したもので、膜厚は順
に540Å,470Å,610Å,610Åである。34は3
3と同様な絶縁性多層反射膜で表面から32の非
晶質シリコン膜に向つて、非晶質シリコン,
SiNx,非晶質シリコン…の順に積層したもので
ある。
Next, some embodiments of the thin film transistor of the present invention will be shown. FIGS. 9 and 10 show a thin film transistor using amorphous silicon as a semiconductor film and using an insulating multilayer reflective film made of the amorphous silicon film and SiN x film for light shielding. In the figure, 27 is a glass substrate, 28, 29, and 30 are gate, source, and drain electrodes made of Mo, respectively.
0.3 Torr, mixing ratio of SiH 4 , NH 3 , N 2 2:1:9
32 is a SiN x film formed at a substrate temperature of 300℃ and a pressure of
8 is an amorphous silicon film formed by glow discharge method of SiH 4 at 0.3 Torr, 33 is amorphous silicon, SiN x , amorphous silicon, etc. from the glass surface in this order.
It is an insulating multilayer reflective film made of stacked layers, and the amorphous silicon has a substrate temperature of 300℃, a pressure of 0.1Torr, and a gas mixture ratio.
It was formed by glow discharge method under the condition of SiF 4 /H 2 of 30, and the film thickness was 390 Å, 330 Å, 430 Å,
It is 430Å. In addition, SiN x has a substrate temperature of 300℃ and a pressure of
0.1 Torr, SiH 4 , NH 3 , N 2 mixing ratio 3:4:60
The film thicknesses are 540 Å, 470 Å, 610 Å, and 610 Å, respectively. 34 is 3
With an insulating multilayer reflective film similar to 3, amorphous silicon,
SiN x , amorphous silicon, etc. are laminated in this order.

この構造の薄膜トランジスタでは遮光能を持つ
た33,34の多層反射膜が絶縁体であるため寄
生容量は発生せず、しかもこの多層反射膜の膜厚
が約0.4μmと薄いため多層反射膜形成時の熱によ
る非晶質シリコン半導体膜の特性変化も起きにく
い。さらに、この多層反射膜はグロー放電法で形
成された膜であるためスパツタと比較してダメー
ジが少く、半導体面をあらすことがない。従つて
従来構造の欠点はすべて解決されている。
In a thin film transistor with this structure, the multilayer reflective films 33 and 34 are insulators and have a light shielding ability, so parasitic capacitance does not occur.Moreover, the thickness of the multilayer reflective film is as thin as approximately 0.4 μm, so when forming the multilayer reflective film, Characteristic changes in the amorphous silicon semiconductor film due to heat are also less likely to occur. Furthermore, since this multilayer reflective film is formed by a glow discharge method, it causes less damage than spatter and does not expose the semiconductor surface. All the drawbacks of the conventional structure are therefore solved.

なお、この例では半導体は非晶質シリコンであ
るが他の材料例えば多結晶シリコン、単結晶シリ
コンでも可能である。また、基板27がセラミツ
ク等の不透明体である場合には33の多層反射膜
ははぶくことができる。さらに付けくわえれば半
導体と接触しない方の遮光膜は従来方法の高抵抗
非晶質シリコン膜とすることも可能である。
In this example, the semiconductor is amorphous silicon, but other materials such as polycrystalline silicon or single crystal silicon may also be used. Furthermore, if the substrate 27 is an opaque material such as ceramic, the multilayer reflective film 33 can be peeled off. Additionally, the light-shielding film that does not come into contact with the semiconductor can be a conventional high-resistance amorphous silicon film.

以上の説明で明らかなように、本発明の薄膜ト
ランジスタは従来の薄膜トランジスタに比べ、寄
生容量の増加がなく安定でしかも光感度がないと
いう優れた特長を持つている。
As is clear from the above description, the thin film transistor of the present invention has excellent features compared to conventional thin film transistors, such as no increase in parasitic capacitance, stability, and no photosensitivity.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の金属遮光膜を用いた薄膜トラン
ジスタの例,第2図は第1図の薄膜トランジスタ
を液晶表示素子に用いた場合の等価回路,第3
図,第4図は従来の半導体遮光膜を用いた薄膜ト
ランジスタの例,第5図,第6図は特にスパツタ
によつて高抵抗化した非晶質シリコンを遮光膜と
した薄膜トランジスタの例,第7図は本発明の薄
膜トランジスタに用いる絶縁性多層反射膜の特性
を調べるために形成した多層反射膜、第8図は第
7図の多層反射膜の反射及び透過特性,第9図,
第10図は本発明の薄膜トランジスタを示してい
る。 1…ガラス基板、2,10…ゲート電極、3…
ゲート絶縁膜、4,11…ソース電極、5,9…
ドレイン電極、6…半導体膜、7…絶縁膜、8…
金属遮光膜、12…液晶容量、13…ソース,ド
レイン間容量、14,16…半導体遮光膜、15
…絶縁膜、17…ガラス基板、18,20,2
2,24…非晶質シリコン膜、19,21,23
…SiNx膜、25…入射光、26…反射光、27
…ガラス基板、28…ゲート電極、29…ソース
電極、30…ドレイン電極、31…SiNx膜、3
2…非晶質シリコン膜、33,34…絶縁性多層
反射膜。
Figure 1 is an example of a thin film transistor using a conventional metal light-shielding film, Figure 2 is an equivalent circuit when the thin film transistor in Figure 1 is used in a liquid crystal display element, and Figure 3 is an example of a thin film transistor using a conventional metal light-shielding film.
4 shows an example of a thin film transistor using a conventional semiconductor light-shielding film, FIGS. 5 and 6 show an example of a thin-film transistor using a light-shielding film made of amorphous silicon whose resistance has been particularly high by sputtering, and FIG. The figure shows a multilayer reflective film formed to investigate the characteristics of the insulating multilayer reflective film used in the thin film transistor of the present invention, Figure 8 shows the reflection and transmission characteristics of the multilayer reflective film shown in Figure 7, Figure 9,
FIG. 10 shows a thin film transistor of the present invention. 1...Glass substrate, 2,10...Gate electrode, 3...
Gate insulating film, 4, 11... Source electrode, 5, 9...
Drain electrode, 6... semiconductor film, 7... insulating film, 8...
Metal light-shielding film, 12... Liquid crystal capacitance, 13... Source-drain capacitance, 14, 16... Semiconductor light-shielding film, 15
...Insulating film, 17...Glass substrate, 18, 20, 2
2, 24...Amorphous silicon film, 19, 21, 23
...SiN x film, 25... Incident light, 26... Reflected light, 27
...Glass substrate, 28...Gate electrode, 29...Source electrode, 30...Drain electrode, 31...SiN x film, 3
2...Amorphous silicon film, 33, 34...Insulating multilayer reflective film.

Claims (1)

【特許請求の範囲】[Claims] 1 絶縁基板と、該絶縁基板に設けられたシリコ
ン膜と、該シリコン膜のいずれか一方の主面に所
定の間隔をおいて設けられたソース、ドレイン電
極と、前記シリコン膜のいずれか一方の主面にゲ
ート絶縁膜を介して設けられたゲート電極と、前
記シリコン膜の少なくとも一方の主面にゲート電
極またはソース、ドレイン電極を介して形成され
るかあるいはゲート電極、ソース、ドレイン電極
がすべて前記主面の同じ側にあるときはその反対
側の主面に形成される非晶質シリコン膜と絶縁膜
を交互に積層した多層反射膜を備えた薄膜トラン
ジスタ。
1. An insulating substrate, a silicon film provided on the insulating substrate, source and drain electrodes provided at a predetermined interval on the main surface of one of the silicon films, and a silicon film provided on one of the silicon films. A gate electrode is provided on the main surface via a gate insulating film, and a gate electrode or source and drain electrodes are provided on at least one main surface of the silicon film, or all of the gate electrode, source and drain electrodes are provided on the main surface of the silicon film. A thin film transistor comprising a multilayer reflective film formed by alternately laminating an amorphous silicon film and an insulating film formed on the opposite main surface when they are on the same side of the main surface.
JP58174633A 1983-09-21 1983-09-21 Thin film transistor Granted JPS6066470A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58174633A JPS6066470A (en) 1983-09-21 1983-09-21 Thin film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58174633A JPS6066470A (en) 1983-09-21 1983-09-21 Thin film transistor

Publications (2)

Publication Number Publication Date
JPS6066470A JPS6066470A (en) 1985-04-16
JPH0451070B2 true JPH0451070B2 (en) 1992-08-18

Family

ID=15982001

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58174633A Granted JPS6066470A (en) 1983-09-21 1983-09-21 Thin film transistor

Country Status (1)

Country Link
JP (1) JPS6066470A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07112053B2 (en) * 1990-04-13 1995-11-29 富士ゼロックス株式会社 Thin film switching element array
JPH08190106A (en) * 1995-01-10 1996-07-23 Victor Co Of Japan Ltd Active matrix device and driving method thereof
JP2016048706A (en) * 2014-08-27 2016-04-07 三菱電機株式会社 Array substrate and manufacturing method thereof
KR20220106156A (en) * 2019-11-27 2022-07-28 코닝 인코포레이티드 Glass wafers for semiconductor device manufacturing

Also Published As

Publication number Publication date
JPS6066470A (en) 1985-04-16

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