JPH0451087B2 - - Google Patents
Info
- Publication number
- JPH0451087B2 JPH0451087B2 JP59126372A JP12637284A JPH0451087B2 JP H0451087 B2 JPH0451087 B2 JP H0451087B2 JP 59126372 A JP59126372 A JP 59126372A JP 12637284 A JP12637284 A JP 12637284A JP H0451087 B2 JPH0451087 B2 JP H0451087B2
- Authority
- JP
- Japan
- Prior art keywords
- present
- collector
- differential amplifier
- vout
- vcc
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
- H03F3/45197—Pl types
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/4508—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using bipolar transistors as the active amplifying circuit
- H03F3/45098—PI types
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
- Amplifiers (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は差動増幅器に関し、特に動作電圧の拡
大を図つた差動ダイオードリミツト回路に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a differential amplifier, and more particularly to a differential diode limit circuit that increases the operating voltage.
従来の回路例を第３図に示す。この差動増幅器
は、トランジスタQ1，Q2のベースに入力される
入力電圧vioが所定の入力レベルを越えるとQ1，
Q2のコレクタ出力間に設けられたダイオードQ3，
Q4によつて出力の振幅が制限されるような動作
を行う。この場合、この回路の交流利得Avは近
似的に次の関係式で与えられる。即ち、
Av＝vput／vio≒2Rc／2re＋RE …
ここで、reはQ1，Q2のエミツタ抵抗、REはQ1，
Q2のエミツタ間に接続される抵抗、RCはQ1，Q2
のコレクタと電源Vccとの間に接続される抵抗で
ある。ここで、エミツタ抵抗reはエミツタ電流を
I1（mA）とするとre≒26／I1（Ω）と与えられる
ものとする。
An example of a conventional circuit is shown in FIG. In this differential amplifier, when the input voltage v io input to the bases of transistors Q 1 and Q 2 exceeds a predetermined input level, Q 1 ,
Diode Q 3 installed between the collector output of Q 2 ,
The output amplitude is limited by Q4 . In this case, the AC gain Av of this circuit is approximately given by the following relational expression. That is, Av=v put /v io ≒2R c /2r e +R E ... Here, r e is the emitter resistance of Q 1 and Q 2 , and R E is Q 1 ,
The resistor, R C , connected between the emitters of Q 2 is Q 1 , Q 2
This is a resistor connected between the collector of and the power supply Vcc. Here, the emitter resistance r e is the emitter current.
If I 1 (mA), r e ≒26/I 1 (Ω) is given.
一方、直流的な電位はこの回路の平衡状態即
ち、vio＝０において次の関係式で表わせる。即
ち、
Vout（DC）＝Vcc−I1Rc …
また、出力振幅はダイオードQ3，Q4の順方向
電圧Vdにより制限されるのでQ1，Q2のコレクタ
電圧はVout（DC）±Vd／２の範囲で動作する。 On the other hand, the DC potential can be expressed by the following relational expression in the equilibrium state of this circuit, that is, v io =0. That is, Vout (DC) = Vcc - I 1 Rc ... Also, since the output amplitude is limited by the forward voltage Vd of diodes Q 3 and Q 4 , the collector voltage of Q 1 and Q 2 is Vout (DC) ± Vd / It operates within the range of 2.
交流利得Avを大にするためには式からも明
らかなようにREを零にするか又はRCを出来るだ
け大きくする必要がある。しかしながら、Q1，
Q2が安定に動作するためには各々のトランジス
タが飽和しない領域で使用されることが必要で、
このためRCの値には制限があり、さらに式か
らも明らかなようにRCを大にするとVout（DC）
が低下することになり動作電圧の下限値に制約が
生ずる問題がある。
In order to increase the AC gain Av, as is clear from the equation, it is necessary to reduce R E to zero or to increase R C as much as possible. However, Q 1 ,
In order for Q 2 to operate stably, each transistor must be used in a region where it does not saturate.
For this reason, there is a limit to the value of R C , and as is clear from the equation, if R C is increased, Vout(DC)
There is a problem in that the lower limit of the operating voltage is restricted.
本発明は上記の問題点を解消した差動増幅器を
提供することにあり、その手段は出力にダイオー
ドリミツト手段を設けた差動増幅器において、一
方のトランジスタのコレクタと電源間、および他
方のトランジスタのコレクタと電源間に各々定電
流源を設けたことを特徴とする差動増幅器、によ
り達成される。
An object of the present invention is to provide a differential amplifier that solves the above problems, and the present invention provides a differential amplifier in which a diode limiting means is provided at the output. This is achieved by a differential amplifier characterized in that a constant current source is provided between the collector and the power supply.
第１図は本発明による一実施例としての差動増
器の回路を示す。第１図において、第３図と同一
構成要素には同一番号が付与されている。図から
明らかなように、抵抗RCの各々に並列に各々の
コレクタと電源との間に定電流源が設けられ定電
流源I2を発生させる。
FIG. 1 shows a differential amplifier circuit as an embodiment of the present invention. In FIG. 1, the same components as in FIG. 3 are given the same numbers. As is clear from the figure, a constant current source is provided in parallel with each of the resistors R C between each collector and the power supply to generate a constant current source I 2 .
この場合、定電流I2の条件として、
０＜I1−I2＜Vd／2RC …
に設定する。このように設定するとvputの振幅を
確保した状態において次の関係式が得られる。即
ち、
Vout（DC）＝Vcc（I1−I2）RC …
式と比較して明らかなように（I1−I2）の値
を上記の式を満足する範囲内で出来るだけ小さ
くすればVout（DC）を大にすることが出来る。
即ち、トランジスタQ1，Q2のコレクタ電位を
Vcc側に持ち上げることが出来る。従つて、従来
例と同一利得、同一エミツタ電流においてVcc作
動電圧が低下でき使用条件が拡大が可能となる。 In this case, the constant current I2 condition is set to 0< I1 - I2 <Vd/ 2RC ... With this setting, the following relational expression can be obtained while ensuring the amplitude of v put . In other words, Vout (DC) = Vcc (I 1 − I 2 ) R C … As is clear from the comparison with the formula, the value of (I 1 − I 2 ) should be made as small as possible within the range that satisfies the above formula. In this case, Vout (DC) can be increased.
In other words, the collector potential of transistors Q 1 and Q 2 is
It can be lifted to the Vcc side. Therefore, with the same gain and the same emitter current as in the conventional example, the Vcc operating voltage can be lowered and the usage conditions can be expanded.
第２図は本発明と従来の動作範囲を比較した図
である。点線のVout（DC）は式によるレベル、
一点鎖線のVout（DC）は式によるレベルであ
る。図に示すように入力直流電位Vin（DC）に対
して従来はVout（DC）のマージンがＡ（ｖ）であ
つたものが本発明によりマージンがＢ（ｖ）と広
くすることが出来る。曲線ａは従来のI2が無い場
合でありｂは本発明のI2が有る場合である。仮り
にダイオードQ3，Q4が無い場合には曲線ｂは
VccレベルにてクリツプしてしまうためI2によつ
てマージンを広げても有効ではない。従来の出力
vput1と本発明の出力vput2から明らかなようにダイ
オードQ3，Q4の作用によつて本発明は顕著にそ
の効果をあらわしている。 FIG. 2 is a diagram comparing the operating ranges of the present invention and the conventional method. The dotted line Vout (DC) is the level according to the formula,
Vout (DC) indicated by the dashed-dotted line is the level according to the formula. As shown in the figure, conventionally the margin of Vout (DC) with respect to the input DC potential Vin (DC) was A(v), but according to the present invention, the margin can be widened to B(v). Curve a is the case without the conventional I 2 and curve b is the case with the I 2 of the present invention. If diodes Q 3 and Q 4 were not present, curve b would be
Since it clips at the Vcc level, increasing the margin with I2 is not effective. conventional output
As is clear from v put1 and the output v put2 of the present invention, the effects of the present invention are significantly exhibited by the effects of the diodes Q 3 and Q 4 .
以上説明したように本発明によれば、電源と各
各のコレクタ間に定電流源を挿入することによつ
てVcc作動電圧を低下する、利得を大にする等々
使用条件を広げることができる。
As explained above, according to the present invention, by inserting a constant current source between the power supply and each collector, the usage conditions can be expanded, such as lowering the Vcc operating voltage and increasing the gain.
第１図は本発明による一実施例としての差動増
幅回路、第２図は本発明と従来の動作範囲を比較
する図、および第３図は従来の差動増幅回路であ
る。
（符号の説明）、Q1，Q2……トランジスタ、
Q3，Q4……ダイオード、I1，I2……定電流。
FIG. 1 shows a differential amplifier circuit as an embodiment of the present invention, FIG. 2 shows a comparison between the operating ranges of the present invention and a conventional one, and FIG. 3 shows a conventional differential amplifier circuit. (Explanation of symbols), Q 1 , Q 2 ...transistor,
Q 3 , Q 4 ...diode, I 1 , I 2 ... constant current.
Claims (1)
増幅器において、一方のトランジスタのコレクタ
と電源間、および他方のトランジスタのコレクタ
と電源間に各々定電流源を設けたことを特徴とす
る差動増幅器。1. A differential amplifier having diode limiting means at its output, characterized in that a constant current source is provided between the collector of one transistor and the power supply, and between the collector of the other transistor and the power supply.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59126372A JPS616907A (en) | 1984-06-21 | 1984-06-21 | Differential amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59126372A JPS616907A (en) | 1984-06-21 | 1984-06-21 | Differential amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS616907A JPS616907A (en) | 1986-01-13 |
| JPH0451087B2 true JPH0451087B2 (en) | 1992-08-18 |
Family
ID=14933540
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59126372A Granted JPS616907A (en) | 1984-06-21 | 1984-06-21 | Differential amplifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS616907A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04245708A (en) * | 1991-01-31 | 1992-09-02 | Nec Corp | Differential circuit |
-
1984
- 1984-06-21 JP JP59126372A patent/JPS616907A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS616907A (en) | 1986-01-13 |
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