JPH0451094A - display control device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a display control device for a display device such as a CRT, and particularly to a display control device that improves memory access using a character refresh method for obtaining display data.

[Prior Art] Conventionally, CRT controllers (CRT display control devices) for CRTs used in word processors, personal computers, etc. often use a character refresh method for memory access, and their circuit configuration is generally as shown in FIG. It has become. In this figure, the CRT controller 2 controlled by the CPUI is connected to the CRT (
It outputs l-sync (horizontal synchronization signal) and V-sync (vertical synchronization signal) synchronization signals to the video RAM (hereinafter referred to as V
(referred to as RAM) 3, ATRIBtlTERAM (referred to as
Attribute RAM (hereinafter referred to as ATRI RAM) 4 address is output. Data in the VRAM 3 is address-converted by a character generator RAM (hereinafter referred to as CG RAM) 5. The data in the CG RAM 5 is sent to the video control circuit 6 for image processing based on the attribute data of the character data in the ATRI RAM 4. The parallel 8-bit data outputted from the video control circuit 6 is converted into serial data by a P-3 (parallel-serial) conversion circuit 7, and is outputted to a CRT (not shown).

[Problems to be Solved by the Invention] However, in the conventional device as described above, in order to obtain 16 bits of information for one character, a VRAM is required.
There was a restriction that it had to have 3 and ATRI RAM 4 (7) 2 image memos. For example, for a CRT model with a resolution of 640 dots x 350 dots, one character box (one character) has a dot configuration of 8 dots x 14 dots.
In the case of ot, the number of characters required for one screen is
It will be 2000. Therefore, if the memory is only for one screen, a 2 Kbyte (kilobyte) image memory is sufficient for both the VRAM 3 and the ATRI RAM 4. On the other hand, the integration and speed of memory is currently progressing, and while 8 Kbyte and 32 Kbyte RAM can be easily obtained at a low price, it is difficult to obtain a RAM with a very small capacity. Recently, it has become even more difficult.

In view of the above-mentioned points, an object of the present invention is to
It is an object of the present invention to provide a display control device that can implement a RAM with a single RAM chip, thereby reducing costs by reducing the number of memories.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a display control device for a display device that performs memory access using a character refresh method.
m-bit latch circuits and a plurality of n m-bit output ports, and by continuously reading the same memory a plurality of n times through the latch circuits and the output ports,
It is characterized in that information in one character is obtained by a plurality of n times m bits.

[Function] In the present invention, for example, a 2×8 bi
t latch circuit and 2 x 8 bit output port, and instead of conventionally outputting addresses for VRAM and ATRI RAM in one go, we changed the address output for VRAM and ATRI RAM in two times. and ATRI RAM
functions can be realized by one RAM chip. Therefore, in the present invention, when performing memory access using the character refresh method, the same high-speed 8-bit
By reading the memory multiple times in succession, it is possible to obtain multiple 8 bits of information for one character, making it possible to perform more advanced image processing.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

■Natsukami Rakugari Figure 1 shows the circuit configuration of a display control device according to an embodiment of the present invention. In this figure, 1 is a CPU, 2 is a CRT controller, 3 is a VRAM, and 5 is a CGRAM.

6 is a video control circuit, and 7 is a P-8 conversion circuit. Next, the internal configuration of the CRT controller 2 will be explained. 8 is a timing control logic circuit that adjusts the count timing of the address counter inside the CRT controller 2 and generates Hsync and Vsync to the CRT. 9 is an address counter that generates an address to VRAM3, IO is an output buffer connected to the address bus of VRAM3, and 11 is a VRAM
This is the output data path from 3. 12 and 13 are 8-bit latch circuits that latch data in VRAM 3, 14 is an 8-bit output port that outputs data latched in one latch circuit 12, and 15 is an 8-bit output port that outputs data latched in the other latch circuit 13. An 8-bit output port outputs , and 16 is an inverter circuit that inverts the clock from the address counter 9 .

In the above 2 configuration, the clock C output from the timing control logic circuit 8 to the address counter 9
It is assumed that LK has a counting speed twice that of the conventional example described above. The address value counted by address counter 9 is sent to VR via output buffer lO.
AM3 and the lowest address bus AO is
At “0°”, VR is sent to the 8-bit latch circuit 12.
AM 3 data is stored. On the other hand, when the lowest address bus AO is "■", the data in the VRAM 3 is stored in the 8-bit latch circuit 13 by the inverter circuit 16.

The data stored in each latch circuit 12.13 is outputted to the address of CG RAM 5 through the 8-bit output port 14.15, as in the conventional example, and the other 8-bit data is outputted to the address of CG RAM 5. is CG RA
The output data of M5 is directly output to the video control circuit 6 as attribute data for image processing.

In this way, in this embodiment, the pair of latch circuits 12 and 13
By reading VRAM3 twice through
Since the image data of IT can be obtained from the two output ports 14 and 15, the part that was conventionally composed of two VRAM and ATRT RAM (see Figure 2) can be combined into one VRAM.
This can be achieved with 3. Therefore, according to this embodiment, cost reduction can be achieved by reducing the number of memories.

■Star λ] [4 Fear Figure 3 shows the circuit configuration of a display control device according to another embodiment of the present invention. In the first embodiment of the present invention shown in FIG. 1 described above, 1
6-bit information was obtained from one 8-bit RAM 3, but in the second embodiment, 32-bit information is obtained by reading the RAM 3 four times. That is, in this embodiment, when attempting to obtain 32-bit information by reading the RAM 3 four times, the address counter 9
2 bits of the address counter value on the output bus of
The clock signal CLK, which is divided into four parts by the decoder circuit 16 that decodes it into bits, is divided into four parts as shown by 17 to 20.
connected to each of the two 8-bit latch circuits, and
These four latch circuits 17 are
~2o, the data in VRAM 3 is sequentially latched. The latch data of each latch circuit 17 to 2o is outputted from four 8-bit output ports 21 to 24, and the 8-bit data outputted from one output port 21 is stored in the CG RAM as in the conventional example.
5, and the other output ports 22-2
CG R for 24 bit data output from 4
The data is directly input to the video control circuit 6 as attribute data of the output data of the AM5.

In this way, in this embodiment, four latch circuits 17 to 2
By reading the VRAM 3 four times through 0, 32 bits of information can be obtained from the output ports 21 to 24.

[Effects of the Invention] As explained above, according to the present invention, in a character refresh type display control device, conventionally, two
By reading the VRAM twice or more times, the image data of 16 bits or more can be obtained from the part that used to consist of two Kbytes of VRAM and ATRI RAM. This can be realized using VRAM, and as a result, costs can be reduced by reducing the number of memories. Also,
Conventionally, attribute data for characters is 8 bits.
However, according to the present invention, the gradation display of the two display devices can be made more multi-level, inversion, blinking, underline, etc.
By specifying display fonts, etc., it is possible to easily have attribute data of 16 bits, 32 bits, etc. in order to perform many types of image processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the circuit configuration of a display control device according to a first embodiment of the present invention, FIG. 2 is a block diagram showing a circuit configuration of a conventional display control device, and FIG. FIG. 2 is a block diagram showing a circuit configuration of a display control device according to an embodiment. 1... CPU, 2... CRT controller 3... VRAM 4... ATRIBUTE RAM, 5... CGRAM, 6... Video control circuit, 7... p-s conversion circuit, 8. ...Timing control logic 9...Address counter, 1O...Output buffer 11...Data bus, 12, 13...8 bit latch circuit, 14, 15...
...8 bit output port, 16...decoder circuit, 17-20...8-bit latch circuit, 21-24...
・8 bit output port. circuit,

Claims (1)

[Claims] 1) In a display control device for a display device that performs memory access using a character refresh method, a plurality of n m-bit latch circuits and a plurality of n m-bit output ports are provided for one m-bit memory. A display control device comprising: a display control device characterized in that information in one character is obtained by a plurality of n times m bits by successively reading the same memory a plurality of n times through the latch circuit and the output port.