JPH0451096B2 - - Google Patents

Description

[Detailed description of the invention]

INDUSTRIAL APPLICATION FIELD The present invention relates to a three-value output circuit capable of selectively obtaining high level, low level and intermediate level outputs. Configuration of conventional example and its problems As shown in Fig. 1, the conventional three-level output circuit uses the midpoint of two cascaded MOS transistors as an output terminal, and one MOS transistor _T1 receives a pulse signal _CL1 . , a pulse signal CL ₂ is applied to the other MOS transistor T ₂ , and corresponding to each pulse signal, high level and low level outputs are obtained at the output terminal V ₀ , and the intermediate level is output from both transistors T ₁ and T ₂ are made conductive, and an intermediate potential determined by those resistances appears at the output terminal _V0 . In the circuit shown in Figure 1, when the load output currents I ₁ and I ₂ flowing through the respective output transistors T ₁ and T ₂ change in the intermediate level output state, the intermediate level potential changes depending on the current value. There are some difficulties. Moreover, in order to suppress this change to a small value, the load output currents I ₁ and I ₂ for both transistors T ₁ and T ₂ must be
Since the circuit must be configured to generate a considerably larger through-current than the previous one, an increase in power consumption was unavoidable. Furthermore, in order to provide sufficient noise margin, it is necessary to set the load output currents I ₁ and I ₂ themselves to a large value, which also leads to an increase in power consumption. Purpose of the Invention The present invention solves the problems of the conventional device as described above. In particular, in the intermediate level output state, the output level does not fluctuate, the load output current is sufficiently large, and the noise margin is high. In addition, the present invention provides a high-performance three-value output circuit with low power consumption. Configuration of the Invention To summarize, the present invention includes a first output transistor whose output terminal is set to a high level by a first control signal, and a second output transistor whose output terminal is set to a low level by a second control signal. and,
It is equipped with a CMOS operational amplifier that sets the output terminal to an intermediate level according to the reference input signal.
This three-value output circuit has a configuration in which a pair of output MOS transistors of a CMOS operational amplifier are connected with switching MOS transistors of the same shape, respectively, and both of the switching MOS transistors are selectively driven. According to this circuit configuration, the intermediate level output state is selected based only on the operating state of the CMOS operational amplifier with both the first and second output transistors cut off, and a stable and low power consumption operating state is achieved. . DESCRIPTION OF THE EMBODIMENT FIG. 2 is a circuit diagram of an embodiment of the present invention. In this circuit diagram, the circuit component G surrounded by the dotted line is a normal
It is a CMOS operational amplifier circuit, _Q1 to _Q7 are P-channel MOS transistors, and _Q8 to _Q14 are N-channel MOS transistors.
MOS transistor, C ₀ is a capacitor. In this example circuit, MOS transistors T ₃ and T ₄ of the same type are connected in cascade to a pair of output transistors Q ₇ and Q ₈ of this CMOS operational amplifier circuit, respectively, and _a high It includes a first output P-channel MOS transistor _T5 that sets the level and a second output N-channel MOS transistor _T6 that sets the low level. A pair of input terminals of a CMOS operational amplifier circuit are V _A and V _B , one input terminal V _A is given a reference signal V _R , and the other input terminal V _B is an output terminal.
Connected to Vo. In this configuration, the control signals CL ₁ to _{CL 4} are pulse signals, and control the output states of high level, intermediate level, and low level. Furthermore, I ₃ and I ₄ indicate output currents at intermediate level output. The operation of the circuit configuration in FIG. 2 will be explained. Table 1 is
The signal states of the control signals CL ₃ to _{CL 6} at each output level are shown in association with the operating states of the transistors T ₃ to _{T 6.} In the table, H indicates the high level value of the control signal, and L indicates the same low level. indicates the state of the value,
ON represents conduction and OFF represents disconnection.

[Table] As shown in Table 1, in order to set the output terminal V ₀ to a high level, the transistor T ₅ is turned on and the other transistors T ₃ , T ₄ and T ₆ are turned off. Further, in order to set the output terminal V ₀ to a low level, the transistor T ₆ is turned on, and the other transistors T ₃ , T ₄ , and T ₅ are turned off. Furthermore, in order to bring the output terminal V ₀ to an intermediate level, transistors T ₃ and T ₄ are turned on and transistors T ₅ and T ₆ are turned off. FIG. 3 is a schematic diagram of the CMOS operational amplifier circuit shown in FIG. 2, and is shown corresponding to the operating state at the time of intermediate level output. In other words, this operational amplifier circuit configuration has a negative feedback circuit configuration, and the output level is kept at the same level as the reference signal V _R regardless of the output currents I ₄ and I ₄ , so the intermediate level does not change. There's nothing to do. In addition, in order to increase the noise margin in the operational amplifier circuit configuration, by changing the dimensions of the pair of output transistors Q ₇ and Q ₈ , the maximum values of the output currents I ₃ and I ₄ can be freely set, and the can do. Now, in the circuit configuration shown in Figure 2, when I ₃ = I ₄ = 0, that is, the load output current is zero, the transistor
The through current flowing through T ₃ , Q ₇ , Q ₈ and T ₄ is at its maximum, but even then, the configuration is such that no through current flows that is large compared to the maximum output current. On the other hand, at high level and low level,
By increasing the dimensions of the transistors T ₅ and T ₆ in FIG _. 2, the desired output current can be freely set.
The current through T ₆ is almost equal to zero. As described above, according to the circuit of this embodiment,
By using a CMOS operational amplifier circuit configuration, it is possible to realize a three-value output circuit with low power consumption and high noise margin. FIG. 4 schematically shows a circuit configuration in which the intermediate level can be arbitrarily set by making the input reference signal variable. That is, in the device shown in FIG. 4, the circuit of the embodiment shown in _FIG . Accordingly, it is possible to selectively set the output voltage _V0 , and in addition to the high level and low level, a multi-level output level can be selectively set as an intermediate level. Effects of the Invention According to the present invention, a CMOS operational amplifier circuit is used to set an intermediate level output in addition to an output transistor that can selectively set high-level and low-level outputs, and a By creating a circuit configuration that can limit the current, performance with a constant intermediate output level, low power consumption, and high noise tolerance is achieved, and its practical effects are truly great.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional example circuit, Fig. 2 is a circuit block diagram of an embodiment of the present invention, Fig. 3 is a schematic diagram of a CMOS operational amplifier circuit used in the circuit of the embodiment of the present invention, and Fig. 4
The figure is a circuit configuration diagram of an applied example for expanding the functionality of the present invention. T ₁ , T ₂ ...MOS transistor, T ₃ , T ₅ ...
P channel MOS transistor, _T4 , _T6 ...N channel MOS transistor, _Q1 to _Q7 ...P channel MOS transistor, _Q8 to _Q14 ...N channel
MOS transistor, C ₀ ... Capacitor, V _A , V _B
...Input terminal, V ₀ ...Output terminal, G...CMOS
Operational amplifier circuit, H... (Example) ternary output circuit block, N... Voltage divider.

Claims (1)

[Claims] 1 A first output transistor whose output terminal is set to a high level by a first control signal, a second output transistor whose output terminal is set to a low level by a second control signal, and a second output transistor whose output terminal is set to a low level by a reference input signal. A ternary output having a configuration in which a pair of output MOS transistors of the CMOS operational amplifier are connected in series with switching MOS transistors of the same shape, and both of the switching MOS transistors are selectively driven. circuit.