JPH0451563A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0451563A JPH0451563A JP2161003A JP16100390A JPH0451563A JP H0451563 A JPH0451563 A JP H0451563A JP 2161003 A JP2161003 A JP 2161003A JP 16100390 A JP16100390 A JP 16100390A JP H0451563 A JPH0451563 A JP H0451563A
- Authority
- JP
- Japan
- Prior art keywords
- parts
- resistance
- fuse
- low
- wiring metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 5
- 229910052751 metal Inorganic materials 0.000 claims abstract description 23
- 239000002184 metal Substances 0.000 claims abstract description 23
- 230000001154 acute effect Effects 0.000 claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 17
- 238000000034 method Methods 0.000 abstract description 14
- 230000005684 electric field Effects 0.000 abstract description 4
- 229920005591 polysilicon Polymers 0.000 abstract description 3
- 238000007664 blowing Methods 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路のヒユーズ回路に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a fuse circuit for a semiconductor integrated circuit.
半導体集積回路(以下工Cと称す。)においてICの外
部より何らかの操作を行うことによって工Cの特性や機
能を変更することがあった。たとえばプログラマブル・
ロジック・デバイスやFROMは書き込み操作によりユ
ーザー自身の思いのままの機能を達成することができた
。また、アナログエCの特性を合わせ込む場合にもその
工C特有の操作により特性を合わせ込むことができるも
のがある。このように工Cができあがった後に調整、あ
るいは機能の変更を行う場合、従来上な技術としてはF
AMO8やヒユーズがあった。ヒユーズとしては従来の
バイポーラP R−OMやプログラマブル・ロジック・
デバイスでは昇華のしやすい金属−N i Or 、
T i W 、 P t S i等を用いている。第3
図に代表的なヒユーズ回路を示す。こコ”’Q 40は
AL配線、41はpOLY Siヒz−ズで42はコ
ンタクトである。4oのAL配線の両端に高電圧を印加
すると41のPoLY 81ヒユーズに大電流が流れヒ
ユーズは溶断する。In a semiconductor integrated circuit (hereinafter referred to as IC), the characteristics and functions of IC may be changed by performing some kind of operation from outside the IC. For example, programmable
Logic devices and FROMs allow users to achieve desired functionality through write operations. Furthermore, when matching the characteristics of an analogue C, there are some that allow the characteristics to be matched by operations specific to the analogue C. In this way, when adjusting or changing the function after the construction C is completed, the conventional technology is
There was AMO8 and Hughes. Fuses include conventional bipolar PR-OM and programmable logic.
In devices, metals that sublimate easily -N i Or;
T i W, P t S i, etc. are used. Third
The figure shows a typical fuse circuit. Here''Q 40 is the AL wiring, 41 is the pOLY Si fuse, and 42 is the contact. When a high voltage is applied to both ends of the 4o AL wiring, a large current flows through the PoLY 81 fuse in 41, and the fuse melts. do.
この従来のヒユーズは最も一般的なものであるがヒユー
ズの材質としては前述した様に昇華しやすい金属として
工Cの標準プロセスには無い工程が必要となる場合、ま
たは標準プロセス工程内での金属(POLY si)
を使5場合の二通りが考えられる。しかし、ここで特殊
な金属を用いる場合はプロセスの工程が増加しウエファ
コストカアージブしてほんの数ビットのヒユーズについ
ては非常に不向きである。またC!MO8のIO等にお
けるヒユーズでPOLY Siを用いる場合aVDで
覆われている場合にはPOLY Siは溶断しに((
通常はヒユーズ部分のPOLY Siの上はOVDを
オーブンとしておく。この場合ウェファ検査でヒーーズ
を切る場合には問題ないが、モールド実装後はモールド
材がヒユーズ部のaVDオーブンをふさいでしまいPO
LY Siが溶断しなくなってしまう。この様に従来
の技術では少数ビットでかつモールド実装後プログラム
する製品に対しては最適ではなかった。This conventional fuse is the most common type, but as mentioned above, the material of the fuse is a metal that easily sublimates, so if a process that is not included in the standard process of Engineering C is required, or if the metal is used within the standard process. (POLY si)
There are two possible cases using 5. However, if a special metal is used here, the number of process steps increases and the wafer cost is increased, making it extremely unsuitable for fuses of only a few bits. C again! When using POLY Si in fuses such as MO8 IO, if covered with aVD, POLY Si will not melt ((
Normally, the OVD is used as an oven above the POLY Si in the fuse part. In this case, there is no problem when cutting the fuse during wafer inspection, but after mold mounting, the mold material blocks the aVD oven in the fuse section and the PO
LY Si no longer fuses. As described above, the conventional technology is not optimal for products that have a small number of bits and are programmed after being molded.
本発明はかかる問題点を解決するだめのもので標準プロ
セスの工程内で特殊な工程を設ける必要がなく、信頼性
のある安価でかつ、確実にヒ一ズとしての機能を果たす
ヒユーズを提供するものである。The present invention is intended to solve these problems, and provides a fuse that is reliable, inexpensive, and reliably functions as a fuse without requiring any special steps in the standard process. It is something.
本発明の半導体装置は第一の配線金属と第二の配線金属
を有し、前記第一の配線金属と前記第二の配線金属とコ
ンタクトを介して第一の配線金属と第二の配線金属を接
続する抵抗を有し、前記抵抗の中央部を前記第一の配線
金属と第二の配線金属のおのおののコンタクトでつなが
れる低抵抗部分より細くし、その細い部分が前記コンタ
クト部分の低抵抗部分と鋭角となることを特徴とする。The semiconductor device of the present invention has a first wiring metal and a second wiring metal, and the first wiring metal and the second wiring metal are connected to each other through contacts with the first wiring metal and the second wiring metal. The central part of the resistor is thinner than the low resistance part connected by the respective contacts of the first wiring metal and the second wiring metal, and the thin part is the low resistance part of the contact part. It is characterized by an acute angle with the part.
本発明の一実施例を第1図に示す。第1図はヒユーズの
構成で10は配線用のAL、11はPOLY Siの
高抵抗、12はPOLY SiとALのコンタクトを
表している。また13はコンタクトを介してALと接続
される低抵抗のPOLYSiである。11と12のなす
角度が14.15で鋭角となっている。POLY S
iの溶断特性は次の要素が大きく影響する。1つは発熱
量当りの表面積、1つは電流が流れる部分の断面積、1
つは電界の集中である。すなわちもっとも効率よ(溶断
させるには、発熱量が太き(表面積が小さ(かつ断面積
を少な(することが必要である。発熱量を太き(するた
めには抵抗を高(する必要があり、通常のプロセスにお
いてはPOLY Siのシート抵抗はプロセスで固有
であり、またPOLY Siの幅はそのプロセスのデ
ザインルールで制限される。抵抗を高くするとPOLY
Siの長さをのばす必要があるが、表面積が増えて
しまう・。この様に通常の構造では最適な溶断特性を得
るのが難しい。本発明はヒユーズの形状を変え電界を集
中させその部分の発熱量を集中的に高め溶断特性を上げ
るものである。POLY SiのヒユーズにおいてA
L配線とコンタクトで接続される低抵抗の部分J、5と
細(なった高抵抗の部分11の形成する角度が鋭角とな
るとその部分1415には非常に電界が集中し、また発
熱量も集中する。したがって特にそこで溶断しやすくな
るこの様にPOLY Si抵抗の形状はさまざまなも
のが考えられ第2図に本発明の他の実施例を示す。この
実施例も第1図の説明と全く同様である。これは11の
部分を折り曲げて16という鋭角となる部分を形成せし
め、この部分の溶断の可能性も付加し、トータル的に溶
断特性の向上を図っている。この様にして溶断部分をあ
る特定の部分に起こさせ易くすることによって溶断に必
要なエネルギーを減らすことができる。An embodiment of the present invention is shown in FIG. FIG. 1 shows the structure of the fuse, with 10 representing an AL for wiring, 11 a high resistance polysilicon, and 12 a contact between the polysilicon and the AL. Further, 13 is a low resistance POLYSi connected to AL through a contact. The angle between 11 and 12 is 14.15, which is an acute angle. POLYS
The fusing characteristics of i are greatly influenced by the following factors. One is the surface area per calorific value, one is the cross-sectional area of the part where the current flows, 1
One is the concentration of the electric field. In other words, in order to achieve the most efficient melting, it is necessary to have a large amount of heat generation (small surface area) and a small cross-sectional area. In normal processes, the sheet resistance of POLY Si is process-specific, and the width of POLY Si is limited by the design rules of that process.
It is necessary to increase the length of Si, but the surface area will increase. As described above, it is difficult to obtain optimal fusing characteristics with a normal structure. The present invention changes the shape of the fuse and concentrates the electric field to intensively increase the amount of heat generated in that area, thereby improving the fusing characteristics. A at the fuse of POLY Si
If the angle formed by the low-resistance portion J, 5 connected to the L wiring by a contact and the thin high-resistance portion 11 becomes an acute angle, the electric field will be extremely concentrated in that portion 1415, and the amount of heat generated will also be concentrated. Therefore, there are various shapes of the POLY Si resistor which are particularly susceptible to melting at that point, and Fig. 2 shows another embodiment of the present invention.This embodiment is also exactly the same as the explanation in Fig. 1. This is done by bending part 11 to form an acute angle part 16, which adds the possibility of fusing at this part and improving the fusing characteristics overall.In this way, the fusing part The energy required for fusing can be reduced by making it easier to cause this in certain areas.
この様に本発明のヒユーズを用いれば新たに特殊なプロ
セス工程を付は加える必要がないので、はんの少数bi
tのヒユーズでも十分にコストパフォーマンスが良く非
常に安価にできる。またこれは特殊なヒユーズ用金属を
用いた場合と比べ面積重にもその小ささは遜色のないも
ので大容普のヒユーズアレイにも容易に適用できる。ま
たプログンム特性としても通常のPOLY Siヒユ
ーズに比べ確実な書き込み特性が実現できる。また書き
込み特性が非常に低エネルギーの溶断によるために周囲
のCVDやAL、拡散等への破壊的影響を与えないので
工Cの信頼性にとっても非常に有益である。In this way, if the fuse of the present invention is used, there is no need to add any new special process steps, so it is possible to
Even a t fuse has sufficient cost performance and can be made at a very low cost. Furthermore, the area weight is comparable to that of special fuse metals, and it can be easily applied to large-sized and ordinary fuse arrays. Furthermore, as for programming characteristics, more reliable writing characteristics can be realized compared to ordinary POLY Si fuses. Furthermore, since the writing characteristic is based on very low energy fusing, it does not have a destructive effect on surrounding CVD, AL, diffusion, etc., and is very beneficial to the reliability of the process.
以上の様に、本発明を用いれば簡明にできるヒーーズと
して価格的にも、特性的にも非常によいものを提供でき
る。As described above, by using the present invention, it is possible to provide a heater which can be simplified and which is very good in terms of cost and characteristics.
12・・・・・・・・・コンタクト
15・・・・・・・・・POLY Siの低抵抗部分
14115.16・・・・・・POLY Siの鋭角
形成部分
40・・・・・・・・・配線用AL
41・・・・・・・・・POLY Siの抵抗42・
・・・・・・・・コンタクト12... Contact 15... Low resistance part of POLY Si 14115.16... Acute angle forming part 40 of POLY Si...・・Al for wiring 41・・・・・・・POLY Si resistor 42・
········contact
第1図は、本発明の実施例でヒユーズ構造を示す図。
第2図は、本発明の実施例でヒユーズ構造を示す図。
第6図は、従来例を示す図。
10・・・・・・・・・配線用AL
11・・・・・・・・・POLY Siの高抵抗出願
人 セイコーエプソン株式会社FIG. 1 is a diagram showing a fuse structure in an embodiment of the present invention. FIG. 2 is a diagram showing a fuse structure in an embodiment of the present invention. FIG. 6 is a diagram showing a conventional example. 10・・・・・・AL for wiring 11・・・・・・・・・POLY Si high resistance applicant Seiko Epson Corporation
Claims (1)
線金属と前記第二の配線金属とコンタクトを介して第一
の配線金属と第二の配線金属を接続する抵抗を有し、前
記抵抗の中央部を前記第一の配線金属と第二の配線金属
のおのおののコンタクトでつながれる低抵抗部分より細
くし、その細い部分が前記コンタクト部分の低抵抗部分
と鋭角となることを特徴とする半導体装置。It has a first wiring metal and a second wiring metal, and a resistor that connects the first wiring metal and the second wiring metal through a contact with the first wiring metal and the second wiring metal. and the center portion of the resistor is thinner than the low resistance portions connected by the respective contacts of the first wiring metal and the second wiring metal, and the thinner portion forms an acute angle with the low resistance portion of the contact portion. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2161003A JP2876722B2 (en) | 1990-06-19 | 1990-06-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2161003A JP2876722B2 (en) | 1990-06-19 | 1990-06-19 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0451563A true JPH0451563A (en) | 1992-02-20 |
| JP2876722B2 JP2876722B2 (en) | 1999-03-31 |
Family
ID=15726729
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2161003A Expired - Fee Related JP2876722B2 (en) | 1990-06-19 | 1990-06-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2876722B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010062360A1 (en) * | 2008-10-31 | 2010-06-03 | Globalfoundries Inc. | Semiconductor device comprising efuses of enhanced programming efficiency |
| CN109166841A (en) * | 2018-08-29 | 2019-01-08 | 上海华虹宏力半导体制造有限公司 | The polysilicon fuse device architecture of electrically programmable |
| US10916500B2 (en) | 2018-08-10 | 2021-02-09 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
| CN114464595A (en) * | 2022-04-12 | 2022-05-10 | 晶芯成(北京)科技有限公司 | Electric fuse structure |
-
1990
- 1990-06-19 JP JP2161003A patent/JP2876722B2/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010062360A1 (en) * | 2008-10-31 | 2010-06-03 | Globalfoundries Inc. | Semiconductor device comprising efuses of enhanced programming efficiency |
| US8268679B2 (en) | 2008-10-31 | 2012-09-18 | GlobalFoundries, Inc. | Semiconductor device comprising eFUSES of enhanced programming efficiency |
| US10916500B2 (en) | 2018-08-10 | 2021-02-09 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
| CN109166841A (en) * | 2018-08-29 | 2019-01-08 | 上海华虹宏力半导体制造有限公司 | The polysilicon fuse device architecture of electrically programmable |
| CN109166841B (en) * | 2018-08-29 | 2020-08-11 | 上海华虹宏力半导体制造有限公司 | Electrically programmable polysilicon fuse device structure |
| CN114464595A (en) * | 2022-04-12 | 2022-05-10 | 晶芯成(北京)科技有限公司 | Electric fuse structure |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2876722B2 (en) | 1999-03-31 |
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