JPH0451609A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To restrict the overcurrent of an output buffer element flowing at the time of switching and to prevent the destruction of the power line of IC by providing a voltage control circuit in the prestage of a high voltage output buffer element. CONSTITUTION:The voltage control circuit 2 is inserted between a conventional differential input circuit 1 and a high voltage output buffer circuit 3. The gate of pMOSQ 7 in the voltage control circuit 2 receives a voltage Vd. A drain is connected to the cathode of a Zener diode for voltage restriction 11 and is connected to a resistance for current restriction 9 at the same time. The other end of the resistance 9 is connected to the anode of the Zener diode 11 and the gate of pMOSQ 5 in the high voltage output buffer circuit 3, and is connected to the drain of high breakdown strength double diffusion nMOSQ 8 through a resistance for current restriction 10. Thus, a current I0 flowing at the switching time of high breakdown strength pMOSQ 5 can completely be controlled by the voltage control circuit 2 and the destruction of the power line of IC can be prevented without the occurrence of an instantaneous large current.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit having a high voltage output buffer circuit.

[Conventional technology]

As shown in Fig. 3, the high voltage output section of a conventional semiconductor integrated circuit (IC) is a MOS logic circuit (not shown) in the previous stage.
A pair of logic signals Vil with low voltage and mutually opposite phases outputted by Vil
and Vi2 are connected to the low voltage side n-channel transistor (nMO
A differential input circuit 1 has n-channel transistors (abbreviated as pMO3) Ql and QB as loads whose sources are connected to the high voltage VH, and a differentially amplified high voltage logic signal. pMO3Q inputting Vd to the gate
5 and low voltage logic signal Vi4 are input to the gate n M O
It had a high voltage output buffer circuit 3 provided with SQ6 CMOS) transistors.

The high voltage VH supplied to the high voltage output section is about 200V, and the output buffer transistor Q5 used is designed to have a large current and a high withstand voltage.

[Problem to be solved by the invention]

In the conventional semiconductor integrated circuit described above, when the high voltage output buffer element changes from the off state to the on state, a switching current flows temporally during the period when the 0MO3 buffer elements are simultaneously on.

In the high-voltage buffer element, a high breakdown voltage of about 200 V is applied, and since the on-resistance is low, this switching current is large.

Therefore, in the case of an IC having a large number of buffer elements, current particularly concentrates on the power supply line of the buffer element, and the IC power supply line is easily destroyed.

[Means to solve the problem]

The semiconductor integrated circuit of the present invention has a p-channel source follower transistor whose gate receives a first high-voltage logic signal, whose source is connected to a high-voltage source, and whose drain outputs a second high-voltage logic signal via a voltage limiting element. and an n-channel transistor having a gate to which a first low voltage logic signal is input, a drain connected to the voltage limiting element via a current limiting resistor, and a source connected to the low voltage source; and two sources. is inserted between the high voltage source and the low voltage source, the second high voltage logic signal is input to the gate of the n-channel transistor, and the second low voltage logic signal is input to the gate of the n-channel transistor, so that a common It is configured to include a high voltage output buffer circuit having a CMOS transistor that outputs a high voltage logic output signal from its drain.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

In the high voltage output section of this embodiment, a voltage control circuit 2 is inserted between the conventional differential input circuit 1 and the high voltage output buffer circuit 3 shown in FIG.

A MOS logic circuit using a low voltage power supply performs digital signal processing and supplies signals Vil to Vi4 to the high voltage output section.

High-voltage pMOS is used in the high-voltage output section, making it easy to obtain high withstand voltage and high current.
Q1. Q3. Q5. Q7 and its complementary type, double-diffused nMO8Q2゜Q4. Q6. It consists of Q8, current limiting resistors 9 and 10, and a voltage limiting Zener diode 11.

The common sources of all the high voltage pMO8s are connected to the high voltage power supply VH.

The drain of pMO3Q1 of differential input circuit 1 is connected to the drain of high voltage double diffusion nMO3Q2 and the gate of pMO3Q3, and symmetrically, the drain of pMO3Q3 is connected to the drain of high voltage double diffusion nMOsQ4 and the gate of pMO8Q1, and Vd is connected to the drain of pMO3Q1. Output.

The gate of pMO3Q7 of the voltage control circuit 2 receives the voltage Vd, and the drain is connected to the cathode of the voltage limiting Zener diode 11 and also to the current limiting resistor 9.

The other end of this resistor 9 is connected to the anode of the Zener diode 11 and the gate of pMO6Q5 of the high voltage output buffer circuit 3, and is also connected to the drain of the high voltage double diffusion nMOS Q 8 via the current limiting resistor 10. has been done.

High voltage double diffusion nMO8Q2. Q4. The sources of Q6Q8 are all connected to the ground power supply 14, the drain of Q6 is mutually connected to the drain of high voltage pMO3Q5 which is an output buffer element, and the high voltage logic output signal VO is connected to the output terminal.
Output.

Each of the low voltage logic signals Vil to Vi 4 has a high breakdown voltage nM.
It is connected to the gate of O3, and the signals Vi1 and Vi3 are in phase, -Vi2. Vi4 is Vi1.

This signal has a phase opposite to that of Vi3, and is input with shifted timing.

The input order of the low voltage logic signals Vil to Vi4 is the output signal ■
When 0 changes from "L" to "H'l", (1)...V
i 4 (2)...Vi3 (3)...Vil, Vi2 Also, when VO changes from 'H°' to "L II" (1)
...Vi3 (2)...V i 1, Vi 2 (3)・
...It is set in the order of Vi4.

When the high voltage logic output signal ■0 is "Yes", that is, when the low voltage logic signals Vil and Vi3 are "'L'" and Vi2 and Vi4 are "H", the high voltage MO3QI.

Q4. Ql, Q6 are on, Q2. Q3. Q8°Q5 is in the off state.

Here, when the low voltage signal Vi4 changes from "H'" to "L",
MO3Q6 is gradually turned off.

After the input logic signal Vi3 changes from "L" to "H"', the signal Vil changes from L" to "H", and ■12 changes from "'H°'→"
When it changes to L'', MO8Q8 gradually turns on, then MO8Q2 also turns on, and MO3Q4 turns off.

At this time, since MOSQ8 is gradually turned on while MO3Q7 remains on, MO3Q7. Q8 is turned on at the same time, but the power supply current is suppressed by the current limiting resistor 9.10.

Also, at this time, the gate voltage of MO3Q5 is equal to the voltage VH of the high voltage power supply by the Zener voltage Vz of the Zener diode 11.
As long as pMO3Q7 is turned on even slightly and current flows, the voltage VG applied between the source and drain of high voltage pMO3Q5 will never exceed the zener voltage Vz, and the current flowing to MO3Q5 will never exceed the Zener voltage Vz. is MO3
The current is limited to a constant level until Q7 turns off.

When MO3Q7 is completely off and MOSQ5 is on, MO3Q6 is either completely off or has sufficient resistance, so no instantaneous large current will flow due to switching.

Conversely, when the output signal VO is "H", that is, the low voltage logic signals Vi1 and Vi3 are "')l", and Vi2.Vi4 are "')".
When “L”, high voltage MO3QI, Q4゜Ql, Q6
is off, Q2. Q3. Q8. Q5 is in the on state.

Here, when the input signal Vi3 changes from "H" to "L", MO3Q8 is gradually turned on. And Vil is H″→
After Vi2 changes from “L” to “H”,
Vi4 changes from “L” to H (H11, MO8
Q2. Q3 gradually turns on, t7, MOSQ4, and Ql gradually turn on, and as a result, MO8Q7 also turns on gradually.

Therefore, MO3Q7. Q8 is turned on at the same time, but as in the previous case, the current from the power supply is suppressed by the current limiting resistor 9°10, and the gate-source voltage VG of MO3Q5 remains as long as MO6Q7 is turned on even slightly. Zener voltage Vz is applied and current flows to MOSQ5. is limited to a certain extent.

When MO3Q7 is completely turned on and MO3Q8 is completely turned off, MO3Q5 is also turned off and no current flows.

In this way, the current flowing during switching of the high-voltage pMO8Q5 is completely controlled by the voltage control circuit 2 inserted before the gate, preventing the destruction of the IC power supply line without generating a momentary large current. I can do it.

FIG. 2 is a circuit diagram of a second embodiment of the invention.

The high voltage output circuit is almost the same as the first embodiment, but the first
In this example, a current limiting resistor 9 and a voltage limiting Zener diode 11 were used at the drain of the high voltage pMO3Q7, whereas in this example, a high voltage pMO3Q12 was used.
are using.

The source of this high voltage PMO3Q12 is a high voltage PMO3Q.
7, and its gate is connected to the drain and connected to the gate of high voltage pMO3Q5 and one end of current limiting resistor 10. The other end of the current limiting resistor 10 is the first
As in the embodiment, it is connected to the drain of the high voltage double-diffused nMOS Q8.

The gate of pMO3Q12 is connected to the drain,
It has the characteristic that it maintains a nearly constant voltage between the source and drain.

Also, Ql2 and Q5 are high voltage pMOs with exactly the same structure.
While Ql of s is on, the mirror circuit is refined, and the ratio of the channel widths of Ql2 and Q5 becomes the ratio of their respective drain currents.

If the ratio of the channel widths of pMOsQl2 and QB is 10 times the current flowing to the drain of pMO3Q5, the gate voltage VG of QB will always be limited to a constant value by pMOsQl2.

In this way, this embodiment also operates in the same way as the first embodiment, and can limit the overcurrent flowing to the high voltage output buffer element. Since it is constructed using MOSFETs without using any elements, it has the advantage that the circuit construction is simple and space-saving.

〔Effect of the invention〕

As described above, the present invention has the effect of limiting the overcurrent flowing during switching of the output buffer element by providing a voltage control circuit before the gate of the high voltage output buffer element.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a first embodiment of the present invention, FIG. 2 is a circuit diagram of a second embodiment of the present invention, and FIG. 3 is a circuit diagram of an example of a conventional semiconductor integrated circuit of the present invention. be. DESCRIPTION OF SYMBOLS 1... Differential input circuit, 2... Voltage control circuit, 3... Output buffer circuit, 9, 1o... Current limiting resistor, 11... Zener diode for voltage limiting, 13
... High voltage power supply, 14... Ground power supply, Ql, QB. QB, Q7. Ql 2-...High voltage pMO8, Q2゜Q
4. Q6. Q8. , , High voltage double-diffused nMO3, Vil
~V i 4...Low voltage logic signal, ■o...High voltage logic output signal, Vd...Differentially amplified high voltage logic signal, V
G...Gate voltage, VH...High voltage.

Claims (1)

[Claims] A p-channel source follower transistor whose gate receives a first high-voltage logic signal, whose source is connected to a high-voltage source, and whose drain outputs a second high-voltage logic signal via a voltage limiting element; a voltage control circuit having an n-channel transistor to which a signal is input, a drain connected to the voltage limiting element via a current limiting resistor, and a source connected to a low voltage source; and two sources connected to the high voltage source and the low voltage source. the second high-voltage logic signal is input to the gate of the p-channel transistor, the second low-voltage logic signal is input to the gate of the n-channel transistor, and a high-voltage logic output signal is output from the common drain. A semiconductor integrated circuit comprising a high voltage output buffer circuit having a CMOS transistor.