JPH0451688U

JPH0451688U -

Info

Publication number: JPH0451688U
Application number: JP9483890U
Authority: JP
Priority date: 1990-09-10
Filing date: 1990-09-10
Publication date: 1992-04-30

Description

[Brief explanation of the drawing]

第１図はこの考案の一実施例を示す図、第２図
は第１図各部の信号波形を示す図、第３図は従来
の復調装置を示す図、第４図及び第５図は第３図
各部の信号波形を示す図である。図において、１は符号系列発生器、２は符号系
列信号、３は第１の二重平衡変調器、４は受信信
号、５は復調信号、６は第１のスイツチ、７はレ
ンジゲート、８は電力分配器、９は第２の二重平
衡変調器、１０は非反転増幅器、１１は反転増幅
器、１２は第２のスイツチ、１３は電力合成器で
ある。なお、図中同一あるいは相当部分には同一
符号を付して示してある。 FIG. 1 is a diagram showing an embodiment of this invention, FIG. 2 is a diagram showing signal waveforms at various parts in FIG. 1, FIG. 3 is a diagram showing a conventional demodulator, and FIGS. FIG. 3 is a diagram showing signal waveforms of each part. In the figure, 1 is a code sequence generator, 2 is a code sequence signal, 3 is a first double-balanced modulator, 4 is a received signal, 5 is a demodulated signal, 6 is a first switch, 7 is a range gate, and 8 9 is a power divider, 9 is a second double-balanced modulator, 10 is a non-inverting amplifier, 11 is an inverting amplifier, 12 is a second switch, and 13 is a power combiner. It should be noted that the same or corresponding parts in the figures are indicated by the same reference numerals.

Claims

[Scope of utility model registration request]

It consists of a code sequence consisting of two values, +1 and -1, with a constant period, and a code sequence signal synchronized with the reception timing, in which positive voltage and negative voltage are associated with each binary value, and a code sequence signal synchronized with the reception timing. a code sequence generator that generates a range gate signal;
a power divider that divides the received signal into two; a non-inverting amplifier that amplifies the code sequence signal in the same phase; and an inverting amplifier that amplifies the code sequence signal in opposite phase; a switch that switches the outputs of both amplifiers using the range gate signal; a first double-balanced modulator which demodulates the received signal by receiving the code sequence signal switched by the input signal and the output of one of the power dividers, and the other output of the power divider and the output of the non-inverting amplifier; a second double-balanced modulator that demodulates the received signal, and a power that combines the demodulated signals that are the outputs of the first double-balanced modulator and the second double-balanced modulator. A demodulation device comprising a combiner and a switch that switches the output of the power combiner using the range gate signal.