JPH045193B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an automatic performance device that reads and reproduces predetermined musical tone information stored in a memory to perform automatic performance.

[Prior art]

2. Description of the Related Art Electronic musical instruments that perform automatic performance by reading and reproducing musical tone information in a memory have been developed and put into practical use.

[Problems with conventional technology]

When automatically playing a piece of music in which the musical tone information at the beginning is information indicating a rest, it is undesirable that a silent state continues from the time when the start of automatic performance is instructed until the musical tone actually starts to be generated.

[Purpose of the invention]

To realize an automatic performance device that starts generating musical tones immediately after an instruction to start automatic performance is given even when automatically playing a piece of music starting from a rest.

[Summary of the Invention] When starting automatic performance of a piece of music starting from a rest, the rest is ignored or the length of the rest is shortened.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing the overall configuration of an electronic musical instrument equipped with an automatic performance function. Keyboard switch part 1
It has multiple keys and various switches for obtaining various effects such as tone, vibrato, sustain, stereo sound localization, normal rhythm, full-in rhythm, and automatic accompaniment, as well as RAM (random access memory) described later. It is equipped with a channel designation switch, etc. For example, reset switch 1
A, reverse switch 1B, record switch 1
C, end key 1D, etc., and their functions will be described later. and CPU (Central Processing Unit) 2
scans the keyboard switch section 1 by periodically outputting a key scan signal via the bus line B1,
In response, the keyboard switch unit 1 outputs output signals from each key and switch and provides them to the CPU 2 via the bus line B2. In response to this, the CPU 2 gives, for example, musical tone generation command information to the musical tone generating section 3 via the bus line B3, and causes the musical tone signal of a melody or automatic accompaniment to be generated and supplied to the localization control section 4. In addition, CPU2 is
Control information in accordance with the sound image localization information preset in the RAM 5 is output to the balance line B4 and given to the sound image localization control section 4, which sets the sound image localization for the musical sound signal and outputs the control information to the left and right speakers 6.
Corresponding signals are output to R and 6L to emit musical tones.

Data read and write operations of the RAM 5 are controlled in accordance with address control information supplied by the CPU 2 to the address register 7 via the bus line B5. Data is exchanged between the CPU 2 and the RAM 5 via the bus line B6. In this case, RAM5 stores the pitch, length, etc. of the song.
Musical tone information indicating rests (hereinafter referred to as melody information for convenience), tone, vibrato, sustain,
Performance information for obtaining various effects such as sound image localization, fill-in rhythm on/off, etc. is stored in different areas, respectively. The address register 7 contains 1 for each of the melody information and performance information.
An independent address counter is provided for each, so that during automatic performance, the melody information and performance information are updated as the melody progresses.
They are read out in parallel and simultaneously, allowing for automatic performance.

The recording section 8 calculates the tone length from the time information (data D ₇ to _{D 0} ) given from the CPU 2 via the bus line B7 and the time information (data TD ₇ to _{TD 0} ) given from the playback section 9 via the bus line B11. time information (data I ₇ to I ₀ ) representing the time is created, is supplied to the CPU 2 via the bus line B8, and is written into the RAM 5 as the melody information or performance information.

The playback unit 9 receives information in accordance with the melody information and performance information read from the RAM 5 during playback from the CPU 2 via the bus line B9, creates data for playback processing, and sends the data to the bus line B10. Also, as mentioned above, time information is given to the recording unit 8 during recording. Note that the CPU 2 is a processor that controls all operations of this electronic musical instrument, and a detailed explanation thereof will be omitted. Furthermore, for the same reason as the provision of the two address counters, both the recording section 8 and the reproducing section 9 are provided with a plurality of identical circuits, each of which operates independently.

Next, other switches on the keyboard switch section 1 will be explained with reference to FIG. The start switch 1E is a switch for inputting a recording start command. Also, a first channel designation switch 1F1, a second channel designation switch 1
F2 is a switch for specifying the first channel and second channel of the RAM 5, respectively, and the record switch 1 is used when recording musical tone information of a melody.
Operate at the same time as C. In this case, Sweets 1F1 and 1
If you operate C at the same time, the first channel will be designated, and if you operate the key after operating start switch 1E, the musical tone information of the predetermined melody will be stored in the RAM.
5 is written. On the other hand, when the switches 1F2 and 1C are operated simultaneously, the second channel is designated, and when the start switch 1E is operated and then the key is operated, musical tone information of another melody is written into the RAM 5. For example, if you first write a melody to the first channel, then the second
When writing another melody to the channel, turn on only switch 1F1, and then turn on switch 1F1.
By operating both F2 and 1C at the same time and then operating the start switch 1E, the melody of the first channel is played, and while listening to it, another melody can be written to the second channel. Further, the play switch 1G is a switch for simultaneously reading out and playing back the two melodies written in the first channel and the second channel of the RAM 5, respectively, as described above, so that they are automatically played.

Next, the configuration of the recording section 8 will be explained with reference to FIG. The PR latch 11 normally contains the count output of the UP/DOWN counter (described later) in the playback unit 9 as data.
When the signal LAT is input as TD ₇ to _{TD 0} through the transfer gate group 12 and the CPU 2 outputs the signal LAT,
latch it. Also, when the playback operation is temporarily stopped during playback, rewinding is performed by operating the reverse switch 1B, and then new recording is started, the latch data of the PR latch 11 is transferred via the CPU 2 to the playback section 8. The output data of the full adder at that time is sent to the full adder described later, and conversely, the output data of the full adder at that time is sent to the full adder, which will be described later.
As data D ₇ to D ₀ , transfer gate group 1
3, it is further latched to PR latch 11.
Then, the data latched to the PR latch 11 is
It is applied to the B input terminals (B7 to B0) of the subtracter 14. In addition, the A input terminal of the subtracter 14 (A7 to A
0), the data TD ₇ ...TD ₀ are input. The subtracter 14 subtracts the input data at the B input terminal from the input data at the A input terminal, and sends the resulting data I7 to I0 to the RAM 5 via the CPU 2 for storage. In the case of melody information, this data I7 to I0 indicates time data giving a key-on time and key-off time, and on the other hand, in the case of the other musical tone information of an effect, it is time data indicating the generation period of the effect. . The transfer gate group 12 has the signal CH output from the CPU 2 applied to its gate via the inverter 15, and the transfer gate group 13 is gate-controlled by having the signal CH directly applied to its gate. .

Next, the configuration of the reproducing section 9 will be explained with reference to FIG. 6. The UP/down counter 17 is an 8-bit counter, and after being cleared by the CPU 2 outputting a clear signal CLR at the start of recording or playback, the UP/down counter 17 is reset based on the signal output from the output terminal P of the tempo oscillator 18. Performs a counting operation that counts clocks.

Furthermore, the frequency of the oscillation output of the tempo oscillator 18 is variable by a tempo volume 19;
The output of the tempo oscillator 18 is then input to an AND gate 20. The output of the tempo switch ESW is input to the other end of the AND gate 20 for gate control, and the output of the AND gate 20 is input to a T-type flip-flop 21 and a transfer gate 23. Further, the set output of the flip-flop 21 is input to a T-type flip-flop 22 and a transfer gate 24. Furthermore, the set output of flip-flop 22 is input to transfer gate 25. Each of the transfer gates 23, 24, and 25 has an output of a tempo acceleration switch CSW, a normal switch FSW, and a slow tempo switch DSW, each of which is a triple lock type switch in which only one is in the on state. applied and gated. and each transfer gate 23,
Each output of 24 and 25 is used as the clock UP/
The signal is applied to the down counter 17 via the OR gate 37 and counted. So flipflop 21,
Reference numeral 22 forms a frequency dividing circuit, and the frequencies of the outputs of the flip-flops 21 and 22 are respectively 1/2 and 1/4 of the output of the tempo oscillator 18.

Furthermore, as shown in the figure, the tempo oscillator 18 outputs from its output terminal Hi a signal faster (higher frequency) than the signal output from the output terminal P, and passes through the transfer gate 36 and OR gate 37 to the up/down signal. It is applied to counter 17 as a clock. This means that if rest information is included as the first tone information of the melody of at least one channel of RAM 5, the CPU 2 detects the rest information and then starts the first tone that is actually sounded.
Until the musical tone information of the musical tone is read out, the gate control signal FF of "1" level is outputted to open the transfer gate 36, and the high speed clock is applied to the up/down counter 17, thereby: This is to prevent the generation of silent periods due to rest information by performing fast-forward read processing for the RAM 5.

The up-count operation and down-count operation of the up/down counter 17 are controlled by the set output signal UP of the flip-flop 26, respectively.
It is carried out by. That is, flip-flop 2
The outputs of a forward switch BSW and a reverse switch ASW (same as the reverse switch 1B in FIG. 1) each consisting of a double lock type switch are input to the set input terminal S and the reset input terminal R of 6, respectively.
Each bit output of the UP/DOWN counter 17 is input to one end of each of the corresponding exclusive OR gates ₂₇₇ to ₂₇₀ , and is also sent to the recording section 8 as data _TD7 to _TD0 . Also, exclusive or gate 2
Corresponding bit outputs of an 8-bit capacity NE latch 28 are input to the other ends of the pins ₇₇ to ₂₇₀ . The respective outputs of the exclusive OR gates 27 ₇ to 27 ₀ are input to the NOR gate 29, and the output of the NOR gate 29 is further supplied to the CPU 2 as a match signal. That is, the exclusive OR gates 27 ₇ to 27 ₀ and the NOR gate 29 form a matching circuit.

The NE latch 28 latches the addition or subtraction result data from the S output terminals S ₇ -S ₀ of the full adder 30 when the CPU 2 outputs a latch clock. Further, the NE latch 28 is cleared by applying a clear signal CLR output from the CPU 2 at the start of recording and reproducing operations. A input terminals _A7 to _A0 of the full adder 30
In this case, the latch data is fed back to the NE latch 28 via the transfer gate group 31 and inputted thereto. Further, the outputs of the exclusive OR gates 32 ₇ to 32 ₀ are input to the B input terminals B ₇ to _{B 0} , and the output of the AND gate 33 is input to the carry input terminal C _IN . I am inputting it through. Therefore, exclusive or gate 32 ₇ ~3
₂₀ , time data from the PR latch 11 in the recording section 8 is input in response to key operations when performing any recording operation for correction after rewinding during playback. Further, the output of the AND gate 33 is applied to each other end via an inverter 34 and a transfer gate 35.

The set output of the flip-flop 33 and the signal R output from the CPU 2 are input to the AND gate 33. This signal R is normally output as "1" and is temporarily output as "0" during the recording correction. and and gate 3
The output of 3 is sent to CPU2. Further, the transfer gate group 31 and the transfer gate 35 are gate-controlled by the signal CHR outputted by the CPU 2, but this signal CHR is temporarily set to "0" when making corrections during recording.
is the output signal. Furthermore, the latch data of the NE latch output from the transfer gate group 31 is sent to the PR latch 11 when data is corrected during reproduction.

Furthermore, the latch data of the NE latch 28 and up/down are input to the A input terminal and the B input terminal of the subtracter 38, respectively.
The count value data of the down counter 17 is input respectively, and the subtracter 38 subtracts the count value data from the latch data during the fast-forwarding process of the RAM 5, and provides the resulting data to the NE latch 28 to latch. let

Next, an explanation will be given of the operation of recording the two pieces of music shown in the musical score of FIG. 9 (round-singing pieces) on the first channel and the second channel of the RAM 5, respectively, and reproducing them. First, the operation in the case of recording will be explained with reference to the flowchart of FIG. Assume that the first song to be played is recorded on the first channel, and the subsequent songs are recorded on the second channel. Further, the melody information of the song is written into the RAM 5 by normal performance by key operations on the keyboard switch section 1.

Prior to starting recording, record switch 1C and first channel designation switch 1F1 are pressed simultaneously to input a recording command to the first channel of RAM5. Next, turn on the start switch 1E,
After inputting the recording start command, the first song starts playing. The output of the clear signal is input to the CPU 2 via the bus line B2, and the CPU 2 accordingly performs the process of step _RM1 in the flowchart of FIG. That is, the clear signal CLR is output to the bus lines B7 and B9, respectively, and the PR latch 11,
Clear the NE latch 28 and UP/down counter 17, respectively. Next, the CPU 2 sets the address counter for the melody information in the address register 7 by outputting address control information for setting the starting address for the melody information in the RAM 5 to the bus line B5 (step RM ₂ ). next
The CPU 2 outputs data NOP to the bus line B6 and writes it to the start address (address 0) of the RAM 5. FIG. 5 schematically shows the storage state. Therefore, this data NOP (NO
OPERATION) is data indicating a rest.
The above is the process of step _RM3 . and then
The CPU 2 increments the address counter of the address register 7 (hereinafter simply referred to as the address register 7) by 1 in step _RM4 , and sets address 1. Next, in step _S5 , it is determined whether or not the reset switch 1A has been turned on. This reset switch 1A is a switch that is turned on when correcting the recording, and when turned on, the step
Returns to RM ₁ processing and is set to the initial state. On the other hand, when not turned on, step RM ₆
Then, it is determined whether the end key 1D has been turned on. Therefore, this end key 1D is
This is a switch that is turned on when the input of melody information is completed to write an end code at the end of the melody information that has been input into the RAM 5. Therefore, when the end key 1D is turned on (Y "YES"),
The process advances to step _RM7 and the above-described processing is executed. However, since the end key 1D is not turned on at this time (N "NO"), the program proceeds to step _RM8 , and a process for determining whether or not the reverse switch 1B (reverse switch ASW) is turned on is executed. When it is turned on, the process of moving to the recording standby state in step _RM9 is executed, and this process will be explained in detail later. Of course, the reverse switch 1B is not turned on at this time, and the process proceeds to step _RM10 , where it is determined whether or not the key has been operated. Then, until the key of the first musical tone (musical tone of pitch C ₃ ) of the melody of the first song in Figure 9 is turned on and the melody performance actually starts, there are no steps.
RM ₁₀ , RM ₅ , RM ₆ , RM ₈ , RM ₁₀ ,... are repeated. When the C ₃ key is turned on after a half-rest interval after the performance starts, the process proceeds to step RM ₁₁ , where a process to determine whether the key is pressed or released is executed. Proceeding to step RM ₁₂ , the CPU 2 inputs the MSB (most significant bit) of the key code to indicate that it is the key code and key press data for pitch C ₃ .
The musical tone information is calculated by adding data "0" to the data. Then, it is given to the musical tone creation section 3 via the bus line B3, and is sent to the speakers 6R and 6L.
(Step RM ₁₃ ). Next, the process proceeds to step _RM16 , where the CPU 2 sets the signal CH to "0", and thereafter, in normal times, the transfer gate group 12 is always open and the transfer gate group 13 is always closed. As a result, the playback section 9
After clearing step RM ₁ mentioned above,
The clock at the set tempo is input and the counting operation is already in progress (the forward switch BSW is currently on, the flip-flop 26 is set, and the up-counting operation is in progress).
The count output of the UP/down counter 17 (time data corresponding to a half-minute rest) is sent as data TD ₇ to _{TD 0} to the A input terminal of the PR latch 11 and the subtracter 14 via the bus line B 11 and the 12 groups of transfer gates. will be input to. Then, the subtracter 14 subtracts the input data from the PR latch 11 to the B input terminal from the input data to the A input terminal, and outputs this result to the CPU 2 as time data.
Next, the process of step _RM17 is executed, and the CPU2
applies the signal LAT to the PR latch 11, causing the data being input at that time to be latched in the PR latch 11,
Thereafter, the latch data is held and applied to the B input terminal of the subtracter 14. Meanwhile, step _RM18 is executed in parallel. Therefore, the input data to both input terminals of the subtracter 14 are as follows.
Time data of half-minute rest and PR cleared at the beginning
The latch data of the latch 11 is "0", and therefore the resulting data I ₇ to I ₀ at that time is the time data of the half rest, and is stored in the address 1 of the RAM 5. In FIG. 5, this resultant data is indicated as "T8" which means time data of half-rest length. Next, address register 7 is incremented by 1 to set address 2 (step RM ₁₉ ), and this
The already calculated key press code, that is, the key code (C ₃ ) and the key press data ("0") are written into address 2 of the RAM 5 (step RM ₂₀ ). Then, the address register 7 is incremented by 1 to set address 3 (step RM ₂₁ ), and the process returns to step RM ₅ .

Next, when it is determined in step RM ₁₀ via steps RM ₅ , RM ₆ and RM ₈ that the key has been released,
Proceeding to step RM ₁₄ , a process is executed to add data "1" to the MSB of the key code to indicate that it is the key code of pitch C ₃ and key release data, and a key release code is created. . Then, it is sent to the musical tone generating section 3, whereby the musical tone of pitch _C3 is muted (step _RM15 ). Next, when proceeding to step RM ₁₇ via step RM ₁₆ , the time data of the UP/down counter 17 at the time of the key release operation is newly latched in the RM latch 11, and is held thereafter. is applied to the B input terminal of. Then, the subtracter 14 subtracts the time measurement data inputted to the A input terminal at the time of the key release operation from the time measurement data inputted to the B input terminal to obtain the result data, and obtains the time data. is written to address 3 of RAM5 (step RM ₁₈ ). In this case, as shown in Figure 5, the time data at this time is "T3".
This represents the key-on time of a quarter note in pitch _C3 . And step
Through the processes R ₁₉ and RM ₂₀ , the key release code is written in address 4 of the RAM 5, as shown in FIG. Address 5 is then specified in step RM ₂₁ , and the process returns to step RM ₅ .

Next, when the pitch E ₃ key of the second musical tone is pressed, this is determined in step RM ₁₀ , and step
The program proceeds to step RM ₁₂ via RM ₁₁ , and the key press code is calculated in the same manner as when the key is operated for pitch _C3 . Then, through the process of step _RM13 , creation and sound emission of a musical tone of pitch _E3 is started. and step
Through each process of RM ₁₆ , RM ₁₇ , and RM ₁₈ , the PR latch 11 latches the time measurement data when the pitch E ₃ key is pressed, and the subtracter 14 latches the clock data when the pitch E ₃ is pressed to the A input terminal. The data obtained by subtracting the time data at the time of key release of the pitch _C3 input to the B input terminal from the time data at the time of key depression is obtained and written to address 5 of the RAM 5. In this case, as shown in FIG. 5, the time data based on the result data is "T1",
This represents the key-off time for the key of pitch C ₃ . Thus, the total time of the key-on time and key-off time of the quarter note is "T4". In addition, after the processing of step RM ₂₀ , step
RM ₂₁ specifies the next 6 addresses of RAM5,
Return to step RM ₅ .

Below, the process when releasing the key of pitch E ₃ is as follows:
This is the same as when the key of C ₃ is released, and the same applies to each process from the third tone onward according to FIG. And when the last note has been processed,
Turn on end key 1D and write end code to RAM
5 as the last data of the melody information.

As described above, when the first song shown in FIG. 9 is recorded on the first channel of the RAM 5, the same song after the song shown in FIG. 9 is recorded on the second channel. The operation in this case is almost the same as in the case described above, but the switch operations and the like before starting the performance are slightly different. That is, first, only the first channel designation switch 1F1 is turned on. Next, record switch 1C and second channel designation switch 1
Turn on F2 at the same time, then start switch 1E
Turn on. Then, start playing. In this case, the melody information of the song already written in the first channel is read out and sent to the musical tone creation section 3, and played back according to the flowchart of the playback process shown in FIGS. 7A and 7B, which will be described later. The sound will begin to be emitted. Then, the subsequent song is played along with the played song and recorded on the second channel.

Figure 8 shows the content of the melody information written in the second channel. Since the beginning of the song is a whole rest, the time data "T16", which is twice as long as the half rest, is placed at address 1. has been written, and the data at other addresses are the same as the contents of the first channel.

Next, the process of step _RM9 when the reverse switch 1B is turned on will be explained. This reverse switch 1B (reverse switch ASW) is a process that turns on when a key operation is made by mistake when inputting the melody information, returns the address register 7 to the desired address, and sets the correct melody information to a standby state where it can be recorded. In that case, when the reverse switch 1B is turned on, the latch data of the PR latch 11 at that time is sent to the CPU.
2 to the NE latch 28 of the reproducing section 9. A corrective recording operation is then initiated.

After writing the melody information to the RAM 5 as described above, if there is information on various effects, that is, performance information other than the melody information, it is further written to other channels of the RAM 5. Therefore, detailed explanation of this operation will be omitted.

Next, with reference to FIGS. 7A and 7B, an explanation will be given of the operation when individually reproducing and emitting the songs recorded in the first channel and the second channel of the RAM 5 as described above.

For example, if you want to play only the songs on the first channel, first turn on the first channel designation switch 1F1, then turn on the start switch 1F1.
Turn on E.

A clear signal is output by the processing in step _SM1 , and both the NE latch 28 and the UP/down counter 17 in FIG. 6 are cleared. Next, step SM ₂
As a result of the process, the start address for the melody information written in the first channel of the RAM 5 is set in the address register 7. Then, the processing data "NOP" (see FIG. 5) is read out from the RAM 5 and supplied to the CPU 2 (step SM ₃ ). Then, the address register 7 is incremented by 1 and address 1 is set (step SM ₄ ). Then, the CPU 2 performs a process of determining whether the MSB of the data "NOP" is "0" or "1", but in this case, since the data is "NOP" indicating a rest, the CPU ₂ performs a process of determining whether the MSB of the data "NOP" is " ₁ " or not. Then, a control signal corresponding to a key-off signal is output to the musical tone generating section 3, and the execution of musical tone generation is prohibited. Also, when proceeding to step SM ₈ , time data "T8" is obtained from address 1 of RAM5.
, and add 1 to address register 7 to make 2.
Set the address (step SM ₉ ) Set the time data “T8” from address ₀ and 1 to B of full adder 30.
input to the input terminal, and then send the resulting data to the NE
Latch latch 28 (step SM ₁₀ ,
_SM11 ). In this case, the order switch is now turned on.
BSW is turned on, and as a result, the flip-flop 26 is in the set state, the AND gate 33 is opened, and the counter 17 is connected to UP/DOWN.
is given an upcount command. The signal R is normally being output as "1", so the output of the AND gate 33 is normally "1", and this signal is supplied to the CPU 2, and
The output of the inverter 34 is normally "0" and is supplied to one end of each of the exclusive OR gates 32 ₇ to 32 ₀ and the carry input terminal C _IN of the full adder 30 via a transfer gate 35 . Note that the signal CHR is normally output as “1”,
Therefore, the transfer gate 35 or the transfer gate group 31 is normally open.

Therefore, in steps SM ₁₀ and SM ₁₁ ,
The time data “T8” is an exclusive OR gate 32 ₇
~ ₃₂₀ , it is input to the B input terminal of the full adder 30 as it is without being inverted. on the other hand,
The output data of the NE latch 28 (8-bit all "0" data) is input to the A input terminal via the transfer gate group 31, so the full adder result data at that time is "T8".
It will be latched to NE latch 28.

Next, in the determination process of step _SM12 , it is determined whether or not the match signal from the NOR gate 29 is output at the "1" level. Therefore, in this case, exclusive or gates 27 ₇ to 27 ₀ are UP/DOWN, respectively.
8-bit all “0” data of counter 17,
Since the latch data "T8" of the NE latch 28 is input, a "0" level match signal indicating a mismatch is supplied to the CPU 2, and the process proceeds to step _SM14 , where the reverse switch 1
B is operated and it is determined whether or not the up/down signal is inverted, and since it is "NO", the process proceeds to step SM ₁₈ , where it is determined whether or not recording is in progress, and it is similarly determined to be "NO", and the process advances to step SM18. ₂₀ , it is determined whether or not reset switch 1A is turned on.
Furthermore, it is determined as "NO" and the process returns to step _SM12 . Then, until the coincidence signal of the "1" level is output, that is, until the count value data of the up/down counter 17 reaches the time data "T8", the steps SM ₁₂ , SM ₁₄ , SM ₁₈ , _SM20 ,
SM ₁₂ ,... are repeated, and a rest state in which no musical tone is produced continues. When a coincidence signal of the "1" level is output, the rest time of the half rest ends, and the process proceeds to step _SM13 . In step _SM13 , it is determined whether up-counting or down-counting is in progress, and if it is determined that up-counting is in progress, the process proceeds to step _SM3 .

Next, in step _SM3 , the key code "C ₃ " and the key press data "0", that is, the data "C ₃ , ON" in FIG.
In step _SM4 , address 3 of RAM5 is set. Then, in step _SM5 , the key press data ``0'' is determined, and the process proceeds to step <sub>SM6</sub> , where a key code ``C ₃ '' and a key-on signal are given to the tone generator 3, and as a result, the key press data ``0'' is determined. One musical tone is reproduced, and the sound emission starts from the speakers 6R and 6L. Then, at step _SM8 , time data "T3" is read from address 3 of RAM5, and at step _SM9 , time data "T3" is read from address 3 of RAM5.
Address 5 of 4 is set. The time data "T3" is applied as is to the B input terminal of the full adder 30. On the other hand, the time data "T8" while the NE latch 28 is latched is being input to the A input terminal of the full adder 30, and therefore the full adder 30
The current addition result data of 0 is equal to the time data "T11", and in addition to being newly latched to the NE latch 28, the exclusive OR gate ₂₇₇
~ ₂₇₀ (step _SM11 ). and,
Proceeding to step _SM12 , the coincidence signal is "1"
The above steps are performed until it is determined whether the level is output or not, and the output is performed at the “1” level.
Each process of SM ₁₄ , SM ₁₈ , SM ₂₀ , and returning to step SM ₁₂ is repeatedly executed.

Then, when the ON time (time data T3) of the first musical tone of the key code "C ₃ " has elapsed and a "1" level match signal is output, the process advances to step _SM13 , and then to step _SM3 . RAM5 of 4
From the address, key code "C ₃ " and key release data "1",
That is, the data "C ₃ , OFF" in FIG. 5 is read out. Further, in step _SM4 , address 5 of RAM 5 is set. Then, in step _SM5 , the key release data "1" is determined, and the process proceeds to step _SM7 , where a key code " _C3 " and a key-off signal are given to the musical tone generator 3, and the first musical tone is emitted. The sound is stopped. Next, in step _SM8 , the time table "T1" is read from address 5 of RAM5, and in step _SM9 , address 6 of RAM5 is set. Then, by steps SM ₁₀ and SM ₁₁ , the time data "T1" is input as is to the B input terminal of the full adder 30, and at this time, the time data "T11" of the previous result data is input to the A input terminal. Therefore, the addition result data output from the full adder 30 is "T12", and the NE latch 28
In addition to being newly latched, the signals are applied to exclusive OR gates ₂₇₇ to ₂₇₀ . and step
The process proceeds to SM ₁₂ , and the steps described above are carried out until the count value of the up/down counter 17 increases to the time data "T12" and a coincidence signal of "1" is output.
Each process of SM ₁₄ , SM ₁₈ , SM ₂₀ , SM ₁₂ , . . . is repeated, and during this time, the first musical tone is muted and the key is off. Further, when a coincidence signal of the "1" level is output, the process proceeds to step _SM13 , and further proceeds to step _SM3 .

The reproduction processing for the first musical tone is thus completed, and the reproduction operation for the second musical tone and subsequent musical tones is performed in the same manner.

Next, an explanation will be given of the operation when the reverse switch 1B is operated to switch the up count to the down count for correction work when a coincidence signal of "1" is determined in step _SM12 . As a result of this switching operation, the flip-flop 26 is reset, and the AND gate 33 is subsequently closed and its output becomes "0".
The signal is applied to the CPU 2 and the inverter 34. Further, a down-counting command is input to the up/down counter 17, and accordingly, a down-counting operation is started to enter a rewinding state. When this is determined at step _SM13 , the process at step _SM22 in FIG. 7B is started. That is, RAM
5, the processing data of the area specified by the address of the address register 7 at that time is read out. For example, data ``G ₃ , ON'' from address 10 (Fig. 5,
The key press code of the third tone is read out. Then, by step _SM26 , the address register 7 is set to -1.
address 9 is set. Then step SM ₂₄ ,
The key depression code is determined by SM ₂₅ , and a new command to mute the third tone is given. next
Time data "T1" is read from address 9 of RAM 5, and address register 7 is incremented by 1 to become address 8 (steps SM ₂₇ and SM ₂₈ ). Next, in step _SM29 , the time data "T1" is applied to the full adder 30, but in this case, since the signal CHR is "1", the output "1" of the inverter 34 is directly applied to the exclusive OR gates ₃₂₇ to ₃₂₀ , Applied to the carry input terminal C _IN of the full adder 30. As a result, the full adder 30 outputs the current latch time data "T16" of the NE latch 28 to the A input terminal.
The time data "T1" inputted to the B input terminal is subtracted from the time data "T15", and the resulting data "T15" is applied to the NE latch 28 and latched (step SM ₃₀ ). Therefore
The NE latch 28 is latched with time data ("T15") that has been rewound by one address because the reverse rotation has started. Then proceed to step SM ₁₂ ,
As mentioned above, steps SM ₁₂ , SM ₁₄ , SM ₁₈ ,
SM ₂₀ , SM ₁₂ , etc. are repeated. If a match signal of "1" (matching the time data "T15") is output before the reverse switch 1B is operated to return to the up count, the step will start again.
From SM ₁₂ and SM ₁₃ , the process proceeds to the flowchart shown in FIG. 7B, and the rewinding process is subsequently executed. Then, for example, the data up to address 6 of the RAM 5 is rewound, and the reverse switch 1B is operated while the second musical tone _E3 is muted. Then, the reversal from down count to up count indicates that the step
Judgments are made in SM ₁₄ and SM ₁₅ , and the process proceeds to step SM ₁₆ , where the address register 7 is incremented by 1, and then reprocessing in the forward direction starting from step SM ₈ becomes possible. Therefore, the sound emission starts from the second musical tone _E3 .

Here, when the record switch 1C is turned on and the recording state is set, the recording state is determined when the step _SM18 is reached via steps _SM12 and _SM14 .
Proceed to step SM ₁₉ . Then, until the correction key is turned on next time, step SM ₂₀ ,
SM ₁₂ , SM ₁₄ , SM ₁₈ , SM ₁₉ , SM ₂₀ ,... are repeated. Then, while E ₃ is off, press the correction key (3rd
For example, if you turn on the key F ₃ ) to modify the musical tone G ₃ ,
This is determined at step _SM19 , and processing for moving to the recording state at step _SM21 is executed.

That is, in this step _SM21 , if address register 7 is incremented by -1, address 9 is set. The signal R is then temporarily set to "0", thereby causing the full adder 30 to continue to function as a subtracter as described above. Then, the full adder 30 inputs time data "T16" from the NE latch 28 to the A input terminal to the B input terminal.
Subtract time data “T1” from address 9 of RAM5, and apply the subtraction result data “T15” to NE latch 2.
Latch it to 8. Then the signal R becomes “1” again.
Transfer gate group 1 is returned to
The time data "T15" from the NE latch 28 is latched to the PR latch 11 through the PR latch 3. Then, the signal CH is returned to the normal "0", and the subtracter 14 outputs the up/down counter 1 to the A input terminal.
7 count value data, that is, the corrected third musical note F ₃
A subtraction operation is executed to subtract the time data "T15" inputted to the B input terminal from the key-on count value data, and thereby a new key-off time of the second musical tone is obtained and written to address 9 of RAM5. be included. Then, return to step RM ₅ in Figure 4 and step 3.
The above-mentioned corrective recording operation for musical tones and below becomes possible.

Note that step SM ₂₆ in FIG. 7B is performed during rewinding.
This process is performed when a key release code is read out from the RAM 5, and the musical tone of the key corresponding to the key release code can be reproduced and emitted for the time data of the previous address.

In step _SM12 of FIG. 7A, when the coincidence signal of "1" is not output, if the reverse switch 1B is operated to reverse the state, for example from up-count to down-count, this will be detected at step _SM14 . , SM ₁₅ , and then proceeds to step SM ₁₇ where the address register 7 is set to -
1 and the rewinding process is performed, and then the process proceeds to step _SM27 , where the above-mentioned rewinding operation becomes possible. On the other hand, when reversing from down counting to up counting, steps SM ₁₄ and SM ₁₅
The rewind operation is determined, and the process proceeds to step _SM16 , where the address register 7 is incremented by 1, and then playback processing in the forward direction starting from step _SM8 becomes possible.

The process of independently reproducing and emitting only the melody information (Fig. 8) in the second channel of the RAM 5 is the same as the case of the first channel described above, and in the case of this second channel, the complete pause is first performed. Since the time data "T16" of the note is read out, the rest state continues for twice the time of the first channel from the start of playback.

Next, referring to the flowchart of FIG. 7C, the operation of processing for simultaneously starting reproduction of the two melodies of the first channel and the second channel will be explained.
In this case, the play switch 1G is turned on. At this time, the process of switch S ₁ is executed, and address register 7 is set to 1, which is the starting address plus 1 address.
The street address is set. Next, in step _S2 , the first
Time data "T8" and "T16" are read from addresses 1 of the channel and the second channel, respectively, and are latched to each NE latch 28 via each full adder 30 (switch S ₃ ). And the CPU has signal FF
is set to "1" to open the transfer gate 36, and the fastest signal outputted from the output terminal Hi of the tempo oscillator 18 is taken out as the fastest clock and applied to the up/down counter 17. As a result, each counter 17 executes the fastest up-counting operation (switch S ₄ ), and also executes the process of determining whether or not a coincidence signal of "1" has been output (switch S ₅ ). When the count value data of each counter 17 reaches the time data "T8" from the start of reproduction, first, a coincidence signal of "1" is output in the first channel, and this is determined and the process proceeds to step _S6 . , the signal FF is set to "0", and the counting operations of the counters 17 of each channel are temporarily stopped. and switch
Proceeding to S ₇ , in each subtractor 38 of each channel,
The current count value data "T8" of the up/down counter 17 is subtracted from the time data "T8" and "T16" latched in each NE latch 28, respectively, and the resulting data "T0" and "T8" are obtained. respectively, the corresponding NE
Latch each latch 28 (switch S ₈ ).
Then, each address register 7 is incremented by +1 and address 2 is set for each channel (switch S ₉ ), and the process then proceeds to step S ₁₀ , where each counter 17 is set to output from one of the transfer gates 23, 24, and 25. Counting of clocks based on the tempo is started, and the process proceeds to step _SM12 , where normal playback processing operations are started. That is, when the first channel and the second channel are started to be played simultaneously by the above processing, in the present example, the first channel is fast-forwarded by the time of the first time data "T8", that is, The half rest in the first channel of the musical score shown in FIG. 9 is ignored by the fast-forward process, and reproduction of the first musical tone _C3 of the first channel is immediately started. The score in Figure 10 explains this situation. On the score, the melody in the first channel has no half rest, and in the melody in the second channel, the whole rest has been changed to a half rest. The state changes respectively. Therefore, when there is a song that starts from a rest, the rest of that song becomes invalid, no silence occurs, and the song becomes less difficult to listen to.

In the above embodiment, the melody information of a song with a rest is first recorded in each of the two channels of the RAM 5, and then the rest is ignored only when both channels are played back at the same time. We have made it so that one of the songs starts playing immediately, but when playing only that channel for each channel, if the song starts from a rest, it is now possible to skip the rest and play the sound immediately. You can also do this. In this case, if the first address of the memory is rest information, the data may be read from address "2". Furthermore, in the embodiment described above, the rest at the beginning of the song was skipped using the fast-forward function of the counter, but by comparing the time information of the rests of both channels, the shorter rest time is There is no problem in subtracting it from the information and reproducing it and skipping it. Also, the number of memory channels is 3.
Alternatively, the number of memories may be four or more.Of course, the number of memories is not limited to one, but may be plural.

〔Effect of the invention〕

As explained above, when starting automatic performance of a piece of music that starts from a rest, this invention ignores the rest or shortens the length of the rest. Even when performing automatic performance of a piece of music starting from , it is possible to realize an automatic performance device that starts generating musical tones immediately after receiving an instruction to start automatic performance.

[Brief explanation of drawings]

FIG. 1 is an overall circuit configuration diagram of an electronic musical instrument according to an embodiment of the present invention, FIG. 2 is a specific configuration diagram of a part of the switches in the keyboard switch section 1, and FIG. 1 is a detailed circuit diagram of the recording section 8. FIG. 4 is a flowchart of the melody information recording process, FIG. 4 is a storage state diagram of the melody information shown in FIG. 7 in the RAM 5, and FIG.
The figure is a storage state diagram of melody information in the first channel of the RAM 5, and FIG. 6 is a detailed circuit diagram of the playback section 9.
FIGS. 7A, B, and C are diagrams showing a flowchart of the reproduction process of the melody information, and FIG.
9 is a diagram showing the storage state of melody information in the second channel of the RAM 5. FIG. 9 is a diagram of musical scores showing the two songs recorded in the first channel and the second channel, and FIG. 10 is a diagram of each of the musical scores in FIG. It is a diagram of a musical score showing the state of each song that appears when the songs are played back at the same time. 1...Keyboard switch section, 1A...Reset switch, 1B (ASW)...Reverse switch (reversal switch), 1C...Record switch, 1D...
...End switch, 1E...Start switch,
1F ₁ ...1st channel designation switch, 1F ₂ ...
...Second channel designation switch, 1G...Play switch, 2...CPU, 3...Musical tone creation section, 4
...Location control section, 5...RAM, 6R, 6L...
Speaker, 7...address register, 8...recording section, 9...playback section, 11...PR latch, 14...
...Subtractor, 17...up/down counter, 18...
...Tempo oscillator, 19...Tempo volume, 2
1, 22, 26...flipflop, 28...
NE latch, 30...Full adder, 36...Transfer gate, 38...Subtractor, BSW...
Forward switch, CSW...tempo acceleration switch,
DSW: slow tempo switch, ESW: tempo switch, ESW: normal switch.

Claims (1)

[Claims] 1. A storage means for storing musical tone information, a reading means for sequentially reading out the musical tone information from the storage means, and automatic performance of a piece of music based on the musical tone information read by the reading means. an automatic performance means; a determination means for determining whether or not the musical tone information read by the reading means is information indicating a rest when the automatic performance means starts automatic performance of a piece of music; When the determining means determines that the musical tone information read by the reading means is information indicating a rest, the automatic performance is configured to automatically perform the musical piece while ignoring the musical tone information indicating the rest. An automatic performance device comprising: a control means for controlling the means; 2 storage means for storing musical tone information representing a first musical piece and musical tone information representing a second musical piece; reading means for sequentially reading out the musical tone information from the storing means; automatic performance means for automatically playing the first music piece and the second music piece based on the musical tone information; and when the automatic performance means starts automatic performance of the first music piece and the second music piece; Compare a first rest length indicating musical tone information expressing the first musical piece read by the reading means and a second rest length indicating musical tone information expressing the second musical piece. a control means for controlling the automatic performance means to automatically perform the first music piece and the second music piece by shortening the rest processing by a time corresponding to musical tone information indicating a shorter rest length; An automatic performance device characterized by comprising the following.