JPH045218B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an address translation method, and particularly to an address translation method suitable for vector operations in a virtual memory method.

[Conventional technology]

In recent years, the need for ultra-high-speed scientific and technological computers (supercomputers) has been increasing for weather prediction, simulation in the nuclear field, image processing in the resource exploration field, and the like.

Supercomputers mainly perform so-called vector operations in which the same operation is performed on each set of a large amount of data arranged in an array. Each element in an array is stored in the main memory, which is relatively slow, and is divided into rows, columns, and pairs according to the start address of the array element (B) and the distance between elements (D). The data is read out to the processing device at regular intervals in the angular direction (B+iD) (i is an integer) and stored at the same or different address after arithmetic processing. Since the array data handled is generally larger than the capacity of the main memory, we use a so-called virtual memory method that converts logical addresses on the program into real addresses according to an address conversion table and accesses the main memory. It is common to take

In order to perform address translation at high speed, many devices are equipped with an address translation buffer (hereinafter abbreviated as translation buffer) to hold a copy of the address translation table stored in the main memory. In order to improve the performance of a processing device that performs vector operations, it is important to have access to the main memory that is commensurate with the internal processing speed.

Conventionally, this type of address conversion method performs multiple main memory accesses at the same time by providing multiple conversion sets for each access, reading address conversion data for multiple pages simultaneously, and performing main memory accesses over multiple pages. By processing the data simultaneously, the data throughput with the main memory device is improved.
Publication No.).

[Problem that the invention seeks to solve]

Such a conventional configuration has the disadvantage that it requires an increased amount of hardware because it includes a plurality of conversion sets. In addition, conventionally, other address translation methods of this type aim to achieve costs close to those described above with a small amount of hardware by dividing the translation set and interleaving the accesses. had the disadvantage that it could only perform one address translation.

The purpose of the present invention is to focus on the fact that in vector operations, accesses that must be processed simultaneously span several consecutive pages in the same direction, and to enable simultaneous address conversion of several consecutive pages using less hardware. The purpose of this invention is to provide an address translation method.

[Means and actions for solving problems]

The system of the present invention divides a program-accessible logical address space into subspaces according to the upper S bits of the logical address, and each subspace is equally divided into pages according to successive M bits and N bits. 2 S including 2 N conversion buffers storing part or all of 2 M address conversion data for the page having the same N bit contents corresponding to each subspace.
at least one arithmetic unit that adds or subtracts "1" from the contents of the M bits; a first address adjustment circuit that generates a first switching signal; and a first address adjustment circuit that receives either the contents of the M bits or the output of the arithmetic unit in response to the first switching signal to adjust each conversion of each conversion set. a first switch corresponding to the conversion buffer, which is used as a search address for the buffer; and a second switch, which generates a second switching signal corresponding to each conversion buffer based on at least the contents of the S bit, M bit, and N bit. and a second switch for switching the converted address from each of the conversion sets corresponding to each of the conversion buffers in response to the second switching signal, The present invention is characterized in that the real page addresses for 2N consecutive pages from the page are obtained all at once.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. This embodiment includes an address register 1, an access direction information register 2, an arithmetic unit 3, a first address adjustment circuit 4, and a second address adjustment circuit 4. Adjustment circuit 5
, four first switching circuits 50, 51, 52 and 53, and four conversion buffers 60, 61, 62,
and 63 as one set, and
4 conversion buffers 70, 71, 72, and 73
The address conversion set 7 is composed of one set, and four second switching circuits 80, 81, 82, and 83.

Address register 1 can now specify 2 to ¹⁸ logical addresses that can be set on the program.
An 18-bit logical address signal is configurable by a processing unit (not shown). The 1st bit, 5th bit, 2nd bit, and 10th bit from the higher order of the logical address signal represent a subspace number S, a first page number M, a second page number N, and an intra-page address A, respectively. In other words, the logical address space consists of two subspaces (hereinafter referred to as the first
(referred to as a subspace and a second subspace), one subspace is divided into 128 pages, and one page is further divided into 1024 addresses.

A subspace is designated by a subspace number S,
Address translation set 6 stores address translation data for the first subspace, and address translation set 7 stores address translation data for the second subspace. That is, address translation set 6 and address translation set 7 have subspace number S.
corresponds to the subspace where is "0" and "1".

A page is designated by a first page number M and a second page number N, and conversion buffers 60, 61,
Each of 62 and 63 stores address translation data of M multipliers of 2 for the same page N in the first subspace, and converts the translation buffer 7
0, 71, 72 and 73 are 2 for pages with the same N in the second subspace.
M multiplier address translation data is stored. That is, the conversion buffers 60 and 70 convert the page group (consisting of 32 pages) whose second page number N is "0", and the conversion buffers 61 and 71 convert the page group whose second page number N is "1". , conversion buffers 62 and 72 correspond to a page group whose second page number N is "2," and conversion buffers 63 and 73 correspond to a page group whose second page number N is "3."

FIG. 2 shows the relationship between logical addresses and real addresses in this embodiment. A logical page number LP expressed by a subspace number S, a first page number M, and a second page number N is converted into a real page number RP, and this real page number RP and intra-page address A (logical (identical to that of the address) allows direct access to the main memory (not shown). By performing this address conversion, even though the main memory has a capacity of 32 pages, if you load the required 32 pages or less into the main memory at the same time, the program will be able to load each page as if each The data can be treated as if there were two subspaces each consisting of 128 pages.

The address conversion data for performing the above address conversion, along with programs and data, are
Stored in main memory. 32 pieces of address translation data having the same second page number N of the address translation data for the first subspace of the address translation data are stored in translation buffers 60, 61, 62, and 63, each consisting of a high-speed memory. Address translation set 6 is preloaded from main memory. Similarly, the address conversion data for the second subspace is also transferred to the conversion buffers 70, 7.
1, 72 and 73 are preloaded into address translation set 7.

Now, the processing unit reads and decodes the instructions in the main memory according to the program, reads the operand data, performs arithmetic processing, and then stores the result of the operation in the main memory if necessary. Perform processing. In the process of processing these data, the address conversion described above is performed every time it is necessary to access the main memory.

In the case of vector operations, the target data for the same operation often spans multiple pages, so the processing device sets the first logical address signal of the elements to be accessed all at once in the address register 1, and
Access direction information is set in the access direction information register 2. The access direction information is subjected to address translation along with the page specified by the subspace number S, the first page number M, and the second page number N among the logical address signals set in the address register 1. Used to specify the page that should be displayed.

Figures 3-1 and 3-2 are diagrams to help you understand this. Figure 3-1 shows the case where the access direction information is positive, and Figure 3-2 shows the case where the access direction information is negative. corresponds to each.
Numbers 0, 1 in Figures 3-1 and 3-2,
2 and 3 are the values of the second page number N, and in address translation set 6, translation buffers 60, 61, 62, and 63 correspond in order, and in address translation set 7, translation buffer 70 corresponds in order. , 71, 72 and 73 correspond. Further, symbols X-1, X, and X+1 indicate the value of the first page number M. number 0,
1, 2 or 3 and the symbol X-1, X or X+
The address designated by 1 is the address of the real page number for a particular page in each address translation set. The symbol LP indicates the logical page number of the first element to be accessed.
1", "LP+2", and "LP+3" represent four consecutive pages in ascending order, "LP", "LP-1", "LP-2",
and "LP-3" indicate four consecutive pages in descending order. X(0), X(1), X(2), and X(3) are the numbers 0,
1, 2 and 3 are shown.

In Figure 3-1, if a page with a second page number N of "2" is set in address register 1, and plus is set as access direction information in access direction information register 2, then the logical page number of the first element The actual page number for “LP” is X
From the address specified by "X" of the conversion buffer in (2), the real page number for the logical page number "LP+1" is X (3) From the address specified by "X" in the conversion buffer, the logical page number " LP+2”
From the address specified by "X+1" of the conversion buffer where the real page number for logical page number "LP+3" is X (0), the real page number for logical page number "LP+3" is
Indicates that data is read from the address specified by "X+1" of the conversion buffer in (1). The cases where the second page number N is "0", "1", and "3" are also easily understood from FIG. 3-1.

Fig. 3-2 differs from Fig. 3-1 in that each shows a case where negative access direction information is given. For example, if the second page number N is "1", four consecutive pages "LP", "LP-"
The actual page numbers for "1", "LP-2" and "LP-3" are "X" and "X" for conversion buffers X(1), X(0), X(3) and X(2), respectively. ”, “X-1”, and “X-1” indicate that the page is read from the address specified. The second page number N is “0”,
Similarly for cases of “2” and “3”,
This can be understood from Figure 3-2.

In the above explanation, whether address translation set 6 or address translation set 7 is used is determined by the subspace number S, but depends on the logical page number of the first element and the access direction. may cross subspace boundaries. The address conversion method in this case is the most distinctive feature of the present invention, and FIGS. 4-1 and 4-2 are diagrams to facilitate understanding. FIG. 4-1 corresponds to the case where the access direction information is positive, and FIG. 4-2 corresponds to the case where the access direction information is negative. In FIGS. 4-1 and 4-2, the values of S, M, and N indicate the values of the subspace number S, the first page number M, and the second page number N, respectively. X(0),X
(1), X(2) and X(3) are the values of N “0”, “1”,
Conversion buffers corresponding to "2" and "3" are shown.

In Figure 4-1, "0" is the value of the subspace number S, and 31 is the value of the first page number M.
However, if a page whose second page number N value is "2" is set in address register 1, and plus is set as access direction information in access direction information register 2, the logical page number of the first element is "LP". The actual page number for the conversion buffer 62
From the address specified by “31” in the conversion buffer 63, the real page for the logical page number “LP+1” is converted from the address specified by “31” in the conversion buffer 63, and the real page number for the logical page number “LP+2” is converted from the address specified by “LP+2” in the conversion buffer 70. This indicates that the real page number for the logical page number “LP+3” is read from the address specified by “0” of the conversion buffer 71 from the address specified by “0”. In other words, the real page numbers for logical page numbers "LP" and "LP+1" are translated by address translation set 6, and the real pages for logical page numbers "LP+2" and "LP+3" are translated by address translation set 7. The value of subspace number S is “0”
Also, when the value of the first page number M is "31" and the values of the second page number N are "0", "1", and "3", it is easy to understand from Figure 4-1. be understood.

FIG. 4-2 differs from FIG. 4-1 in that it shows a case where negative access direction information is given and four consecutive pages straddle the boundary of the subspace. For example, if "1" is the value of the subspace number S, "0" is the value of the first page number M, "1" is the value of the second page number N, and the access direction information is When a minus value is set in the access direction information register 2, the real page number for the logical page number "LP" of the first element is changed from the address specified by "0" of the conversion buffer 71 to the logical page number "LP-1". The real page number for the conversion buffer 70 is changed from the address specified by “0” to the logical page number “LP”.
The actual page number for “-2” is the conversion buffer 63
This indicates that the real page number for the logical page number "LP-3" is read from the address designated by "31" of the conversion buffer 62. In other words, the real page numbers for logical page numbers "LP" and "LP-1" are translated by address translation set 7, and the real page numbers for logical page numbers "LP-2" and "LP-3" are translated by address translation set 6. This indicates that the The value of subspace number S is “1”,
The case where the value of the first page number M is "0" and the values of the second page number N are "0", "2", and "3" is also easily understood from FIG. 4-2.

As explained above in Figures 4-1 and 4-2, even if the logical page numbers of four consecutive pages cross the boundary between the first subspace and the second subspace, the real page numbers will be changed all at once. will be obtained.

Referring again to FIG. 1, when the access direction information set in the access direction information register 2 is positive, the arithmetic unit 3 sets "1" to the value of the first page number M set in the address register 1. and when the access direction information is negative, the first
"1" is subtracted from the value of the page number M, and the results of these calculations are supplied to each of the first switching circuits 50, 51, 52, and 53.

The first address adjustment circuit 4 adjusts the response to the first switching circuits 50 to 53 based on the access direction information set in the direction information register 2 and the value of the second page number N set in the address register 1. A switching signal is generated and supplied to the first switching circuits 50-53. Each of the first switching circuits 50 to 53 selects and accepts the value of the first page number M and the value of the arithmetic unit 3 in response to this switching signal. The output of the first switching circuit 50 is supplied to conversion buffers 60 and 70, the output of the first switching circuit 51 is supplied to conversion buffers 61 and 71, and the output of the first switching circuit 52 is supplied to conversion buffers 62 and 72. The output of the first switching circuit 53 is supplied to conversion buffers 63 and 73.

In the conversion buffers 60 and 70, the real page number is read from the address specified by the output of the first switching circuit 50 and supplied to the second switching circuit 80. In the conversion buffers 61 and 71, the real page number is read from the address specified by the output of the first switching circuit 51 and supplied to the second switching circuit 81. In the conversion buffers 62 and 72, the first switching circuit 5
The real page number is read from the address specified by the output of 2 and is supplied to the second switching circuit 82. In the conversion buffers 63 and 73,
The real page number is read from the address specified by the output of the first switching circuit 53 and is supplied to the second switching circuit 83.

The second address adjustment circuit 5 receives the access direction information set in the access direction information register 2,
Subspace number S set in address register 1
, the value of the first page number M, and the value of the second page number N, the second switching circuits 80 to 80
83 and generates a switching signal corresponding to the second switching circuit 8.
Supply from 0 to 83.

In FIG. 5, the second switching circuits 80 to 8 are switched from the second address adjustment circuit 5 in the case where the subspace boundary is crossed.
3 shows the switching signal supplied to 3. In FIG. 5, Y ₀ , Y ₁ , Y ₂ and Y ₃ are sequentially connected to the second switching circuit 8.
This is a switching signal supplied to 0, 81, 82, and 83. If it is "0", it selects the real page number read from the translation buffer belonging to address translation set 6, and if it is "1", it selects the real page number read from the translation buffer belonging to address translation set 6. 7
Select the real page number read from the conversion buffer belonging to .

It can be easily understood that by supplying the signals shown in FIG. 5, the address conversion shown in FIGS. 4-1 and 4-2 is possible. In addition, when the subspace boundary is not crossed, if the value of the subspace number S is "0", the second address adjustment circuit 5
All outputs are “0”, and if the value of the subspace number S is “1”, the second address adjustment circuit 5
It is clear that the outputs of are all "1".

As described above, the second switching circuits 80 to 83
The real page numbers for the logical page numbers of four consecutive pages are read from the page.

In all the embodiments described above, the conversion buffer holds a copy of all the address conversion data in the address conversion table stored in the main memory. This includes those that hold copies of data.

〔Effect of the invention〕

According to the present invention, by employing the above-described configuration, pages for which address translation is to be performed are selected based on the access direction of the page and the first page, and multiple pages that are consecutive even across the boundaries of subspaces are address translation can be performed simultaneously with a small amount of hardware.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing one embodiment of the present invention, Fig. 2, Fig. 3-1, Fig. 3-2, Fig. 4-1.
4-2 and 5 are diagrams for explaining FIG. 1. 1... Address register, 2... Access direction information register, 3... Arithmetic unit, 4... First address adjustment circuit, 5... Second address adjustment circuit,
6, 7...Address conversion set, 50, 51, 5
3...first switching circuit, 60, 61, 62, 6
3, 64, 70, 71, 72, 73... conversion buffer, 80, 81, 82, 83... second switching circuit.

Claims (1)

[Claims] 1. Divide the program-accessible logical address space into subspaces based on the upper S bits of the logical address, and each subspace consists of successive M bits and N bits.
2, which stores part or all of 2 to the M power of address conversion data for the page, which is equally divided into pages according to bits, and has the same contents of the N bits corresponding to each partial space. 2 S conversion sets including N conversion buffers, at least one arithmetic unit that adds or subtracts "1" from the contents of the M bits, and at least one calculation unit based on the contents of the N bits. and the first one corresponding to each conversion buffer of each conversion set.
a first address adjustment circuit that generates a switching signal; and a first address adjustment circuit that receives either the contents of the M bits or the output of the arithmetic unit in response to the first switching signal, and supplies the address adjustment circuit to each conversion buffer of each conversion set. a first switch corresponding to the conversion buffer used as a search address; at least the S bit and the M bit;
a second address adjustment circuit that generates a second switching signal corresponding to each of the conversion buffers based on the contents of the N bits; and a second switch for switching the converted address of the address conversion method.