JPH0452483B2 - - Google Patents

Info

Publication number
JPH0452483B2
JPH0452483B2 JP58184067A JP18406783A JPH0452483B2 JP H0452483 B2 JPH0452483 B2 JP H0452483B2 JP 58184067 A JP58184067 A JP 58184067A JP 18406783 A JP18406783 A JP 18406783A JP H0452483 B2 JPH0452483 B2 JP H0452483B2
Authority
JP
Japan
Prior art keywords
signal
response
circuit
function
output signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58184067A
Other languages
Japanese (ja)
Other versions
JPS6075910A (en
Inventor
Yoshihisa Uchida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shimadzu Corp
Original Assignee
Shimadzu Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shimadzu Corp filed Critical Shimadzu Corp
Priority to JP58184067A priority Critical patent/JPS6075910A/en
Publication of JPS6075910A publication Critical patent/JPS6075910A/en
Publication of JPH0452483B2 publication Critical patent/JPH0452483B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B23/00Testing or monitoring of control systems or parts thereof
    • G05B23/02Electric testing or monitoring

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Testing And Monitoring For Control Systems (AREA)

Description

【発明の詳細な説明】 (イ) 産業上の利用分野 本発明はプロセス等の系のステツプ応答を検出
する装置に関する。
DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to an apparatus for detecting step responses of systems such as processes.

(ロ) 従来技術 一般に、プロセスを最適に制御する為には、そ
のプロセスの特性に応じて調節器のパラメータを
最適に設定しなければならない。プロセスの特性
を知る手段として、インパルス応答法、ステツプ
応答法、ランプ応答法および周波数応答法があ
る。これらの方法は、プロセスにそれぞれインパ
ルス信号、ステツプ信号、ランプ信号および正弦
波信号を加え、その応答曲線からプロセスの特性
を推定するものである。
(B) Prior Art Generally, in order to optimally control a process, the parameters of a regulator must be optimally set according to the characteristics of the process. There are impulse response methods, step response methods, ramp response methods, and frequency response methods as means for understanding process characteristics. These methods add an impulse signal, a step signal, a ramp signal, and a sine wave signal to the process, respectively, and estimate the characteristics of the process from the response curves.

これらのうち、インパルス応答法はプロセスの
安定を乱すことがないから最も好ましい方法であ
るといえるが、インパルス信号は理想化された、
観念的な信号であつて、物理的に実現不可能であ
るから実際には採用することができない。ランプ
応答法および周波数応答法は、プロセスの平衡を
乱すばかりでなく、応答曲線からプロセスの特性
を求める解析過程が極めて複雑であつて好ましい
方法とはいい難い。
Among these, the impulse response method is the most preferable method because it does not disturb the stability of the process, but the impulse response method is
Since it is an ideal signal and cannot be realized physically, it cannot be used in practice. The ramp response method and the frequency response method not only disturb the equilibrium of the process, but also have an extremely complicated analysis process for determining the process characteristics from the response curve, so they are not preferred methods.

ステツプ応答法に関しては、プロセスの動的特
性を容易に把握することができるので好ましい方
法ではあるが、ステツプ信号を加えることによつ
て、プロセスの平衡が乱されてしまう欠点を有す
る。すなわち、一般に、第1図に示す如く、プロ
セスの特性を伝達関数Gで表わし、このプロセス
にmなるステツプ信号を加えると、mGなるステ
ツプ応答を得るが、例えばこのプロセスの特性が
むだ時間Lを含む1次遅れ(ゲインR、時定数
T)であつたとすると、そのブロツク線図は第2
図の如く示すことができる。この場合、ステツプ
応答は mRe-Ls/1+Ts ……(1) となり、これを時間関数に変換すれば、 mR(1−e-t-L T) となつて、これを時間についてプロツトして表わ
した応答曲線を第3図に示す。このステツプ応答
曲線からR,T,Lを求めることができる。プロ
セスの調節器のPIDの調節値はR,T,Lの関数
で決められるから、直ちに最適調節値が設定でき
ることになる。ところが、このような1次遅れ系
のプロセスにmなるステツプ信号を加えると、ス
テツプ応答曲線は第3図から明らかなように、
mRだけ安定していた値から外れてしまうことに
なる。
The step response method is a preferred method because it allows the dynamic characteristics of the process to be easily grasped, but it has the disadvantage that adding a step signal disturbs the equilibrium of the process. That is, in general, as shown in Fig. 1, if the characteristics of a process are expressed by a transfer function G, and a step signal of m is added to this process, a step response of mG is obtained. If there is a first-order lag (gain R, time constant T) including
It can be shown as shown in the figure. In this case, the step response is mRe -Ls /1+Ts...(1), and if this is converted into a time function, it becomes mR(1-e -tL T ), and the response expressed by plotting this with respect to time is The curve is shown in Figure 3. R, T, and L can be determined from this step response curve. Since the PID adjustment value of the process controller is determined by a function of R, T, and L, the optimum adjustment value can be immediately set. However, when a step signal of m is added to such a first-order delay system process, the step response curve becomes as shown in Fig. 3.
This means that only mR deviates from the stable value.

(ハ) 目的 本発明の目的は、プロセスの特性を動的に把握
することのできるステツプ応答曲線を、プロセス
の安定を乱すことなく得ることのできる、ステツ
プ応答検出装置を提供することにある。
(C) Objective An object of the present invention is to provide a step response detection device that can obtain a step response curve that can dynamically grasp the characteristics of a process without disturbing the stability of the process.

(ニ) 構成 本発明の構成を第4図に示す機能的ブロツク線
図に基づいて説明する。
(d) Configuration The configuration of the present invention will be explained based on the functional block diagram shown in FIG.

第1の回路1は、1から1次遅れ関数を引いた
形の指数関数形信号m{Ls/(1+Ls)}を発生
する。第2の回路2は、第1の回路1の出力信号
の逆関数の形の伝達関数(1+Ls)/Lsを有し
ている。Gなる伝達関数を有する被測定系3に第
1の回路1の出力信号を加えると、その応答信号
はm{Ls/(1+Ls)}Gとなつて時間とともに
元の平衡状態に戻るが、その応答信号は第2の回
路2を通過させられ、mGなる信号となつて被測
定系3にステツプ信号mを加えた場合と同等の応
答曲線を得る。
The first circuit 1 generates an exponential function signal m{Ls/(1+Ls)} in the form of 1 minus the first-order lag function. The second circuit 2 has a transfer function (1+Ls)/Ls in the form of an inverse function of the output signal of the first circuit 1. When the output signal of the first circuit 1 is applied to the system under test 3 having a transfer function G, the response signal becomes m{Ls/(1+Ls)}G and returns to the original equilibrium state over time. The response signal is passed through the second circuit 2, becomes a signal mG, and obtains a response curve equivalent to when a step signal m is applied to the system under test 3.

(ホ) 実施例 本発明の実施例を、以下、図面に基づいて説明
する。
(e) Examples Examples of the present invention will be described below based on the drawings.

第5図は本発明実施例の構成を示すブロツク図
である。
FIG. 5 is a block diagram showing the configuration of an embodiment of the present invention.

指数関数形信号発生回路11は、ステツプ信号
発生回路11aと1次遅れ要素(時定数L)11
bとから構成され、1次遅れ要素11bはステツ
プ信号発生回路11aの出力信号mを入力してそ
の出力を信号mに負帰させている。従つて、この
指数関数形信号発生回路11の出力信号bは、1
次遅れ要素11bの出力信号をaとすると、 b=m−a となつて、 a−m1/1+Ls であるから、 b=m(1−1/1+Ls)=mLs/1+Ls ……(2) となる。
The exponential function signal generation circuit 11 includes a step signal generation circuit 11a and a first-order delay element (time constant L) 11.
The first-order delay element 11b inputs the output signal m of the step signal generation circuit 11a, and causes the output to be negatively applied to the signal m. Therefore, the output signal b of this exponential function signal generation circuit 11 is 1
If the output signal of the next delay element 11b is a, then b=m-a, and a-m1/1+Ls, so b=m(1-1/1+Ls)=mLs/1+Ls...(2) Become.

ステツプ応答を検出すべきプロセスWには、こ
の(2)式で表わされる信号が入力される。そしてそ
の応答信号cは、指数関数形信号発生回路11の
出力信号bの逆関数の形の伝達関数(1+
Ls)/Ls、すなわち、ゲイン1、積分時間Lを
有するPI制御器12に入力されるよう構成され
ている。
The signal expressed by equation (2) is input to the process W that is to detect the step response. The response signal c is a transfer function (1+
Ls)/Ls, that is, it is configured to be input to a PI controller 12 having a gain of 1 and an integration time L.

なお、指数関数形信号bの発生は、具体的には
例えばステツプ信号mを進相回路を通過させるこ
とによつて得ることができる。
Note that the exponential function signal b can be specifically generated by passing the step signal m through a phase advancing circuit, for example.

以上の本発明実施例によると、例えばステツプ
応答を検出すべきプロセスWの特性が第5図に示
すようなむだ時間Lを含む1次遅れ(ゲインR、
時定数T)であつたとすると、その応答信号c
は、 c=b・Re-Ls/1+Ts となり、(2)式より、 c=1Ls/1+Ls・Re-Ls/1+Ts ……(3) となる。この信号cは、指数関数Ls/(1+
Ls)、すなわち、時間関数で表現するとe-t/Lが乗
ぜられているから、プロセスWの伝達関数がどの
ような関数であつても時間tの経過とともにその
値は0に、すなわち元の安定値に近づく為、プロ
セスWの安定は乱されない。
According to the embodiments of the present invention described above, for example, the characteristics of the process W in which the step response is to be detected are the first-order lag (gain R,
time constant T), the response signal c
is c=b・Re -Ls /1+Ts, and from equation (2), c=1Ls/1+Ls・Re -Ls /1+Ts ...(3). This signal c is an exponential function Ls/(1+
Ls), that is, when expressed as a time function, it is multiplied by e -t/L , so no matter what kind of function the transfer function of process W is, as time t passes, its value becomes 0, that is, the original Since it approaches a stable value, the stability of process W is not disturbed.

この応答信号cを、PI制御器12を通過させ
ることによつて得られる信号dは、 d=c・1+Ls/Ls となるから、(3)式より、 d=mLs/1+Ls・Re-Ls/1+Ts・1−Ls/Ls =mRe-Ls/1+Ts ……(4) となる。すなわち、信号dは、前述の(1)式より明
らかなように、プロセスWにステツプ信号mを加
えたときの応答信号と同等の信号となり、この
PI制御器12の出力信号dの形からプロセスW
の動的特性を把握することができる。
The signal d obtained by passing this response signal c through the PI controller 12 is d=c・1+Ls/Ls, so from equation (3), d=mLs/1+Ls・Re -Ls / 1+Ts・1-Ls/Ls=mRe -Ls /1+Ts...(4) In other words, as is clear from equation (1) above, the signal d becomes a signal equivalent to the response signal when the step signal m is added to the process W, and this
From the shape of the output signal d of the PI controller 12, the process W
It is possible to understand the dynamic characteristics of

なお、本発明の応用として、プロセスW′の特
性が積分性の場合には、第6図にそのブロツク線
図を示す如く、出力信号を2次の指数関数とすれ
ばよい。このとき、プロセスW′の応答信号は2
連のPI制御器12′を通すことによつて、プロセ
スW′のステツプ応答me-Ls/Tsを得る。なお、
2次の指数関数形信号m{Ls/(1+Ls)}2は、
前述の指数関数発生回路11の後段に、更に1次
遅れ要素11bを同様な接続で追加することによ
つて発生することができる。
In addition, as an application of the present invention, when the characteristic of the process W' is integral, the output signal may be made into a quadratic exponential function, as shown in the block diagram of FIG. At this time, the response signal of process W′ is 2
The step response me -Ls /Ts of process W' is obtained by passing it through a series of PI controllers 12'. In addition,
The second-order exponential function signal m{Ls/(1+Ls)} 2 is
This can be generated by further adding a first-order lag element 11b in a similar connection after the exponential function generating circuit 11 described above.

(ヘ) 効果 以上説明したように、本発明によれば、被測定
系への出力信号を指数関数形にして、その応答信
号を出力信号の逆関数形の要素を通すことによ
り、被測定系のステツプ応答と等しい信号を得る
よう構成したので、被測定系の安定を乱すことな
く、そのステツプ応答を検出することができる。
その検出結果から直ちに被測定系の特性(ゲイ
ン、時定数、むだ時間)を得て、最適調節値を決
定して最適な制御を行うことができる。
(f) Effects As explained above, according to the present invention, the output signal to the system under test is made into an exponential form, and the response signal is passed through an element of the inverse function form of the output signal. Since the structure is configured to obtain a signal equal to the step response of , the step response can be detected without disturbing the stability of the system under test.
The characteristics of the system to be measured (gain, time constant, dead time) can be immediately obtained from the detection results, and the optimum adjustment values can be determined to perform optimum control.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はプロセスにステツプ信号を加えた場合
の一般的なブロツク線図、第2図は、むだ時間を
含む1次遅れのプロセスにステツプ信号を加えた
場合のブロツク線図、第3図はその応答曲線を示
すグラフ、第4図は本発明の構成を示す機能的な
ブロツク線図、第5図は本発明実施例の構成を示
すブロツク図、第6図はその応用例を示すブロツ
ク線図である。 11……指数関数形信号発生回路、11a……
ステツプ信号発生回路、11b……1次遅れ要
素、12……PI調節器。
Fig. 1 is a general block diagram when a step signal is added to a process, Fig. 2 is a block diagram when a step signal is added to a first-order delay process including dead time, and Fig. 3 is a general block diagram when a step signal is added to a process. A graph showing the response curve, FIG. 4 is a functional block diagram showing the configuration of the present invention, FIG. 5 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 6 is a block diagram showing an example of its application. It is a diagram. 11...exponential function signal generation circuit, 11a...
Step signal generation circuit, 11b...1st order delay element, 12...PI controller.

Claims (1)

【特許請求の範囲】[Claims] 1 1から1次遅れ関数を引いた形の指数関数形
信号を発生する第1の回路と、その第1の回路の
出力信号の逆関数の形の伝達関数を有する第2の
回路を備え、ステツプ応答を検出すべき系に上記
第1の回路の出力信号を加えるとともにその応答
信号を上記第2の回路に通し、上記第2の回路の
出力から当該系のステツプ応答曲線を得るよう構
成されたステツプ応答検出装置。
1. A first circuit that generates an exponential function signal in the form of 1 minus a first-order lag function, and a second circuit that has a transfer function in the form of an inverse function of the output signal of the first circuit, The system is configured to apply the output signal of the first circuit to a system in which a step response is to be detected, pass the response signal to the second circuit, and obtain a step response curve of the system from the output of the second circuit. Step response detection device.
JP58184067A 1983-09-30 1983-09-30 Step answer detector Granted JPS6075910A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58184067A JPS6075910A (en) 1983-09-30 1983-09-30 Step answer detector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58184067A JPS6075910A (en) 1983-09-30 1983-09-30 Step answer detector

Publications (2)

Publication Number Publication Date
JPS6075910A JPS6075910A (en) 1985-04-30
JPH0452483B2 true JPH0452483B2 (en) 1992-08-24

Family

ID=16146798

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58184067A Granted JPS6075910A (en) 1983-09-30 1983-09-30 Step answer detector

Country Status (1)

Country Link
JP (1) JPS6075910A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4766524A (en) * 1986-02-07 1988-08-23 Hitachi, Ltd. Back light device for uniformly illuminating a liquid crystal display plate

Also Published As

Publication number Publication date
JPS6075910A (en) 1985-04-30

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