JPH0452513A - High-speed thermal waveform recorder - Google Patents

Abstract

PURPOSE:To enable prevention of deterioration of reproducibility of a recording waveform at a rise time when high-speed paper feeding is set, by a method wherein an address of data writing in a memory is generated in accordance with a data sampling signal an address of data reading from the memory is generated synchronously with a recording period of a thermal line head. CONSTITUTION:To an arbiter 14, a sampling signal S1 is inputted from an A/D converter 6, a record sync signal S2 synchronizing with a motor drive pulse is inputted from a thermal head control circuit 13 and, moreover, a system clock CLK is inputted. The circuit 14 outputs a read/write signal S3 to an OE end terminal of a buffer 7, outputs a signal S3 to a R/W terminal of a memory 8 and outputs a chip select signal S4 to a CS terminal. Next, it outputs the signal S3 to an SEL terminal of a data selector 9, a count increment signal S5 to a CLK terminal of a ring counter 10, a count increment signal S6 to a CLK terminal of a ring counter 11, and the signal S3 to a G terminal of buffer 12 through an inverter 15.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a high-speed waveform recording device using a thermal line head, and more particularly to improving the reproducibility of a recording waveform at the start of recording paper feeding.

<Prior Art> FIG. 4 is a schematic diagram of a waveform recording device using a thermal line head. In the figure, motor 1 is connected to pulley 2
The platen 3 is rotated via the , and the thermal recording paper 4 is sent out. The thermal line head 5 is disposed at a position facing the platen 3 so as to sandwich the thermal recording paper 4 and to be orthogonal to the feeding direction of the thermal recording paper 4.

In such a waveform recording device, a moment of inertia exists in the platen 3, and a frictional force exists between the platen 3, the thermal recording paper 4, and the thermal line head 5.

Therefore, in order to instantly increase the feeding speed of the recording paper 4 to a high-speed paper feeding state of 200 mm/s, the motor 1 needs a large torque.

Incidentally, a stepping motor is generally used as the motor 1 for feeding the recording paper.

However, it is impossible for a stepping motor to start up at a frequency higher than its self-starting range. Therefore, slow-up control is used to gradually accelerate the paper feed speed to the set paper feed speed.

<Problems to be Solved by the Invention> However, when a signal of a constant frequency is recorded while performing slow-up control of the recording paper feed, at the start of recording, the feeding speed of the recording paper 4, that is, the stepping motor 1
Since the feeding cycle is relatively slow with respect to the one-line recording cycle of the thermal line head 5, the recording result becomes dense as shown in FIG.

FIG. 6 is an explanatory diagram of recording timing in such a conventional apparatus. In the figure, the sampling period shown in (A) and the recording period shown in (B) have a one-to-one correspondence. On the other hand, since the cycle of the motor drive pulse shown in (C) is slow-up controlled, the cycle near the recording start point is long. As a result, two lines of C will be recorded during the recording period while the recording paper 4 is fed one step by motor drive pulses 1- and 2-.

Specifically, when performing real-time recording while waiting for a trigger, the reproducibility of the recording waveform near the trigger when high-speed paper feed is set is significantly degraded.

One way to solve this problem is to load the measured data into memory and then record the waveforms at low speed in batch processing (1), but the memory capacity is limited and long-term recording is not possible. It's impossible.

The present invention has been made with attention to these points,
The purpose is to provide a high-speed thermal waveform recording device in which the reproducibility of recording waveforms does not deteriorate even at the start-up when high-speed paper feed is set, and the number of measurement data is not limited.

<Means for Solving the Problems> The present invention, which solves the above problems, provides a device that performs high-speed waveform recording using a thermal line head, which includes a memory for temporarily storing sampled measurement data, and a memory that temporarily stores sampled measurement data, and a device that performs high-speed waveform recording using a thermal line head. a first ring counter that counts up and generates an address for writing data to the memory; and a second ring that counts up in synchronization with a recording cycle of the thermal line head and generates an address for reading data from the memory. a counter; an arbitration unit that arbitrates the timing of writing data to the memory and reading data from the memory; a buffer that latches data written to the memory; and a buffer that latches data read from the memory. It is characterized by the following:

<Operation> According to the high-speed thermal waveform recording device of the present invention, a data write address to the memory is generated according to the pig sampling signal, and a data read address from the memory is generated in synchronization with the recording cycle of the thermal line head.

As a result, there is a one-to-one correspondence between the feeding period of the recording paper and the recording period of the thermal line head, and it is possible to prevent deterioration of the reproducibility of the recording waveform at the start-up when the high-speed paper feeding is set.

<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, for example, waveform data sampled by an A/D converter 6 is temporarily latched in a buffer 7. The waveform data latched in the buffer 7 is input to the D terminal of the memory 8 via the data bus DB. In addition, G of buffer 7
A sampling signal S1 is input from the A/D converter 6 to the terminal. The count value of a ring counter 10 or the count value of a ring counter 11 is input to the A terminal of the memory 8 via a data selector 9. Data read from the memory 8 is temporarily latched in the buffer 12 via the data bus DB, and is input to the thermal head control circuit 13.

Motor drive pulses are also manually input to the thermal head control circuit 13. The operation timing of each of these parts is arbitrated by an arbitration circuit 14. The arbitration circuit 14 receives the sampling signal S1 from the A/D converter 6, receives the recording synchronization signal S2 synchronized with the motor drive pulse from the thermal head control circuit 13, and also receives the system clock CL.
K is input. The arbitration circuit 14 outputs a read/write signal S3 to the OE terminal of the buffer 7, and outputs the read/write signal S3 to the OE terminal of the buffer 7.
A read/write signal S3 is output to the R/W terminal of C8.
A chip select signal S4 is output to the terminal, a read/write signal S3 is output to the SEL terminal of the data selector 9, a first count-up signal S5 is output to the CLK terminal of the ring counter 10, and the ring counter 1] CLK of
A second count-up signal S6 is outputted to the terminal, and a read/write signal S3 is outputted to the G terminal of the buffer 12 via an inverter 15.

FIG. 2 is a schematic explanatory diagram of recording timing in the apparatus of FIG. 1. In the figure, the recording period shown in (B) is (A
There is no one-to-one temporal correspondence with the sampling period shown in ), but there is a one-to-one correspondence with the motor drive pulse shown in (C).

FIG. 3 is a timing chart illustrating the timing relationship of each part in FIG. 1.

Time t. It is assumed that a recording start trigger is input. During cycle 1, data a is sampled as shown in (A). The data a is the sampling signal S1 (for example, E of the A/D converter) at the end of cycle 1 shown in (B).
OC) and is latched into the buffer 7 (xl) as shown in (C).

On the other hand, since the sampling signal S1 is also input to the arbitration circuit 14, the arbitration circuit 14 inputs (D
) is output (x2).

As a result, the ring counter 10 increments the count value (X,) as shown in (E).

In cycle 2, the count value of the ring counter 10 is selected by the data selector 9 and input as an address to the memory 8 as shown in (K) (X4). At the same time (L
), the chip select signal S4 becomes active, and data a is written to address "1" of the memory 8 (x5).

During cycle 2, the first driving pulse of the motor is generated as shown in (F), and the recording paper is fed by one step (x6). Since the recording synchronization signal S2 synchronized with the drive pulse is input from the thermal head control circuit 13 to the arbitration circuit 14, the arbitration circuit 14 inputs (
Output the count-up signal S6 shown in G) (X7)
. This causes the ring counter 11 to change the count value to (H).
Increment as shown in (X8). Arbitration circuit 1
4 is the fall of the count-up signal S6, and as shown in (I), the read/write signal S3 is temporarily set to the read side (
x9). As a result, the count value of the ring counter 11 is selected by the data selector 9 and inputted to the memory 8 as an address (X+O). At the same time, chip select signal S4 becomes active (X11), and data a is read from address "1" of memory 8 (X,
)(J), it is latched in the buffer 12 (X
+2). Pig a latched in the buffer 12 is applied to the thermal head control circuit 13 and a recording operation is executed.

Similar operations are repeated in cycle 3 and beyond. That is,
The count value of the ring counter 10 is incremented by the sampling signal S1 and the count value is stored in the memory 8.
Write the sampling data as the address. Then, the count value of the ring counter 11 is incremented by a recording synchronization signal S2 synchronized with the motor drive pulse, and data is read out from the memory 8 using the count value as an address of the memory 8 for recording.

With this configuration, the sampling data is written to the memory 8 at an appropriate timing, read out from the memory 8 at an appropriate timing, and recorded at the timing shown in FIG. 2.

Incidentally, the arbitration circuit 14 also has a function of arbitrating read/write of the memory 8 when the sampling signal S1 and the motor drive pulse are generated simultaneously.

In other words, the data sampling period is several 100 μs, whereas the access time of the memory 8 is several 100 ns.
Therefore, arbitration can be performed by executing processing in synchronization with a system clock of approximately several MHz.

Further, each ring counter 10, 11 returns to 0 after a full count (for example, FFFFh), and repeats the operation until the end of recording. After the recording paper feed speed reaches a steady speed, the data sampling interval and motor drive pulse period become the same, so the discrepancy in the count values of each ring counter 10 and 11 is due to the discrepancy that occurred until the motor reached a constant speed. Become. This discrepancy does not increase no matter how long the recording time becomes.

Therefore, if the number of bits of each ring counter 10 and 11 is secured for the number of counts necessary for the motor startup operation, the count value of ring counter 10 will not exceed the count value of ring counter 11. Each of these ring counters 10 and 11 is reset by a main sequencer (not shown) at the start of recording. After the recording is completed, data sampling is stopped and recording is continued until the count value of the ring counter 10 and the count value of the ring counter 11 become equal, so that all data is recorded.

In the above-described embodiment, an example in which a dedicated memory is used as the memory has been described, but for example, an acquisition memory used for memory mode recording may be used instead. in this case,
Arbitration circuit and data selector functions are integrated into the main CPU and DM.
It can also be realized using an A controller or the like.

<Effects of the Invention> As described in detail above, according to the present invention, since the recording cycle and the motor drive pulse cycle match, it is possible to eliminate disturbances in the recording results immediately after the start of recording paper feeding during high-speed recording paper feeding. I can do it.

Further, even if the stepping motor is started up by slow-up control, there is no disturbance in the recording results, so there is no need to use a motor with a large torque and a high self-starting frequency, and the apparatus can be made smaller.

Furthermore, since the memory is accessed using the count value of the ring counter as an address, there is no restriction on recording length as in the memory mode, and continuous real-time recording can be performed as long as the thermal recording paper lasts.

In reality, the time for temporary storage in the memory is delayed, but the motor start-up time is within 1 second at the latest, and the discrepancy between data sampling and recording is within this range, so there is no practical problem.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a schematic explanatory diagram of recording timing in the apparatus of FIG. 1, and FIG. 3 is a timing chart explaining the timing relationship of each part of FIG. 1. FIG. 4 is a schematic configuration diagram of a waveform recording apparatus using a thermal line head, FIG. 5 is a diagram of conventional recording, and FIG. 6 is an explanatory diagram of recording timing in the conventional apparatus. 6... A/D converter 7, 12... Buffer 8.
...Memory 9...Data selector 10.1
1...Ring counter 13...Thermal head control circuit

Claims (1)

[Claims] A device that performs high-speed waveform recording using a thermal line head, comprising: a memory that temporarily stores sampled measurement data; and a memory that counts up in synchronization with data sampling and sets a data writing address to the memory. a first ring counter that generates data; a second ring counter that counts up in synchronization with the recording cycle of the thermal line head and generates an address for reading data from the memory; A high-speed thermal waveform recording device comprising: an arbitration unit that arbitrates the timing of reading data from the memory; a buffer that latches data written to the memory; and a buffer that latches data read from the memory. .