JPH0452560B2 - - Google Patents

Description

Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to a history information recording method for a central processing unit using a pipeline system, and in particular, history information is recorded only when each state of the pipeline is valid. The present invention relates to a history information recording compression method that compresses the record of history information by recording only the number of cycles during the invalid period when all states of the pipeline are invalid.

(b) Problems with the prior art The history information recording method in the central processing unit using the conventional pipeline method writes the history information to the memory regardless of whether each state of the pipeline is valid or invalid. , the data is written in synchronization with the clock, and invalid data of each state is written when all states of the pipeline are invalid, which is not required for maintenance work or the like.

Therefore, unnecessary data is written in a memory with a limited capacity, and there is a drawback that necessary data is insufficient.

(c) Purpose of the Invention The purpose of the present invention is to eliminate the above-mentioned drawbacks by writing various data into the history information recording memory only when each state of the pipeline is valid, and when all states of the pipeline are invalid. The object of the present invention is to provide a history information recording compression method that allows the connection of the pipeline to be recognized in the conventional manner by writing the number of cycles in the hot period.

(d) Configuration of the Invention The configuration of the present invention is that in a central processing unit using a pipeline system, when each state of the pipeline is valid V1, V2, ...), data of the valid state of the pipeline (DATA1, V2, ...) is processed. 2, 3,
~) 9 into the memory 10 (means 11, 12,
13, 17, and means 14, 15, 16 for writing into the memory 10 the number of cycles CRT9 during a period in which all states of the pipeline are invalid, so that the record of history information is compressed and recorded. It is something.

(e) Embodiment of the invention FIG. 1 is a circuit block diagram showing an embodiment of the invention. FIG. 2 is a time chart explaining the operation of FIG. 1.

In FIG. 1, registers 1, 2, 3, and 4 are valid signals V in each state of the pipeline.
1, V2, V3, and V4 are stored, respectively.
In addition, registers 5, 6, 7, and 8 contain the above V1, V2, and V of each state of each pipeline.
3. Various data synchronized with the V4 signal are stored. As shown in the OR circuit 17, each output of the registers 1, 2, 3, and 4 passes through the OR circuit 17 to the counter CTR 14, the adder 13, and the gate.
Enter WE12.

Also, each output of registers 1, 2, 3, and 4 is
Enters the NOR circuit 16, passes through the adder 15, increments the counter CTR14, and increments the counter CTR14.
Add “+1” to the count value. This circuit counts the number of cycles at the clock speed when all states of the pipeline are invalid. The count value of the counter CTR 14 is stored in the "CTR" section of the write register 9 with a delay of one clock.

In the time chart in Figure 2, counter 1
4, the value of the counter 14 is n
, the pipeline valid signal V
1, V2, V3, and V4, it becomes n+1 at the next clock. The output of the OR circuit 17 functions as a signal to reset the counter CTR14, and when a valid signal of a certain state of the pipeline, for example V1, is input, the counter CTR1
4 is reset.

Therefore, as long as the period in which all states of the pipeline are invalid continues, the "CTR" section of the write register 9 records the number of cycles by counting the period at the clock speed. {“Register 9CTR” in the time chart in Figure 2
Refer to column} Also, write register 9 V1, V2, V3, V
4 stores the valid signals of registers 1, 2, 3, and 4, respectively, and the write register 9
"DATA1, DATA2, DATA3, DATA
4" section has registers 5, 6, 7, and 8, respectively.
Various data of each pipeline state stored in is stored respectively.

Then, the output of the OR circuit 17 is output to the adder 13.
If the address indicated by the address register ADR11 of the history information recording memory 10 is "m", the address "m" is added "+1" to become "m".
+1'', open the gate 12, send out the write enable WE signal for the history information recording memory 10, and write the contents of the write register 9 to the history information recording memory 10. {Refer to the "Register 9, Gate 12, and Register 11" columns in the time chart of FIG. 2} Therefore, the history information recording memory 10 stores valid signals V1, V2, V3,
Only when any of V4 is being sent, the contents of the write register 9 at that time are written, and if all states of the pipeline are invalid, the number of cycles of the invalid period is written to the "CTR" of the write register 9.
However, writing of the write register 9 to the history information recording memory 10 is not performed. That is, data during an invalid state in which all states are invalid is ignored.

Also, at this time, address register ADR11 is also
Set the address of the history information recording memory 10 to “+1”
Therefore, the history information recording memory 10 can record the data of any state of the pipeline in the history information recording memory 10 only when the state of the pipeline is valid. When the enable signal V1, ~ of any state (usually the first state) is activated,
It has been counted up to that point. Number of cycles during which all states of the pipeline are invalid (stored in the “CTR” part of write register 9)
can be recorded in the history information recording memory.

(f) Effects of the Invention As explained in detail above, in the history information recording compression method of the present invention, in the history information recording method in a central processing unit using a pipeline, any state of the pipeline is valid. It records various data of each state only when all states of the pipeline are invalid, and ignores the data of each state when all the states of the pipeline are invalid, which is unnecessary for maintenance work. The number of cycles in a certain period is recorded, and when a certain state of the pipeline becomes valid next, the number of cycles and various data of each state including the state are recorded in the history information recording memory. This allows only the necessary history information to be recorded in the limited memory, which has a great effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a circuit showing one embodiment of the present invention, and FIG. 2 is a time chart explaining the operation of FIG. In the drawings, 1, 2, 3, 4, 5, 6, 7,
8, 9, 11 are registers, 10 is a history information recording memory or memory, 12 is a gate WE, 13,
15 is an adder, and 14 is a counter CTR.

Claims (1)

[Claims] 1. In a central processing unit using a pipeline system, each state of the pipeline is valid (V1,
V2, ~), means 11, 12, 13, 17 for writing data (DATA1, 2, 3, ~) 9 of the valid state of the pipeline into the memory 10;
and means 14, 15, and 16 for writing into the memory 10 the number of cycles CTR9 during a period in which all states of the pipeline are invalid, and the history information is compressed and recorded. Information recording compression method.