JPH0452656B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a digital modulation device, and in particular, modulation of an ^M2 code among DC-free codes that do not contain a DC component in the code itself is realized with a relatively simple circuit configuration. The object of the present invention is to provide a digital modulation device that can perform the following functions.

Recently, a special type of video tape recorder (hereinafter referred to as VTR) with a smaller cassette size than conventional consumer video tape recorders (hereinafter referred to as VTR) and an integrated camera, which is small and lightweight, has been developed.
VTR development is underway. This type of VTR can be classified into short-time recording/playback type and long-time recording/playback type, depending on the purpose of use. Naturally, in order to record and play back video signals of several MHz, VTRs use a rotating head to increase the relative speed and improve the frequency bandwidth and signal C/N, but audio signals are transmitted directly in the direction of tape travel. A method of recording in the longitudinal direction is adopted. However, in order to achieve long-term recording and playback with the above-mentioned special VTR, the tape speed must be reduced to 1/4 to 1/2 that of conventional VTRs due to the small cassette size.
It is necessary to keep it to 5. In this case, not only is the reproduction band narrower to several KHz compared to conventional audio signals, but the S/N is also significantly degraded, making it far from Hi-Fi. Therefore, one way to not only improve these shortcomings but also more actively improve the sound quality is to digitize the audio signal, compress the audio signal in units of one field, and record it directly on one side of the tape. It is considered. An example of this recording format is shown in FIG. 1, and an example of signal processing timing is shown in FIG. In this case, a method is adopted in which the digital signal is directly digitally modulated and recorded, but it is also necessary to select various digital modulation methods depending on the recording medium and running performance. When selecting from among various modulation methods, 1. self-clocking is possible, 2. the minimum magnetization reversal interval Tmin is large, that is, the maximum recording frequency is low, and 3. the maximum magnetization reversal interval Tmax is small. That is, phase information for self-clocking can be obtained temporally. 4. The detection window width T _W is large, that is, the S/N ratio against continuous noise is good and it is resistant to crosstalk. , 5. It is necessary to take into consideration that the conversion handling unit bit numbers m and n are small. Furthermore, when recording and reproducing a recording current waveform through an AC coupling element (e.g., a head through a rotating transformer), as in a VTR, the recording current waveform with a DC component is distorted, and the reproduction signal is not the same as the recording current. Even when integral detection is used to reproduce a waveform, the DC component lost by the AC coupling element cannot be reproduced. Therefore, DC-free codes that do not contain DC components are also important. Recently, as a DC free cord,
Various devices have been devised related to digital VTR,
For example, 1.M ² 2.ZM, 3.8-10 block code, 4.
There are scrambled, interleaved NRZi, etc.

The present invention realizes the above-mentioned ^M2 code modulation device in the DC free hood with a relatively simple configuration, and can also be used as an MFM modulation device used in conventional digital audio tape recorders etc. with a single switch. This has the advantage that it can be easily used by switching.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The digital modulation device of the present invention will be described below with reference to drawings of embodiments. First, MFM and ^M2
We describe the modulation rules for . MFM associates bit "1" with inversion, and bit "O" with no inversion. Furthermore, like FM, the boundaries between bits are also inverted. However, bit “O”
It is inverted only at the boundary between and bit “O”. on the other hand,
When ^M2 has two or more consecutive 1's, the magnetization may or may not be reversed by the last bit "1". Whether or not to invert is determined so that there is no direct current component of the signal.

Here, FIG. 3 shows an example of comparison of DC components of MFM and ^M2 , that is, baseline fluctuations, and comparison of modulation waveforms. In order to estimate the DC component in this case, the "charge" must be set as +1 for the minimum positive pulse width, -1 for the minimum negative pulse width, and ±2 for twice the pulse width. All you have to do is assume and count. This waveform in which the accumulated charge becomes extremely large has a DC component (baseline fluctuation).

FIG. 4 shows an embodiment of the digital modulation device of the present invention. In FIG. 4, A is an MFM modulation circuit, and B is a gate pulse generation circuit, which counts accumulated charges and makes sure that the accumulated charges are not zero. In this case, a gate pulse is generated at the last bit "1" of consecutive bits "1". C is MFM modulation circuit
This is a gate circuit that selects the ^M2 modulation circuit, and when the switch SW is set to 1, the MFM modulation output is obtained by preventing the passage of the aforementioned conditional gate pulse, and when the switch SW is set to 2, the gate pulse is passed,
This is to obtain ^M2 modulated output. 1 is a modulation circuit input terminal, to which a modulation circuit input signal a given in NRZ is applied. 2 is a clock pulse input terminal, to which a clock pulse b having a rising edge is applied to the data center of the modulation circuit input signal a. This clock pulse b is used to detect bit "1" in the data. 3 is a clock pulse input terminal, to which a clock pulse c having a falling edge is applied at the boundary between data. This clock pulse c is used to detect the boundary between bits "O" and "O". 4 is a clock pulse input terminal, to which a clock pulse P twice as large as the data clock is applied. 5 is a modulation output terminal, from which ^M2 modulation output q is output. The above MFM modulation circuit A is inverter 1
1. Delay flip-flop (hereinafter referred to as D-FF)
12, 13, 14, OR circuit 15, 16, NAND
It is composed of circuits 17 and 18, an AND circuit 19, and a flip-flop (hereinafter referred to as FF) 20. The NAND circuit 17 divides the modulation circuit input signal a into delayed data h and outputs a midpoint information pulse i of bit "1". The above OR circuit 16
outputs a boundary information pulse k between bits "O" and "O". The above NAND circuit 18 outputs pulse 1 which is a combination of both pulses, and in the case of MFM modulation, the pulse as it is is output.
It will be output from the AND circuit 19. Also
In the case of MFM modulation, the MFM modulation output is obtained from the FF 20 by repeating inversion at the rising edge of the pulse from the AND circuit 19.
The above gate pulse generation circuit B includes monostable multivibrators 21 and 22, D-FF 23, and AND circuit 2.
4, NAND circuits 25 and 26, an OR circuit 27, a 4-bit up-down counter 28, and an R-S flip-flop (hereinafter referred to as R-SFF) 29. In addition, gate circuit C is a switch
It consists of a SW and an OR circuit 31.

FIG. 5 shows a timing chart during ^M2 modulation of the above-mentioned digital modulation device, and the code a
-u correspond to the symbols a to u in FIG.

Next, the ^M2 modulation operation of the digital modulation device described above will be explained in detail based on FIGS. 4 and 5.

The ^M2 modulation rule is one of the MFM modulation rules, in which when multiple bits "1" are consecutive, the cumulative charge from the first bit "O" to the last bit "1" is counted and this is not zero. In this case, it can be considered that the last bit "1" is not inverted. Therefore, in the case of ^M2 , it is necessary to detect the last bit "1" of consecutive bits "1" and to determine whether or not it is inverted depending on the state of the accumulated charge. Therefore, first, the modulation circuit input signal a
is added to the monostable multivibrator 21, and a pulse e is generated at the falling edge of the data of the modulation circuit input signal a, and the last bit "1" of a single or continuous bit "1" is detected. In order to exclude a single bit "1" detection pulse from this pulse e and detect the last bit "1" information of consecutive bits "1", the modulation circuit input signal a is input to the D-FF12,
13 and 14, a pulse f delayed by 1.5T is obtained, and this pulse f gates the previous pulse e, and the AND circuit 24 obtains a pulse g. moreover,
If the accumulated charge is not zero, use this pulse g,
The inverted information pulse of the last bit "1" of the consecutive bits "1" of the pulse 1 is gated and excluded. In order to count the accumulated charge, the modulation circuit input signal a is passed through D-FF12 and 13 at 1.0T.
The leading edge detection pulse o of the first bit "O" of consecutive bits "1" is
is obtained in the NAND circuit 25, thereby clearing the 4-bit up-down counter (for example, 74F191) 28. This up-down counter 28 counts the cumulative charge. After being cleared by the leading edge detection pulse o from the NAND circuit 25, the clock p, which is twice the data clock, is counted up or down. 4-bit up-down counter 28
The outputs Q _A to Q are gated by an OR circuit 27 and a count "O" is detected. The output S of this OR circuit 27
When the count "O" of 1 and the pulse g of the AND circuit 24 match, it means that the accumulated charge has become zero. Here, if the OR gate output S of the counter 28 is not zero at the position of the pulse g of the AND circuit 24, the last bit "1" of the consecutive bits "1" means that the charges continue to accumulate with the same polarity. It is necessary to generate a gate pulse u to correspond to "no inversion". Gate pulse u generates pulse t from pulse s and pulse g through NAND circuit 26, and R-SFF2
Set 9. When the pulse s is zero, the R-SFF 29 is reset so that the last bit "1" of the consecutive bits "1" corresponds to inversion, and the up-down switching of the up-down counter 28 is modulated. Do this with output q.
By the above operation, a modulated output of ^M2 is obtained at the output terminal 5.

As detailed above, according to the present invention, it is possible to obtain both MFM and ^M2 modulation with a relatively simple configuration, and it is also effective in cases where DC recording and playback is not possible, such as in VTRs. It has the advantage of being able to

[Brief explanation of the drawing]

Figure 1 shows an example of PCM time axis compression recording by a VTR, where a is a tape path diagram, b is a tape pattern diagram, and Figure 2a is a timing chart.
Figure 2b is the signal arrangement diagram, and Figure 3 is the MFM.
FIG ^. 4 is a block diagram showing an embodiment of the digital modulation device of the present invention, and FIG. 5 is a timing chart thereof. A...MFM modulation circuit, B...gate pulse generation circuit, C...gate circuit, 11...inverter, 12-14, 23...delay flip-flop, 15, 16, 27, 31...OR circuit, 1
7, 18, 25, 26...NAND circuit, 19,
24...AND circuit, 20...flip-flop,
21, 22... Monostable multivibrator, 29
...R-S flip-flop, SW... switch.

Claims (1)

[Claims] 1. A pulse code modulated digital signal.
Corresponds to the midpoint of bit “1” by NANDing a pulse delayed by the data bit period T of the input data given in the form of NRZ and a thin rising pulse that has phase information at the midpoint of the input data bit. Obtain the pulse and input the above input data.
Bit “OO” is obtained by ORing a pulse delayed by 1.5T and a pulse obtained by delaying the above input data by T, and ORing this pulse with a thin falling pulse that has phase information at the boundary between bits. The boundary pulse of these two NAND
Obtain the modulation clock pulse by taking
A clear pulse is obtained by NANDing an MFM modulation means, a narrow rising pulse having phase information at the falling edge of the pulse obtained by delaying the input data by T, and a pulse obtained by delaying the input data by 2.5T,
The falling edge and falling edge of this clear pulse are in phase synchronization, and a 4-bit up-down counter whose clock input is a pulse having a period T/2 is cleared by the clear pulse and output obtained by counting up or down. A pulse with count “O” is obtained from the input data, and multiple consecutive bits “1” are obtained by ANDing a pulse obtained by delaying the input data by 1.5T and a narrow rising pulse that has phase information at the falling edge of the input data. ”, the pulse corresponding to the last bit “1” and the pulse of the above count “O”
Set the R-S flip-flop with the pulse obtained from NAND, and set the R-S flip-flop with the above count “O” pulse.
A gate pulse generation means is provided which obtains a cumulative charge "NON ZERO" pulse by clearing the -S flip-flop, and the above modulation clock pulse is ANDed with this "NON ZERO" pulse to obtain a final modulation clock pulse. A digital modulation device characterized in that it flip-flops at a rising edge to obtain an ^M2 modulation output waveform, and uses the ^M2 modulation output to switch the up-down counter between up and down. 2. The digital modulation device according to claim 1, wherein the MFM modulation output is obtained by inhibiting "NON ZERO" pulses.