JPH0452749A - Bus arbitrating circuit - Google Patents

Abstract

PURPOSE:To easily change the bus using priority among the data transfer modules by issuing the bus using grant with use of a memory where a priority pattern is previously stored when plural bus using requests are arbitrated and then rewriting a data pattern stored in the memory as necessary. CONSTITUTION:The bus using request signals 101 - 103 outputted from the data transfer modules 1.1 - 1.3 are held in the corresponding bits of a bus using request register 2. A selector 7 selects a bus using request signal 313 that arranges the outputs given from the register 2 and then outputs the signal 313 to a RAM 8, i.e., a priority deciding means as an address signal. Then the RAM 8 outputs the bus using grant signals 411 - 413 to the corresponding bits of a bus using grant register 4 as the priority decision data. Then a bus using grant data pattern, i.e., the priority is previously written into the rewritable RAM 8 as the data. Thus it is possible to flexibly cope with the change of the priority without increasing the hardware quantity.

Description

TECHNICAL FIELD The present invention relates to a bus arbitration circuit, and more particularly to a bus arbitration circuit that grants bus usage permission to bus usage requests from a plurality of data transfer modules according to predetermined priorities. be.

Prior Art An example of a conventional bus arbitration circuit of this type is shown in FIG. In the figure, a plurality of data transfer modules 1 to 1.n each make a bus use request (REQ) 10 to a common bus 1.
1 to Inn. These bus use requests 101-1
0n is set and held in the corresponding bit of request register 2, respectively.

These held outputs 401 to 40n are respectively input to the priority order determining means 3, and bus use permission (ACK) 411 to 4in is given to the bus use request according to a predetermined priority order.
are generated and set and held in the corresponding bits of the bus permission register 4, respectively.

A circuit example of the priority determining means 3 is shown in FIG.
In this example circuit, a circuit for determining priorities for bus use requests 401, 402, and 403 from three data transfer modules is shown.

These bus use requests 401 to 403 are handled by the AND gate 31
- 33 are each staffed by one person, and there are 40 requests to use the bus.
1; 402 are the respective inputs of the inverters 34 and 35. The output of the inverter 34 becomes the other input of the AND gate 32, 33, and other requests 402, 4 other than the own request 401
03 is suppressed.

Further, the output of the inverter 35 becomes another input of the AND gate 33, and other requests 403 are suppressed.

The output of these AND gates 31 to 33 is bus use permission 4
11 to 41n, and bus use permission register 4 in FIG.
The output of this register 4 becomes the final bus use permission], 11 to lln.

For example, when bus use requests 401 to 403 are input at the same time, bus use request 401 is input to AND gate 3 and at the same time is inverted by inverter 34 to close AND gates 32 and 33. Therefore, only the output 411 of the AND gate 31 is permitted to use the bus, and the register 4
If you hold it, it will be output as permission to use the lotus.

The outputted bus use permission 111 resets the bus use request register 2 that holds the own bus use request, and at the same time is input to the or game 1-5 to suppress the bus use request 31.
Generate 5.

When the transfer module 11 that has received the bus use permission 111 completes the data transfer, it outputs a transfer completion signal 211 to the OR gate 6. As a result, a bus use permission register reset signal 320 is generated from the OR gate 6, and all registers 4 are reset. In response to this, the bus use inhibition 31.5 generated by the OR gate 5 is canceled, and other requests for use of the q bus can be accepted.

In such conventional bus arbitration circuits, the priorities are fixed at the IIS point of the circuit design because they are configured with a priority determining means 3 that arbitrates bus use requests or with hardware such as AND gates and inverter games. I'm going to pinch it. If you change the priority order of J, or if you add a data transfer module, should you deal with it by changing the design?
It is necessary to prepare a separate means for determining priorities.

Another disadvantage is that as the number of data transfer modules increases, the amount of hardware in the circuit for determining priorities also increases accordingly.

Purpose of the Invention Therefore, the present invention has been made to eliminate such drawbacks of the conventional ones, and its purpose is to solve the problem of increasing the amount of hardware due to changes in priorities, addition of data transfer modules, etc. An object of the present invention is to provide a bus arbitration circuit that can be flexibly handled.

According to the present invention, there is provided a bus arbitration circuit which grants permission to use a bus according to a predetermined priority order in response to a bus use request from one of a plurality of data transfer modules. A selector that selectively derives a bus use request signal and an address signal from the outside;
A storage means in which available data is stored in advance, and a J
write means for rewriting bus use permission data from the column section in the storage means when an address signal from the outside is supplied as an address signal; A bus arbitration circuit is obtained which is characterized in that bus use permission is determined based on permission data.

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and parts equivalent to those in FIG. 3 are designated by the same reference numerals. Although this example shows a case where there are three transfer module calls, the present invention is not limited to this. Bus use request signals 101 to 103 output from the three transfer modules 1 to 1 and 3 are held in corresponding bits of the bus use request register 2, respectively.

When the control signal 311 is logic “0”, the SE1/Q7 selects the bus use request signal (T?P, Q”) 313, which is a combination of three outputs from the register 2, and the inhibition signal 315. , R which is a priority determining means as an address signal.
Output to AM8. The RAM 8 uses the output of the selector 7 as an address and uses the contents of the specified address as priority determining data as a bus use permission signal (^CK') 411-4
13 to the corresponding bits of the bus permission register 4, respectively.

This register 4 temporarily holds the data and outputs it to the corresponding data transfer modules 101-103 as bus use permission signals (ACK) Ill-113. This bus use permission signal IN~113 simultaneously resets the bus use request register 2 that holds its own request signal, and is ORed by the OR gate 5 which is the inhibiting means, and the inhibiting signal 31
By inputting the signal as 5 to the highest address of the selector 7, other request signals are suppressed. The details will be described later.

When one of the data transfer end signals 211 to 213 is output from the data transfer module to which the bus use permission signal has been output,
It is ORed by the OR gate 6 which is the termination means, and the termination signal 3 is output.
20 resets the bus use permission register 4, all the held bus use permission signals become logic "0".
become. The inhibition signal 315 for other bus use request signals becomes logic "0", and other bus use request signals can be accepted.

Figure 2 shows the RA when there are three data transfer modules.
This is an example of stored data in an MB. Bus use request signal 1
Address inputs of RAM 8 corresponding to 01 to 103 are assumed to be REQI', REQ2', and REQ3', respectively.

The RAM 8 is a rewritable RAM, and the address corresponds to the request signal from the data transfer module, and the priority bus use permission data pattern is written in advance as data, so that the read data becomes the bus use permission signal. It becomes.

Furthermore, the most significant bit of the address is the inhibition signal 315 (second
By inputting a signal corresponding to ACK (in the figure) and writing a pattern in which the output of the RAM 8 becomes "0" when "]" appears thereon, other request signals are suppressed.

An example will be explained according to FIGS. 1 and 2.

For example, if only the bus use request signal (corresponding to REQ3') is input to the request register 2, the bus use request signal is temporarily held in the corresponding bit of the request register 2, and then input from the register 2 to the selector 7.

Since the control signal 311 that controls the selector 7 is at logic "0", the selector 7 selects the bus use request signal 313 and the inhibition signal 315 from the register 2 and outputs them to the RAM 8 as address signals. The output address becomes "0001" and as shown in FIG. be done.

The contents of this register 4 are bus use permission signals 111 to 11.
Output as 3. Among them, the bus use permission signal 113 which is logic "1" is transmitted to the corresponding data transfer module 3.
At the same time, the register 2 holding its own bus use request 103 is reset.

Further, the bus use transfer permission signal 113 is ORed by the inhibiting means 5, and the inhibiting signal 315 is outputted to the RAM 8 through the selector 7. When the logic "1" is input to the input address ACK corresponding to the inhibit signal 315, this RAM 8 outputs the priority determining data "000" as shown in FIG. 2, regardless of the other request signals REQI' to REQ3'.゜ is output,
Other bus use request signals are suppressed.

Transfer module 3 that received the bus use permission signal 113
When the data transfer end signal 213 is output from the terminating means 6, the end signal 320 which is ORed by the terminating means 6 resets the bus use permission register 4. Since register 4 has been reset, bus use permission signals Ill to 1]3 are set to logic “0”.
, and the inhibition signal 315 ORed by the inhibition means 5 becomes 0"
becomes.

At this point, the control signal all is logic "0", the selector 7 selects the output signal 313 of the bus use request register 2 and the inhibition signal 315, and selects the RA as the address signal.
Outputting to M8.

As shown in FIG. 2, when the inhibit signal 315 changes from logic "1" to "0", the RAM 8 stores priority determining data "01" if the address is "0010".
0" (a value other than "000"), and other bus use request signals are accepted.

Next, bus use request signal 101 (corresponding to REQI')
A case will be explained in which the request signal 103 and the request signal 103 (corresponding to REQ3') are respectively input to the request register 2. These bus use request signals are temporarily held in the corresponding bits of the bus use request register 2 and inputted to the selector 7 as the bus use request signal 313. Since the control signal 311 that controls the selector 7 is at logic "0", the selector 7 controls the bus use request signal 313 and the inhibition signal 315.
is selected and supplied to the RAM 8 as an address signal.

This address becomes "0101", and as shown in FIG. 2, priority determining data "100" is read out as bus permission signals 411 to 413 and temporarily held in bus permission register 4. The content of this register 4 is that among the bus use permission signals 111 to 113, the permission signal 111 which is logic "1" is output to the corresponding data transfer module 1 and holds its own bus use request signal 101. Reset request register 2.

Further, the bus use permission signal 111 is ORed by the inhibiting means 5, and the inhibiting signal 315 is supplied to the RAM 8 through the selector 7 as an address signal. l? In AM8, the input address 80K corresponding to the inhibit signal 315 is set to logic ``1''.
is input, other bus use request signals REQl' ~
Irrespective of RE Q3', the priority determination data "000" is sent to the bus use permission signal 41 as shown in FIG.
Output as 1 to 413. At this time, the contents of the bus use permission register 4 do not change.

The bus use permission signals 411 to 413 are held by the register 4, or when the data transfer end signal 211 is output from the transfer module 1 that has received the bus transfer permission signal 111, they are ORed by the ending means 6 and the end signal 320 is output. resets the bus permission register 4. By resetting this register 4, the lotus use permission signal 11
1 to 3 become logic "0". Therefore, the inhibiting signal 315 ORed by the inhibiting means 5 becomes "0".

At this point, the control signal 311 is at logic "0", and the selector 7 selects the output signal 313 of the register 2 holding the bus use request signal and the inhibition signal 315, and outputs them to the RAM 8 as an address signal. When the inhibit signal 315 changes from logic "1" to "O" in the RAM 8, the input address becomes "0001", and the priority determining data "001" is read out as shown in FIG. Similar to the series of operations described above, the data transfer module 3
receives the bus permission signal 113.

Since the following operations are similar to the series of operations described previously, further explanation will be omitted.

FIG. 5 is a time chart of the configuration diagram in FIG. 1.

The operation of the block diagram of FIG. 1 based on the priority determination data shown in FIG. 2 will be explained with reference to FIG.

When bus use request signals 101 to 103 for a plurality of data transfer modules 1 to 1 and 3 are issued at the same time, they are held in the request register 2 at clock 0 and manually entered as addresses in the RAM 8. The address signal at this time is “011
1", so the priority determination data written in advance"
100” is the bus use permission signal 111 to 11 from RAM8.
Output as 8.

At clock 1, the priority determination data is held in the lotus use permission register 4. This register 4 provides a bus use permission signal 111 to the data transfer module 1. Next, at clock 2, the bus use request signal held in the request register 2 is reset by the bus use permission signal 111, and at the same time, the inhibition means 5 ORs the bus use permission signal 111, and the inhibition signal 315 is set to the bus use permission signal 111. Together with the use request signal 313, the selector 7 outputs it to the RAM 8 as an address signal.

The output address is 1011°, and the RAMP priority determination data “000” is assigned to the bus use permission register 4.
is output to.

When the transfer end signal 211 from the data transfer module 1 is detected at clock 3, the bus use permission signal 211 is reset at clock 4 by the end signal 320 ORed by the end means 6.

By resetting this permission signal i+t, the inhibition signal 315 becomes "O" and is outputted to the RAM 8 through the selector 7 as a rear address signal. At this time, the address becomes "0011", the RAM 8 outputs "010" as shown in FIG. 2, and the bus use request signal 102 is accepted.

Note that the bus use request signal 103 is the same as the bus use request signal 102.
Similarly, the requests are accepted in order and the entire operation is completed.

Next, a procedure for changing the priority determination data in the RAM 8 will be explained. The output of the control signal 311 becomes "1", the selector 7 selects the external address signal 310, and outputs this address signal 310 to the RAM 8.

The RAM 8 receives the external address signal 31 that has passed through the selector 7.
The data of the external data signal 312 is written to O.

In this case, the address signal 310 is an address specified by software, and the priority order determination data input from the data signal 312 is written to the RAM 8, and the priority order has been changed.

Effects of the Invention As described above, according to the present invention, when arbitrating a plurality of bus use requests, bus use permission is issued using a memory in which priority patterns are stored in advance, and this memory is updated as necessary. Since the data pattern in the data transfer module is rewritten, it is easy to change the priority order, and the addition of a data transfer module can also be flexibly accommodated.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing an example of a data pattern in the RAMg of FIG. 1, FIG. 3 is a diagram showing an example of a bus arbitration circuit showing the prior art, FIG. 4 is a circuit diagram showing an example of the priority determining means shown in FIG. 3, and FIG. 5 is a timing chart showing an example of the operation of the blocks shown in FIG. Explanation of symbols of main parts 1... Busts 1 to 1, 3... Data transfer module 7...
...Selector 8...RAM

Claims (1)

[Claims] (1) A bus arbitration circuit that grants bus use permission to bus use requests from a plurality of data transfer modules according to a predetermined priority order, the bus arbitration circuit providing bus use request signals from the data transfer modules and external signals. a selector for selectively deriving an address signal; a storage means that uses the output of the selector as an address input and stores bus use permission data in advance; and an address signal from the outside is supplied as an address by the selector; and writing means for externally rewriting bus use permission data in the storage means, and bus use permission is granted based on the bus use permission data read from the storage means. .