JPH0452841A - Storage device - Google Patents

Abstract

PURPOSE:To make it possible to use a system as long as possible by repeating memory access even at the time of detecting an uncorrectable memory access error or the like as the result of a memory access. CONSTITUTION:When the count value of a retry counter 8 reaches a prescribed value, a count end detection circuit 9 informs its detection result to a memory error F/F 11. The F/F 11 displays the existence of an uncorrectable memory error and transmits the displayed contents to a central processing unit(CPU) 14 to be a memory access requesting source to stop the system. Even when the memory access error exists, the memory access is repeated by the prescribed number of times without directly executing fault processing. Only when the memory access error is still continued after repeating the memory access by the prescribed number of times, the fault processing is started.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a storage device, and more particularly to a storage device that performs failure processing when a memory access error is detected as a result of memory access.

[Conventional technology]

Generally, a storage device is connected to a central processing unit, an input/output control device, etc. via a bus to constitute an information processing system. Conventionally, in this type of storage device, access to the memory is controlled by address-data commands input via an external bus as a result of memory access from a central processing unit, etc., and reading from this memory is performed. If an uncorrectable error is detected in the next data, the process moves to fault handling.
The storage device reported a memory error to the memory access requester, stopping the entire information processing system.

[Problem to be solved by the invention]

In the conventional storage devices described above, when a memory access error is detected and the failure is handled, even if the error is temporary and there is a possibility that the error will not occur if the memory access is performed again, the information is not stored unconditionally. The drawback is that it stops the processing system.

[Means to solve the problem]

The storage device according to the present invention includes a memory access instruction circuit that issues an access instruction again when an uncorrectable error is detected by reading data from the memory, and a retry counter that stores the number of memory retry access executions due to memory access error diversion. a count end detection circuit for detecting that a predetermined number of memory accesses have been completed; and a means for outputting a memory error detection report to a memory access requester when a memory error is detected even after performing a predetermined number of memory retry accesses. It has

[Effect]

According to the present invention, the number of times the information processing system is shifted to failure processing is reduced, and the system can be used effectively.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of a storage device according to the present invention. In the figure, 1 is a data register, 2
is an address register, 3 is a command register, and 4 is the output of this command register 3. The contents of the command 3a are decoded and if it is a read command, the data is addressed to the RAM 5 by the address signal 21 of the output of the address register 2. is read, and if it is an honor command, it is stored in RAM.
5, a memory access control circuit operates to write data 1 output from data register 1 to the address indicated by address signal 2, and 6 is an uncorrectable error detection circuit that checks the data read from RAM 5. 8 is a try counter for counting the number of retry accesses; 9 receives the output of the retry counter 8 and determines whether the count value has reached a predetermined number of times; A count end detection circuit outputs a signal to that effect if the number of retries has been reached; 10 is a memory access instruction circuit that outputs an access instruction signal as a precaution for memory retry access; 11 is a retry counter 8 when the number of retries reaches a predetermined value; A memory error display F/F, 12, indicates that the memory error has been reached.
Address register 2゜Command register 3. Memory access control circuit 4゜RAM5, uncorrectable error detection circuit 6. Reply display F/F 7, retry counter 8.
Count end detection circuit 9. Memory access instruction circuit 10
and memory error display 1'/]i' 11 is a main storage device, and 13 is a system bus common to the system.

Note that FIG. 2 is a schematic block diagram of an information system including the main storage device 12 shown in FIG. 1. In the same figure, 1
4 is a central processing unit, 15 is an input/output device, and 16 is a diagnostic device.

Next, the operation of the storage device according to the above configuration will be explained with reference to the operation flowchart shown in FIG. First, when the central processing unit 14 performs memory access to the main storage device 12, step S is performed.

When the central processing unit 14 outputs information such as address data commands to the system bus 13, it proceeds to step S.
At step 2, the main memory device 12 receives and accesses the address data command output to the system bus 13. That is, this address data command is stored in data register 1, address register 2, and command register 3, respectively. Then, in step S3, the memory access control circuit 4 decodes the contents of the command 3m output from the command register 3, and if it is a read command, it is addressed to the RAM 5 using the address signal 2a output from the address register 2. Data is read out, and if it is a write command, data 1 of the output of the data register 1 is written into the RAM 5 at the address indicated by the address signal 2a. In this case, when the memory access control circuit 4 performs reading in step S4, the RAM 5
At the same time, the data read from the data register 1 is stored in the data register 1, and the data 1
A is checked, that is, it is detected whether or not there is a memory access error. If the uncorrectable error detection circuit 6 does not detect an uncorrectable error in step S5, it reports that there is no error to the reply display F/F 7 in step S6, and the memory access control circuit 4 controls memory access. Display reply that it has finishedF/
Report to FT. Then, when the end of memory access is reported, if there is no uncorrectable error, the reply will be displayed as 1.
i'lB" 7 and outputs a reply signal 7m to the central processing unit #14 that is the source of the memory access request. Then, in step S7, when the central processing unit 14 receives the reply, the contents of the data register 1 are system bus 13
The data is fetched via the central processing unit 14, and the memory access of the central processing unit 14 is completed.

Next, in step S5, when the uncorrectable error detection circuit 6 detects an uncorrectable error when the memory access control circuit 4 reads out the RAM 5, the reply display F/F 7 suppresses the reply response and the memory access control circuit 4 detects an uncorrectable error. An uncorrectable error is reported to the instruction circuit 10 and retry counter 8. Then, in step S, the retry counter 8 receives the uncorrectable error signal 6a and the memory access end signal 5a from the memory access control circuit 4.
When both are detected, the count value, which is the number of retry accesses, is incremented by one. Then, in step S9, the count end detection circuit 9 receives the output of the retry counter 8 and determines whether the value has reached a predetermined number of times. If the predetermined number of times has not been reached, the memory access instruction circuit 10 is notified of this fact, and the memory access instruction circuit 10 outputs a detailed access instruction for memory retry access to the memory access control circuit %4, and then starts the RAM 5 again. is read out.

In this way, memory retry access is performed until the retry counter 8 reaches a predetermined number of times.

If the number of retry counters 8 has reached a predetermined value in step S9, the count end detection circuit 9 reports this to the memory error display F/F 11 in step S1°. The memory error display F/F 11 displays that an uncorrectable memory error has occurred, and notifies the central processing unit 14, which is the source of the memory access request, to that effect, and the system is stopped at step 8+1.

In this way, even if a memory access error occurs, the process does not immediately proceed to failure processing, but the memory access is repeated a predetermined number of times. Then, only if the memory access error continues even after repeating the memory access a predetermined number of times, the process shifts to failure processing.

〔Effect of the invention〕

As explained in detail above, according to the storage device of the present invention, even if a memory access error such as an uncorrectable one is detected as a result of memory access, the error does not occur by accessing the memory again. Since there is a possibility that the data can be read out at any time, the probability that the information processing system will stop operating due to a failure is reduced, and the system can be used for a longer period of time.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the storage device according to the present invention, FIG. 2 is a schematic block diagram of an information processing system equipped with the main storage device 12 shown in FIG. 4, and FIG. 3 is the same as that shown in FIG. 3 is a flowchart showing the operation of FIG. 1...Data register, 2...Φ・e address register, 3...Command register, 4...Memory access control circuit, 5...R7, M, l@...Cannot be corrected Error detection circuit, 7--Reply display F/F1
8... Retry counter, S--count end detection circuit, 10... Memory access instruction circuit, 11.
...memory display Fβ, 12...e main storage device,
13...Bus, 14...Φ central processing unit, 15...
- Input/output device, 16...Diagnostic device. Patent applicant: Ibaraki NEC Co., Ltd.

Claims (1)

[Claims] In a storage device that controls memory access using address/data commands input from an external bus and detects whether or not there is an uncorrectable error in the read data, memory retry access is performed again when an uncorrectable error is detected. 1. A storage device characterized in that when an uncorrectable error is detected even after a predetermined number of memory retry accesses, a memory error detection report is sent to a memory access request source.