JPH0453034B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a static type semiconductor memory device (hereinafter referred to as "static type memory").

[Conventional technology]

As shown in FIG. 2, a conventional static memory has a power supply terminal 1, a word line 2, and a bit line 3.
a, 3b, inverter transistors 4a, 4b,
Access transistors 5a, 5b, load resistor 6
A, 6b, storage nodes 7a, 7b, and ground line 8 constitute a unit memory cell.

In a device configured in this way, reading/
In the memory retention state where no write operation is performed,
Bit lines 3a and 3b are set to high potential, and word line 2 is set to low potential. Writing is performed by setting the bit line 3a or 3b to a low potential and the word line 2 to a high potential, and after writing is completed, by setting the word line 2 to a low potential, the written state is maintained. Ru.

To read data, set word line 2 to high potential,
A current is passed from the bit line to the conductive one of the inverter transistors 4a and 4b and the path of the access transistor connected in series with that transistor to generate a minute potential difference in the bit line. This is done by sensing with sense up.

Here, the load resistors 6a and 6b only prevent data from being inverted (memory contents being destroyed) due to a drop in the potential of a high-potential storage node due to leakage current from the inverter transistor that is cut off. The resistance value is chosen so that the current is supplied from the power supply.

However, static memory
In order to house many of the circuits shown in the figure on the same chip, the number of parts was large, and there was a limit to the increase in memory capacity.

In response to this, the inventor of the present invention proposed a static type memory as shown in FIGS. 3 to 5. FIG. 3 is a system diagram showing the block system. In FIG. 3, 10 is a memory cell matrix, 11 is an X (row) address buffer, and 12 is a Y
(column) address buffer, 13 is X (row) address decoder including word driver, 14 is Y (column)
Address decoder, 15 is a sense amplifier, 16 is a read/write control circuit, 17 is an output buffer,
18 is a detector, 19 and 20 are signal generators, 21 is a data output terminal, X0 to Xn are X (row) address signals, Y0 to Ym are Y (column) address signals,
is the chip select signal, DI is the data input signal,
R/W is a read/write control signal.

The detector 18 is designed to generate a detection signal φ _P when detecting a change in the address signal. The signal generator 19 is configured to generate a latch signal φ L for latching the output buffer 17 when the detection signal φ _P is supplied, and the signal generator 20 is configured to generate a latch signal φ _L for latching the output buffer 17 when the detection signal φ _P is supplied. When this happens, the signals on all word lines are set to "1" level. The read/write control circuit 16 is configured to control whether data is written to or read from the memory cell matrix 10. As shown in FIG. 4, the unit memory cells inside the memory cell matrix 10 include a word line 2, a bit line 3a on the positive phase side, a bit line 3b on the negative phase side, four transistors 4a,
It is composed of 4b, 5a, and 5b. 9a, 9
b is a load connected to the bit lines 3a and 3b.

The operation of the apparatus configured as described above will be explained using the timing diagram shown in FIG. In FIG. 5a, at time t1, any one of the X address signals X0 to Xn or the Y address signals Y0 to Ym
If any one of them changes, the detector 18
is a predetermined time period from time t1, as shown in Figure 5b.
Detection signal φ _P is generated after T1. The duration of this detection time φ _P is sufficient as long as it is the time necessary to operate the circuit to which this signal is supplied and is less than or equal to the duration of the address signal shown in FIG. 5a. When detection signal φ _P is generated, row address decoder 1
3, all the signals on the word line (there is a plurality of word lines) between the memory cell matrix 10 and the memory cell matrix 10 are set to the "0" level as shown in FIG. 5d. The signal generator 20 receives the latch signal φ _L and sets the word line control signal φ _X to the "0" level as shown in FIG. 5f.

Therefore, the row address decoder 13 sets the signal on the selected word line to "1" as shown in FIG. 5c.
level. At this time, the signal on the unselected word line continues to be at the "0" level as shown in FIG. 5d. Furthermore, as the latch signal φ _L becomes the "0" level, the output buffer 17 temporarily sends out the invalid data ID as shown in FIG. After that, the valid data of the address Ai specified by the address signal output from the row address decoder 13
Send VD. Then, after a predetermined delay time, the detector 18 detects the time when the valid data of the address Ai will be sent out at the time t2.
, the detection signal φ _P is set to “0” as shown in FIG. 5b.
Therefore, the latch signal φ _L becomes the "1" level as shown in FIG. 5e, and the data in the output buffer 17 is held. Then, as the latch signal φ _L goes to the "1" level, the word line control signal φ _X goes to "1" as shown in FIG. 5f.
level, so the signals on all word lines are “1”
level. At this time, since the signal on the selected word line is already at the "1" level as shown in FIG.
As shown in Figure d, the level changes from "0" to "1".

In this way, all word lines are "1" after time t2.
level, a "1" level signal is supplied to the word line 2 in FIG. 4, and the access transistors 5a and 5b are on.
When the signals on the bit lines 3a and 3b are kept at the "1" level, the transistors 5a and 5b serve as loads for the transistors 4a and 4b, and since the transistors 4a and 4b in FIG. 4 constitute a flip-flop circuit, The memory state of this circuit is determined by the X address signals X0 to Xn or the Y address signals.
It is maintained until Y0~Ym changes. Note that the signals on the bit lines 3a and 3b are transmitted to the transistors 9a and 3b.
It is held at the "1" level via pin 9b.

When the address signal changes at time t3, the detection signal φ _P becomes "1" after T1, as shown in FIG. 5b.
As shown in FIG. 5c, d, and e, the signal on the selected line, the signal on the non-selected line,
When the latch signal φ _L becomes "0" level at the same time and the latch signal φ _L becomes "0", the word line control signal φ _X becomes "0" level.

However, the device shown in FIG. 3 has problems in that it consumes a lot of power and requires a large cooling device. For this reason, the inventor of the present invention proposed a further improved static memory as shown in FIG. In FIG. 6, 20a is a signal generator, and 22 is a timer. In FIG. 6, the same or equivalent parts as in FIG. 3 are given the same reference numerals.

Next, the functions and operations of the device configured as described above will be explained using the timing chart shown in FIG.
The timer 22 generates a periodic _signal as shown in FIG. The word line control signal _φX is set to the "0" level during the period when the signal is supplied. The operation until the word line control signal _φX shown in FIG. 7f rises due to a change in the X address signal or Y address signal shown in FIG. 7a is the same as that of the device shown in FIG. 3. After the word line control signal _φX rises, the signal generator 20a
The word line control signal _φX is controlled in synchronization with the signal from the timer 22 shown in FIG. 7h, and the intermittent signal shown in FIG. 7f is sent out. As a result, the signal supplied to the unselected word line shown in FIG. 7d is also interrupted, so that the access transistor 5 shown in FIG.
a and 5b are intermittently brought into conduction. Therefore, the replenishment of charges from the bit lines 3a and 3b is also intermittent, and the power consumption is lower than that in FIG. 3. Note that the timing waveforms shown in FIGS. 7b, c, e, and g are similar to the timing waveforms shown in FIG. 5b, c, e, and g.

[Problem that the invention seeks to solve]

However, the reduction in power consumption is still insufficient, and it has been expected that a static memory that will further reduce power consumption will emerge.

The present invention has been made in view of these points, and an object thereof is to obtain a semiconductor memory device that can reduce power consumption.

[Means for solving problems]

In order to achieve such an object, the present invention provides a static type semiconductor memory device having a memory cell matrix, in which an access transistor is connected to each of two transistor elements constituting a flip-flop circuit so as to serve as a load. A memory cell matrix is used as a unit memory cell, and after a predetermined time has elapsed after receiving an address change detection signal and after a word line corresponding to a row address signal is selected, a plurality of word lines are connected to one or a predetermined unit row. a selection signal generating means for outputting a selection signal for sequentially selecting each word line for a certain period of time; A control means for activation is provided.

[Effect]

In the static semiconductor memory device according to the present invention, only one row or a plurality of rows of access transistors are turned on after the address signal changes.

〔Example〕

First, an overview of the present invention will be explained. In the static memory to which the present invention is applied,
When the address signal changes, a data output corresponding to that address is sent out, and after the output is latched, the word lines are sequentially brought to a high potential until the next address change, and the bit line at the high potential is connected to the storage node via the access transistor. Supplies current to maintain a high potential.

Next, an embodiment of a static type memory according to the present invention is shown in FIG. In FIG. 1, 23 is an address counter, and 24 is a selector. 1st
In the figure, the same or corresponding parts as in FIG. 6 are given the same reference numerals. The address counter 23 is a counter clocked by the word line control signal _φX .
A row address independent of the output of the row address buffer is generated, and the selector 24 selects whether to take in the address output from the row address buffer or the address output from the address counter.

The operation of the device configured in this way is as follows. The operation timing is similar to that shown in FIG. In the device shown in FIG. 1, the address counter 23 uses the word line control signal _φ
A row address signal is generated independently of external row address signals X0-Xn. Since the selector 24 takes in the output of the row address buffer 11 during the period of reading new data at the start of the cycle, the data at the address specified by the external address signals X0 to Xn is normally output, the output is latched, and the word line control signal is output. When _φ
Only one row of access transistors 5a and 5b shown in the figure becomes conductive. Thereafter, each time the word line control signal _φX is input as a clock, the output of the address counter 23 is sequentially increased to sequentially turn on all the rows. Therefore, the bit lines 3a, 3
The replenishment of charge from b is also for only one row, and the power consumption is lower than that in FIG. 6. Note that the address counter 23 has the row addresses of all word lines set, and sequentially outputs row address signals in response to clock input. After outputting row address signals for all word lines, this operation is repeated thereafter. Therefore, when the latch signal φ _L becomes "1", the word line control signal φ _X periodically becomes "1",
This acts as a clock and row address signals are sequentially output from the address counter 23, causing the latch signal _φL to become "0" and the word line control signal _φX to become "0".
The counting operation of the address counter 23 stops at the point when the row address signal reaches the current row address signal.
However, since the latch signal φ _L is "0", this output is not input to the row address decoder 13.
When the next address change occurs, the address counter 23 starts counting from this row address signal. In this embodiment, only one of all word lines is active at any given time, reducing power consumption.

In addition, in the above explanation, the address counter 23 is 1.
Although it is assumed that a row is selected, the same effect can be expected even if addresses are generated to select multiple rows.

〔Effect of the invention〕

As explained above, the present invention provides a memory cell matrix in which the unit memory cell is an access transistor connected to each of two transistor elements constituting a flip-flop circuit, and an address change detection signal. After a predetermined time has elapsed and after the word line corresponding to the row address signal has been selected, multiple word lines are
a selection signal generating means for outputting a selection signal for sequentially selecting one unit row or each predetermined unit row for a certain period of time; By providing a control means for sequentially activating the word lines, power consumption can be reduced, and the cooling device and the like can be made smaller.

[Brief explanation of the drawing]

FIG. 1 is a system diagram showing one embodiment of a semiconductor memory device according to the present invention, FIG. 2 is a circuit diagram showing an example of a unit memory cell constituting a conventional static type semiconductor memory device, and FIG. 4 is a system diagram showing a static type semiconductor memory device, FIG. 4 is a circuit diagram showing unit memory cells configuring the device shown in FIG. 3, and FIG. 5 is a timing diagram for explaining the operation of the device shown in FIG. 3. , FIG. 6 is a system diagram showing another conventional static type semiconductor memory device, and FIG. 7 is a timing chart for explaining the operation of the device shown in FIG. 6. 10...Memory cell matrix, 11...Row address buffer, 12...Column address buffer,
13... Row address decoder, 14... Column address decoder, 15... Sense amplifier, 16... Read/write control circuit, 17... Output buffer,
18...detector, 19,20a...signal generator,
21...Data output terminal, 22...Timer, 23
...Address counter, 24...Selector.

Claims (1)

[Scope of Claims] 1. A plurality of word lines arranged in each row, a plurality of bit line pairs arranged in each column, connected between a first storage node and a ground node, and connected to a gate electrode. a first inverter transistor connected to the second storage node, and a second inverter transistor connected between the second storage node and the ground node, the gate electrode of which is connected to the first storage node. The transistor is connected between the transistor and one bit line of the bit line pair arranged in the column corresponding to the first storage node, and the gate electrode is connected to the word line arranged in the corresponding row. The first
and the other bit line of the bit line pair arranged in the column corresponding to the second storage node, and the gate electrode is connected to the word line arranged in the corresponding row. connected second
a memory cell matrix in which unit memory cells are arranged in a plurality of rows and columns, each having access transistors; A row address decoder for selecting a line, a column address decoder for receiving a column address signal and selecting a bit line pair corresponding to this column address signal, and a column address decoder for detecting a change in the row address signal and outputting an address change detection signal. an address change detection means for outputting, upon receiving an address change detection signal from the address change detection means, a word line corresponding to the row address signal is selected after a predetermined time has elapsed after receiving the address change detection signal; selection signal generating means for outputting a selection signal for sequentially selecting the plurality of word lines one by one or for each predetermined unit row for a certain period of time; and each row selected based on the selection signal from the selection signal generation means. control means for sequentially activating selected word lines by keeping the access transistors conductive for the predetermined period of time. 2. The selection signal generation means includes a signal generation means for receiving an address change detection signal from the address change detection means and outputting a signal whose H level and L level sequentially change after a predetermined time has elapsed, and an H level from this signal generation means. Claim 1: The address counter includes an address counter that counts up or counts down in response to a change from a level to an L level or from an L level to an H level and outputs a selection signal. The semiconductor storage device described in . 3. The control means has a selector that receives a signal from the signal generation means of the selection signal generation means and selectively outputs the selection signal from the address counter of the selection signal generation means to the row address decoder based on this signal. A semiconductor memory device according to claim 2, characterized in that: