JPH0453068Y2 - - Google Patents

Description

[Detailed explanation of the invention] "Industrial application field" This invention uses a delta-sigma modulated signal to
The present invention relates to a decimation circuit suitable for use when converting to a linear PCM signal.

"Prior Art" Delta-sigma modulation is known as one of the analog/digital conversion technologies.

FIG. 4 is a block diagram showing the configuration of a delta-sigma modulation circuit. In the figure, numeral 1 is an integrating circuit that integrates the deviation between the input analog signal _S.sub.X and the feedback quantized signal (+V/-V). 2 is a comparator circuit that operates with a high-speed clock signal ckl (1 to 4 MHz), and when the output signal of the integrating circuit is negative, it is a "0" signal, and when it is positive, it is a "1" signal. Output as _Y. Furthermore, the comparator circuit 2 is connected to the integrator circuit 1.
Depending on the polarity of the output signal, +V or -V, which is the maximum level of the signal to be A/D converted, is fed back to the deviation detection point 3 as a quantized signal. According to the above circuit configuration, the average power of the quantized signal to be fed back is equal to the average power of the analog input signal S _X.
In this case, the delta-sigma modulation circuit can be considered a 1-bit A/D converter.

Since the output signal of this delta-sigma modulation circuit has a high clock rate (1 to 4 MHz), processing in the subsequent circuit will be difficult if left as is. Therefore, a decimation circuit is provided after the delta-sigma modulation circuit to convert the output signal into a low-speed linear PCM signal.
It is converted to a linear PCM signal of about

FIG. 5 is a block diagram showing the configuration of a conventional decimation circuit. In the figure, 5 is the signal S _Y
This is a gate that opens when the signal is "1" and closes when the signal is "0". Each value of the triangular window function (D in Figure 6) is sequentially supplied to this gate from the weighting function generating circuit 6 in synchronization with the high-speed clock ckl, and when it is in the open state, the value of the window function is is output,
When in the closed state, a "0" signal is output. The output signal of the gate 5 is accumulated every predetermined period by a feedback loop consisting of an accumulator 7 and a delay 8.
A signal S _z is created. In this case, the accumulation period of the accumulator 7 and the delay 8 is determined by the period of the reset signal R (see FIG. 6C), and the weighting function generator 6 generates a window function for each period of the reset signal R. It is now output.

As mentioned above, converting a linear PCM signal using a window function converts a delta-sigma modulated signal into a linear PCM signal.
When converting to a PCM signal, the sampling frequency is 1/N (N = delta-sigma modulation signal clock/
This is to remove high frequency noise such as aliasing distortion caused by the linear PCM signal clock.

``Problems to be solved by the invention'' By the way, in the conventional decimation circuit described above, a triangular window is used as the window function, so the spectrum of the output signal is as shown in Fig. 7, and the sub-pole The amount of attenuation was approximately -27dB. As a result, if an A/D converter was constructed by combining a conventional decimation circuit and a delta-sigma modulation circuit, the number of effectively usable bits would be about 4 to 5 bits, which was extremely impractical.

This invention was made in view of the above-mentioned circumstances, and provides a decimation circuit that can obtain a practically effective number of bits when configuring an A/D converter in combination with a delta-sigma modulation circuit. The purpose is to

"Means for Solving the Problem" In order to solve the above problem, this invention generates a window function having the same period as the generation period of the output linear PCM signal, and Function and delta sigma modulated input linear PCM
In the decimation circuit that converts the input linear PCM signal to the output linear PCM signal by multiplying and accumulating signals, the window function generating section generates a window function in which the amount of attenuation of the sub-pole is larger than that of the triangular window. It is characterized by the use of materials that

"Effect" Since the delta-sigma modulated signal is multiplied by a window function with a large sub-pole attenuation, harmonic noise is suppressed, thereby increasing the number of effective bits when configuring an A/D converter. be able to.

"Embodiments" Hereinafter, embodiments of this invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the structure of an embodiment of this invention, and parts corresponding to those in FIGS. 4 and 5 described above are designated by the same reference numerals, and explanation thereof will be omitted.

In FIG. 1, reference numeral 10 denotes a Blackman-Harris window generating section, which generates each value of the Blackman-Harris window as shown in FIG. 2 in synchronization with the timing of the high-speed clock ckl. In addition, the Blackman-Harris window generating section 10 generates a reset signal R (see FIG. 6C).
The window function is generated repeatedly every cycle.

According to the above configuration, the spectrum of the output signal S _Z becomes as shown in Fig. 3, and the attenuation amount of the subpole is -
It becomes more than 67dB. Therefore, when an A/D converter is configured by combining the decimation circuit and delta-sigma modulation circuit shown in Figure 1, harmonic noise will not be mixed in until the maximum value is attenuated by 67 dB or more. Up to about 12 bits can be used effectively.

In addition, in the above embodiment, a Brackman-Harris window was used as the window function, but instead of this,
A Hamming window, a Brachmann window, etc. may also be used. The amount of attenuation in this case is -43 dB for the former and -58 dB for the latter.

The Hamming window, Brachman window, and Brachman-Harris window suitable for use in the above embodiments are defined by the following equations (1) to (3), respectively.

<Hamming window> ω(n)=0.54348−0.45652・COS{2πn/(N−
1)} ...(1) <Bruckmann window> ω(n)=0.42659−0.49656・COS{2πn/(N−
1)} +0.07685・COS{4πn/(N−1)} …(2) <Bruckman-Harris window> ω(n)=0.35875−0.48829・COS{2πn/(N−
1)} +0.14128・COS{4πn/(N−1)} −0.01168・COS{6πn/(N−1)} …(3) In the above formulas (1) to (3), N is an integer constant It is. Further, n is an integer variable corresponding to the passage of time.

Figure 8 shows Hamming window W1, Bratschmann window W2,
Each shows a Bratschmann-Harris window W3. these are,
For the case where N=102, the values of each window function ω(n) are calculated using the above equations (1) to (3), and the results are plotted.

"Effect of the invention" As explained above, according to this invention, a window function having the same period as the generation period of the output linear PCM signal is generated by the window function generator, and delta-sigma modulation is performed with this window function. In the decimation circuit that converts the input linear PCM signal to the output linear PCM signal by multiplying and accumulating the input linear PCM signal by the input linear PCM signal, the attenuation of the sub-pole as the window function generating section is larger than that of the triangular window. Since a device that generates a window function is used, harmonic noise can be significantly suppressed, and an A/D converter can be constructed with practicality.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of this invention, FIG. 2 is a waveform diagram showing a black mannaris window used in the same embodiment, and FIG. A characteristic diagram showing the spectrum of the Harris window. Figure 4 is a block diagram showing the configuration of the delta-sigma modulation circuit.
Fig. 5 is a block diagram showing the configuration of a conventional decimation circuit, Fig. 6 is a waveform diagram showing the waveforms of each part of the conventional decimation circuit, and Fig. 7 shows the spectrum of a triangular waveform window used in the conventional decimation circuit. The characteristic diagram, FIG. 8, is a diagram showing a Hamming window, a Brachman window, and a Brachman-Harris window suitable for application to this invention. 10...Brackman-Harris window generation section (window function generation section).

Claims (1)

[Claims for Utility Model Registration] (1) A window function generating section generates a window function having the same period as the generation period of the output linear PCM signal, and this window function and the delta-sigma modulated input linear PCM signal are In the decimation circuit that converts the input linear PCM signal to the output linear PCM signal by multiplying and accumulating, the window function generating section generates a window function in which the amount of attenuation of the sub-pole is larger than that of the triangular window. A decimation circuit characterized by using. (2) The decimation circuit according to claim 1, wherein the window function generating section generates a Brackman-Harris window. (3) Claim 1, wherein the window function generating section generates a Hamming window.
The decimation circuit described in section. (4) The decimation circuit according to claim 1, wherein the window function generating section generates a Brachman window.