JPH0453087A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To increase a write margin in a long cycle by generating a one-shot pulse and boosting against when detecting reduction in the level of a word line driving signal in the case of operating. CONSTITUTION:On standby, the word line driving signal (the inverse of RAS) is H and the word line driving signal (RX) is L. When reading or writing a data, however, the inverse of RAS is L and the signal RX is boosted up to a Vcc+alpha through a boosting capacitor 3 according to the delay signal of the RX itself. In such a case, when there is fine leaf in the boosting capacitor 3 and the level of the RX is reduced only by beta, a level detector 4 for the RX outputs H. A node B is turned from H to L while being slightly delayed rather than the change of a node A from L to H by the operations of inverters 5-7. In this case, there is a moment when the both nodes A and B are made H, and by inputting the two H of these nodes A and B and the H of a node C to a gate 9, the one-shot pulse to be momentarily made H is generated at the output of the gate 9. This one-shot pulse boosts the level of the RX again through a boosting capacitor 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a word line drive signal generation circuit.

[Conventional technology]

FIG. 3 is a circuit diagram of a conventional word line drive signal (R1) generation circuit. In the diagram, (1) is Otori Channel! A transistor, (2) a delay circuit, and (3) a boosting capacitor. FIG. 4 is a timing chart of each signal O of the word line drive signal generation circuit of FIG. 3.

Next, the operation will be explained. In semiconductor storage devices,
When in standby, Rm8 is I! Right! is Xl0W
However, when reading or writing data, i is I and ow, and Rx is boosted to more than Woo (Maoe+α) by the delay signal of R1 itself via boost capacitor (3) □ By boosting the east x to maoe+α in this manner, advantages such as being able to write Woo into the memory 7μ and improving the speed of reading charges from the memory 7μ are obtained.

[Problem to be solved by the invention]

The word line drive signal generation circuit in a conventional semiconductor memory device is configured as described above, so if there is a slight leak in the boost capacitance, the boost level of RX will decrease over time, causing IX to drop below Vco. By increasing the pressure to α, the advantage of K cannot be obtained. Also L”jc 6701
W with e Read Modify Write etc.
There was a problem that writing could not be performed at the lower limit of oo.

This invention was made to solve the above problems, and even if there is a small leak in the boost capacitor (3), the R
Keep the boost level of K constant and set the special KLong oy
An object of the present invention is to obtain a semiconductor memory device with an increased write margin in OL.

[Means to solve the problem]

The semiconductor memory device according to the present invention includes a circuit that detects the level of lx, and a circuit that detects the level of lx, and
[Operation] The semiconductor memory device according to the present invention generates a one-shot pulse when detecting a decrease in the level of lx during operation,
Boost again.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1g1 is a circuit diagram of a word line drive signal generation circuit in a semiconductor memory device showing a -* embodiment of the present invention. In the figure, (1) is a 1-channel transistor, (2) F
i delay circuit, (3), Qfl is a boost capacitor 0, but the boost capacitor αα is set to have a larger capacitance than the boost capacitor (3); o(4) is the boost capacitor (3); Detection circuit, (5), (6), (7
), (8) is an inverter, (9) is a muN'D game F
There is f. FIG. 2 is a timing chart diagram of each signal and each node in FIG. 1 to explain the 0th order operation. When in standby mode, use lA8, IILgk, Teap, RXi.
Low f Arca, when reading or writing data, Rig is Low and RX is Ik! It is boosted to Voa+α by its own delay signal via the boost capacitor (3). Here, if there is a small leaf of boosting capacitance (3)K and the RXGD level drops by β and becomes Woe 1 α-β, the ILX level detector (4) outputs Hlgh. (When ix is greater than or equal to vCc+α, this level detector (4) outputs LOW.) Node B is activated by the action of inverters (5), (c+), and (7).
The change from Low to High in the two-tom is H with a little delay.
lgh becomes LQW 0 Here, there is a period 111 where both node A and node B become Iiiih, and this twotom, the two Hlgh of node B and the Hlgh of 7-do 0 (R
By inputting ig9 to the AND gate (9), a one-shot signal that becomes H1gh during -r is generated at the output of the gate (9). This one-shot current boosts the level of Ilx again to Maoe+6 via the boost capacitor ω. [Effects of the Invention] As described above, according to the present invention, the level of RX decreases during operation. By detecting this and boosting the pressure again, lx
The effect of being able to maintain a constant level of 0

[Brief explanation of drawings]

FIG. 1 is a word line drive signal generation circuit diagram in a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a timing chart of each signal and each node in FIG. 1, and FIG. 3 is a conventional O semiconductor memory device. 4 is a timing chart of each signal in FIG. 3. In the figure, (1) is an n-channel transistor, (2
) is a delay circuit, (a) = (2) is a boost capacitor, (4) is a level detector, (5) # (6), (7),
(8) is an inverter, and (9) is a gate (φ0). In the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] 1. A semiconductor memory device, wherein the word line drive signal generation circuit includes a circuit that generates a one-shot pulse when detecting a drop in the level of the word line drive signal during operation, and boosts the word line drive signal again.