JPH045309B2 - - Google Patents

Info

Publication number
JPH045309B2
JPH045309B2 JP56195406A JP19540681A JPH045309B2 JP H045309 B2 JPH045309 B2 JP H045309B2 JP 56195406 A JP56195406 A JP 56195406A JP 19540681 A JP19540681 A JP 19540681A JP H045309 B2 JPH045309 B2 JP H045309B2
Authority
JP
Japan
Prior art keywords
intermediate frequency
video
circuit
detection circuit
balanced
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56195406A
Other languages
Japanese (ja)
Other versions
JPS5896472A (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP56195406A priority Critical patent/JPS5896472A/en
Publication of JPS5896472A publication Critical patent/JPS5896472A/en
Publication of JPH045309B2 publication Critical patent/JPH045309B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/44Receiver circuitry for the reception of television signals according to analogue transmission standards

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Television Receiver Circuits (AREA)

Description

【発明の詳細な説明】 この発明は映像中間周波増幅器と映像検波回路
とインターキヤリア音声中間周波検波器と自動局
部発振周波数制御器とを含み、集積回路によつて
構成されるようなテレビジヨン受像機の信号処理
回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention includes a video intermediate frequency amplifier, a video detection circuit, an intercarrier audio intermediate frequency detector, and an automatic local oscillation frequency controller, and is applicable to a television receiver configured by an integrated circuit. related to the signal processing circuit of the machine.

第1図は従来のテレビジヨン受像機の信号処理
回路の概略ブロツク図である。構成において、映
像中間周波増幅器1には、チユーナ(図示せず)
から入力端子2,3を介して映像中間周波信号が
与えられる。映像中間周波増幅器1はその映像中
間周波信号を増幅した後、それを映像検波回路4
に与える。映像検波回路4は映像中間周波信号を
検波し、映像検波出力を端子5から出力する。同
時に、映像検波回路4は映像中間周波信号から搬
送波信号を取り出し、自動局部発振周波数制御器
8に与える。なお、映像検波回路4は平衡出力回
路を含み、自動局部発振周波数制御器は平衡入力
回路を有していて、映像検波回路4と自動局部発
振周波数制御器8は平衡接続される。
FIG. 1 is a schematic block diagram of a signal processing circuit of a conventional television receiver. In the configuration, the video intermediate frequency amplifier 1 includes a tuner (not shown).
A video intermediate frequency signal is applied from the input terminals 2 and 3 through input terminals 2 and 3. After amplifying the video intermediate frequency signal, the video intermediate frequency amplifier 1 transmits it to the video detection circuit 4.
give to The video detection circuit 4 detects the video intermediate frequency signal and outputs the video detection output from the terminal 5. At the same time, the video detection circuit 4 extracts a carrier signal from the video intermediate frequency signal and supplies it to the automatic local oscillation frequency controller 8. The video detection circuit 4 includes a balanced output circuit, the automatic local oscillation frequency controller has a balanced input circuit, and the video detection circuit 4 and the automatic local oscillation frequency controller 8 are connected in a balanced manner.

一方、映像中間周波増幅器1の他方出力から映
像中間周波信号がインターキヤリア音声中間周波
検波器6に与えられ、インターキヤリア中間周波
信号が端子7から出力される。このような信号処
理回路は単一の半導体基板内に設けられて、バイ
ポーラモノリシツク半導体集積回路によつて構成
され、従来よりテレビジヨン受像機に頻繁に使用
されるものである。
On the other hand, the video intermediate frequency signal is applied from the other output of the video intermediate frequency amplifier 1 to the intercarrier audio intermediate frequency detector 6, and the intercarrier intermediate frequency signal is output from the terminal 7. Such a signal processing circuit is provided within a single semiconductor substrate and is constituted by a bipolar monolithic semiconductor integrated circuit, and has conventionally been frequently used in television receivers.

このような信号処理回路において、映像中間周
波増幅器1、映像検波回路4、インターキヤリア
音声中間周波検波器6および自動局部発振周波数
制御器8のそれぞれの利得を上げたとき、たとえ
ば映像検波回路4の端子5から映像中間周波増幅
器1の入力端2,3に浮遊容量や電磁誘導などに
より帰還が生じて、映像中間周波増幅器1の利得
を大きくするにしたがい不安定になり、発振およ
び相互干渉を起しやすくなる。この現象はインタ
ーキヤリア音声中間周波検波器6および自動局部
発振周波数制御器8についても同様である。特
に、映像中間周波増幅器1、映像検波回路4、イ
ンターキヤリア音声中間周波検波器6および自動
局部発振周波数制御器8をIC化した場合、IC内
の配線、抵抗あるいはインダクタンスによる交流
成分の帰還により発振や相互干渉をより起こしや
すくなる。
In such a signal processing circuit, when the gains of the video intermediate frequency amplifier 1, the video detection circuit 4, the intercarrier audio intermediate frequency detector 6, and the automatic local oscillation frequency controller 8 are increased, for example, the gain of the video detection circuit 4 increases. Feedback occurs from the terminal 5 to the input terminals 2 and 3 of the video intermediate frequency amplifier 1 due to stray capacitance, electromagnetic induction, etc., and as the gain of the video intermediate frequency amplifier 1 is increased, it becomes unstable and causes oscillation and mutual interference. It becomes easier. This phenomenon also applies to the intercarrier audio intermediate frequency detector 6 and the automatic local oscillation frequency controller 8. In particular, when the video intermediate frequency amplifier 1, the video detection circuit 4, the intercarrier audio intermediate frequency detector 6, and the automatic local oscillation frequency controller 8 are integrated into ICs, oscillation occurs due to the feedback of AC components through wiring, resistance, or inductance within the IC. and mutual interference are more likely to occur.

それゆえに、この発明の主たる目的は、各ブロ
ツクのそれぞれの回路電流を特に交流的に平衡入
力することにより、利得を上げても安定動作し得
るテレビジヨン受像機の信号処理回路を提供する
ことである。
Therefore, the main object of the present invention is to provide a signal processing circuit for a television receiver that can operate stably even when the gain is increased by inputting the circuit currents of each block in a balanced manner, especially in an alternating current manner. be.

この発明を要約すれば、映像中間周波増幅器と
映像検波回路と自動局部発振周波数制御器とをそ
れぞれ交流的に平衡となるように構成された差動
増幅回路を介して直列的に接続し、映像中間周波
増幅器とインターキヤリア音声中間周波検波器も
交流的に平衡入力となるように構成された差動増
幅回路を介して直列的に接続して信号処理回路を
構成したものである。
To summarize this invention, a video intermediate frequency amplifier, a video detection circuit, and an automatic local oscillation frequency controller are connected in series via differential amplifier circuits each configured to be balanced in terms of alternating current. The intermediate frequency amplifier and the intercarrier audio intermediate frequency detector are also connected in series through a differential amplifier circuit configured to have balanced AC input to form a signal processing circuit.

この発明の上述の目的およびその他の目的と特
徴は以下に図面を参照して行なう詳細な説明から
一層明らかとなろう。
The above objects and other objects and features of the present invention will become more apparent from the detailed description given below with reference to the drawings.

第2図はこの発明の一実施例の概略ブロツク図
である。この第2図は以下の点をのぞいて第1図
と同じである。すなわち、映像中間周波増幅器1
0は平衡出力回路を含み、映像検波回路は平衡入
力回路を含む。そして、映像中間周波増幅器10
と映像検波回路11は平衡接続される。また、イ
ンターキヤリア音声中間周波検波器12も同様に
して平衡入力回路を含み映像中間周波増幅器10
とインターキヤリア音声中間周波検波器12は平
衡接続される。このように、映像中間周波増幅器
10と映像検波回路11と自動局部発振周波数制
御器8を平衡接続しかつ映像中間周波増幅器10
とインターキヤリア音声中間周波検波器12も平
衡接続することによつて安定に動作させることが
できる。すなわち、映像中間周波増幅器10、映
像検波回路11、自動局部発振周波数制御器8お
よびインターキヤリア音声中間周波検波器12の
それぞれの利得を上げたとき、たとえば映像検波
回路11の出力端子5から映像検波回路11の入
力部に浮遊容量や電磁誘導などにより帰還が生じ
たとしても、その入力が平衡入力であるため、帰
還成分は同相成分として加わる。したがつて、ル
ープゲインは第1図に示した信号処理回路のよう
には大きくなることがなく、発振を生じにくくな
る。また、インターキヤリア音声中間周波検波器
12および自動局部発振周波数制御器8も同様に
して平衡接続されているので、前述の説明と同様
にして安定に利得を上げることができる。
FIG. 2 is a schematic block diagram of one embodiment of the present invention. This FIG. 2 is the same as FIG. 1 except for the following points. That is, the video intermediate frequency amplifier 1
0 includes a balanced output circuit, and the video detection circuit includes a balanced input circuit. And a video intermediate frequency amplifier 10
and the video detection circuit 11 are connected in a balanced manner. Similarly, the intercarrier audio intermediate frequency detector 12 includes a balanced input circuit, and the video intermediate frequency amplifier 10 includes a balanced input circuit.
and intercarrier audio intermediate frequency detector 12 are connected in a balanced manner. In this way, the video intermediate frequency amplifier 10, the video detection circuit 11, and the automatic local oscillation frequency controller 8 are connected in a balanced manner, and the video intermediate frequency amplifier 10
By connecting the intercarrier audio intermediate frequency detector 12 and the intercarrier audio intermediate frequency detector 12 in a balanced manner, stable operation can be achieved. That is, when the respective gains of the video intermediate frequency amplifier 10, the video detection circuit 11, the automatic local oscillation frequency controller 8, and the intercarrier audio intermediate frequency detector 12 are increased, for example, video detection is detected from the output terminal 5 of the video detection circuit 11. Even if feedback occurs at the input section of the circuit 11 due to stray capacitance, electromagnetic induction, etc., the feedback component is added as an in-phase component because the input is a balanced input. Therefore, the loop gain does not become as large as in the signal processing circuit shown in FIG. 1, and oscillations are less likely to occur. Further, since the intercarrier audio intermediate frequency detector 12 and the automatic local oscillation frequency controller 8 are also connected in a balanced manner, the gain can be stably increased in the same manner as described above.

第3図は映像中間周波増幅器10と映像検波回
路11に含まれる平衡出力回路と平衡入力回路の
具体的な電気回路図である。図において、映像中
間周波増幅器10は映像中間周波増幅回路101
を含む。この映像中間周波増幅回路101はたと
えば差動増幅回路などによつて構成され、出力信
号が平衡出力として導出される。この平衡出力は
トランジスタ102と103に与えらえる。トラ
ンジスタ102と103は差動増幅回路を構成
し、それぞれのエミツタから出力端子109,1
10に出力信号が与えられる。
FIG. 3 is a specific electrical circuit diagram of a balanced output circuit and a balanced input circuit included in the video intermediate frequency amplifier 10 and the video detection circuit 11. In the figure, the video intermediate frequency amplifier 10 is a video intermediate frequency amplification circuit 101.
including. This video intermediate frequency amplification circuit 101 is composed of, for example, a differential amplification circuit, and outputs an output signal as a balanced output. This balanced output is provided to transistors 102 and 103. Transistors 102 and 103 constitute a differential amplifier circuit, and output terminals 109 and 1 are connected from their respective emitters to output terminals 109 and 103.
An output signal is provided to 10.

映像中間周波増幅器10の出力端子109,1
10から出力された映像中間周波信号は映像検波
回路11の入力端子111,112に与えられ
る。入力端子111,112に入力された映像中
間周波信号はそれぞれコンデンサ113,115
を介してトランジスタ114,116のベースに
入力される。このトランジスタ114,116は
平衡入力回路を構成する。そして、それぞれのエ
ミツタから検波回路117に映像中間周波信号が
与えられる。この検波回路117は差動増幅回路
によつて構成される。
Output terminal 109,1 of video intermediate frequency amplifier 10
The video intermediate frequency signal output from 10 is applied to input terminals 111 and 112 of video detection circuit 11. Video intermediate frequency signals input to input terminals 111 and 112 are connected to capacitors 113 and 115, respectively.
It is input to the bases of transistors 114 and 116 via. The transistors 114 and 116 constitute a balanced input circuit. A video intermediate frequency signal is then provided from each emitter to the detection circuit 117. This detection circuit 117 is constituted by a differential amplifier circuit.

なお、第2図に示すインターキヤリア音声中間
周波検波器12も同様にして映像検波回路11の
平衡入力回路と同様の回路が設けらている。
Note that the intercarrier audio intermediate frequency detector 12 shown in FIG. 2 is also provided with a circuit similar to the balanced input circuit of the video detection circuit 11.

以上のように、この発明によれば、映像中間周
波増幅器と映像検波回路とインターキヤリア音声
中間周波検波器と自動局部発振周波数制御器とを
含む信号処理回路において、映像中間周波増幅器
の出力と映像検波回路の入力、映像検波回路の出
力と自動局部発振周波数制御器の入力、映像中間
周波増幅器の出力とインターキヤリア音声中間周
波検波器の入力とをそれぞれ交流的に平衡となる
ように構成された差動増幅回路を介して接続する
ようにしたので、浮遊容量や電磁誘導などにより
帰還を生じたとしても、帰還成分は同相成分とな
るので、ループゲインを小さくすることができ、
発振を生じさせることなく安定に利得を上げるこ
とができる。特に、この発明による信号処理回路
をIC化した場合、交流的に平衡がとられている
ため、IC内の電源および接地配線に交流電流が
流れることがなく極めて安定な動作を図ることが
できる。
As described above, according to the present invention, in a signal processing circuit including a video intermediate frequency amplifier, a video detection circuit, an intercarrier audio intermediate frequency detector, and an automatic local oscillation frequency controller, the output of the video intermediate frequency amplifier and the video The input of the detection circuit, the output of the video detection circuit, the input of the automatic local oscillation frequency controller, the output of the video intermediate frequency amplifier, and the input of the intercarrier audio intermediate frequency detector are configured to be AC balanced, respectively. Since the connection is made through a differential amplifier circuit, even if feedback occurs due to stray capacitance or electromagnetic induction, the feedback component becomes the common mode component, so the loop gain can be reduced.
Gain can be stably increased without causing oscillation. In particular, when the signal processing circuit according to the present invention is implemented as an IC, it is balanced in terms of alternating current, so no alternating current flows through the power supply and ground wiring within the IC, and extremely stable operation can be achieved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の信号処理回路の概略ブロツク図
である。第2図はこの発明の一実施例の概略ブロ
ツク図である。第3図は第2図に示す映像中間周
波増幅器と映像検波回路にそれぞれ内蔵される平
衡出力回路および平衡入力回路の具体的な電気回
路図である。 図において、8は自動局部発振周波数制御器、
10は映像中間周波増幅器、11は映像検波回
路、12はインターキヤリア音声中間周波検波
器、102,103,114,116はトランジ
スタを示す。
FIG. 1 is a schematic block diagram of a conventional signal processing circuit. FIG. 2 is a schematic block diagram of one embodiment of the present invention. FIG. 3 is a specific electrical circuit diagram of a balanced output circuit and a balanced input circuit built into the video intermediate frequency amplifier and video detection circuit shown in FIG. 2, respectively. In the figure, 8 is an automatic local oscillation frequency controller;
10 is a video intermediate frequency amplifier, 11 is a video detection circuit, 12 is an intercarrier audio intermediate frequency detector, and 102, 103, 114, and 116 are transistors.

Claims (1)

【特許請求の範囲】 1 少なくとも映像中間周波増幅器と、映像検波
回路と、インターキヤリア音声中間周波検波器
と、自動局部発振周波数制御器とが単一の半導体
基板上に設けられてバイポーラモノリシツク半導
体集積回路によつて構成されるテレビジヨン受像
機の信号処理回路において、 前記映像中間周波増幅器と前記映像検波回路は
それぞれ平衡出力回路を含み、 前記映像検波回路と前記インターキヤリア音声
中間周波検波器と前記自動局部発振周波数制御器
は、それぞれ交流的に平衡な差動増幅回路で構成
された平衡入力回路を含み、 前記映像中間周波増幅器の出力と前記映像検波
回路の入力とを交流的に平衡接続し、前記映像検
波回路の出力と前記自動局部発振周波数制御器の
入力とを交流的に平衡接続し、前記映像中間周波
増幅器の出力と前記インターキヤリア音声中間周
波増幅器の入力とを交流的に平衡接続するように
したことを特徴とする、テレビジヨン受像機の信
号処理回路。
[Claims] 1. A bipolar monolithic semiconductor device in which at least a video intermediate frequency amplifier, a video detection circuit, an intercarrier audio intermediate frequency detector, and an automatic local oscillation frequency controller are provided on a single semiconductor substrate. In a signal processing circuit for a television receiver constituted by an integrated circuit, the video intermediate frequency amplifier and the video detection circuit each include a balanced output circuit, and the video detection circuit and the intercarrier audio intermediate frequency detector The automatic local oscillation frequency controller includes a balanced input circuit each composed of an AC balanced differential amplifier circuit, and connects the output of the video intermediate frequency amplifier and the input of the video detection circuit in an AC balanced manner. The output of the video detection circuit and the input of the automatic local oscillation frequency controller are connected in an alternating current balance, and the output of the video intermediate frequency amplifier and the input of the intercarrier audio intermediate frequency amplifier are connected in an alternating current balance. A signal processing circuit for a television receiver, characterized in that the signal processing circuit is connected to the television receiver.
JP56195406A 1981-12-03 1981-12-03 Television receiver signal processing circuit Granted JPS5896472A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56195406A JPS5896472A (en) 1981-12-03 1981-12-03 Television receiver signal processing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56195406A JPS5896472A (en) 1981-12-03 1981-12-03 Television receiver signal processing circuit

Publications (2)

Publication Number Publication Date
JPS5896472A JPS5896472A (en) 1983-06-08
JPH045309B2 true JPH045309B2 (en) 1992-01-31

Family

ID=16340574

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56195406A Granted JPS5896472A (en) 1981-12-03 1981-12-03 Television receiver signal processing circuit

Country Status (1)

Country Link
JP (1) JPS5896472A (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5432925A (en) * 1977-08-19 1979-03-10 Matsushita Electric Ind Co Ltd Signal processing circuit

Also Published As

Publication number Publication date
JPS5896472A (en) 1983-06-08

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