JPH0453150A - Method of testing integrated circuits - Google Patents

Method of testing integrated circuits

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Publication number
JPH0453150A
JPH0453150A JP2158204A JP15820490A JPH0453150A JP H0453150 A JPH0453150 A JP H0453150A JP 2158204 A JP2158204 A JP 2158204A JP 15820490 A JP15820490 A JP 15820490A JP H0453150 A JPH0453150 A JP H0453150A
Authority
JP
Japan
Prior art keywords
conductor
integrated circuit
lead
conductor lead
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2158204A
Other languages
Japanese (ja)
Inventor
Hiroyasu Nakada
中田 裕康
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2158204A priority Critical patent/JPH0453150A/en
Publication of JPH0453150A publication Critical patent/JPH0453150A/en
Pending legal-status Critical Current

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  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To improve the mechanical strength of an electrical connection between an integrated circuit and a conductive pattern and make it possible to use an insertion board repeatedly by using a conductor lead in a state in which it is reinforced by an insulation film and making it possible to move the connection between the conductor pattern and the conductor lead to the inside of the conductor lead. CONSTITUTION:In a great number of tape-shaped conductor leads 14 formed on the bottom surface of an insulation film 12, the inner end 14a thereof projects into a through hole 13, and an outer end 14b thereof projects from the outer end of the insulation film 12. The portion which is inner more than the outer end 14b is exposed inside through holes 15, 16. During a first use of an insulation board 4, the inner end 14a of each lead 14 of the film 12, a connection terminal 3 of an integrated circuit 1, and a portion 17 where the outer end 14b of each lead 14 is connected to a pattern 11 are TAB connected. Thus, a terminal 3 is connected to a pin 7 via the lead 14 and a pattern 11. During a second use of the board 4, the lead 14 is connected to the pattern 11 in a portion where the board 4 is exposed to the through hole 15. During a third use of the board 4, the lead 14 is connected to the pattern 11 in a portion where the board 4 is exposed to the transmission hole 16.

Description

【発明の詳細な説明】 〔概要〕 所定の絶縁基板に搭載した集積回路の特性を試験する方
法に関し、 集積回路を搭載する絶縁基板の繰り返し使用を可能なら
しめると共に、集積回路と絶縁基板との電気的接続の安
定化を目的とし、 中心部に集積回路収容部を有する絶縁基板には、集積回
路試験装置の測定端子と接続される多数の導体パターン
を該収容部の四方に形成し、内端部が集積回路の外部接
続端子に対向し中間部から外端部が該導体パターンに対
向する多数のテープ状導体リードを絶縁フィルムに形成
し、該絶縁フィルムには、該集積回路収容部に対向する
第1の透孔と該導体パターンに重なる部分で該導体リー
ドを表呈せしめる第2の透孔とを設け、該導体リードの
内端部を該絶縁フィルムの第1の透孔より突出せしめる
と共に、該導体リードの外端部を該絶縁フィルムの外縁
端より突出せしめ、該絶縁基板の第1回目の使用時には
、該導体リードの内端部を該集積回路の外部接続端子に
圧着すると共に、該導体リードの外端部を該導体パター
ンに圧着し、 該導体リードと該導体パターンとの圧着を剥離せしめ該
集積回路と該絶縁フィルムとを交換する該絶縁基板の第
2回目以降の繰り返し使用時には、その繰り返し毎に該
導体パターンと該導体リードとの圧着が、該第2の透孔
内に表呈する部分の該導体リードを用い、前回圧着時と
重ならないように順次該導体リードの長さ方向内側に移
動せしめることを特徴とし構成する。
[Detailed Description of the Invention] [Summary] This invention relates to a method for testing the characteristics of an integrated circuit mounted on a predetermined insulating substrate, which enables repeated use of the insulating substrate on which the integrated circuit is mounted, and also improves the relationship between the integrated circuit and the insulating substrate. For the purpose of stabilizing the electrical connection, an insulating substrate with an integrated circuit accommodating area in the center is provided with a large number of conductive patterns on all sides of the accommodating area to be connected to the measurement terminals of the integrated circuit testing equipment. A large number of tape-shaped conductor leads whose ends face the external connection terminals of the integrated circuit and whose middle parts and outer ends face the conductor pattern are formed on an insulating film, and the insulating film has a plurality of tape-shaped conductor leads arranged in the integrated circuit accommodating part. A first through-hole facing each other and a second through-hole exposing the conductor lead at a portion overlapping the conductor pattern are provided, and the inner end of the conductor lead protrudes from the first through-hole of the insulating film. At the same time, the outer end of the conductor lead is made to protrude beyond the outer edge of the insulating film, and when the insulating substrate is used for the first time, the inner end of the conductor lead is crimped to the external connection terminal of the integrated circuit. At the same time, the outer end of the conductor lead is crimped to the conductor pattern, the crimping between the conductor lead and the conductor pattern is peeled off, and the integrated circuit and the insulating film are replaced. During repeated use, the conductor pattern and the conductor lead are crimped each time using the conductor lead in the portion exposed in the second through hole, and the conductor lead is crimped in sequence so as not to overlap with the previous crimping. The structure is characterized in that it is moved inward in the length direction.

〔産業上の利用分野〕[Industrial application field]

本発明は集積回路の試験方法、特に集積回路を搭載する
絶縁基板の繰り返し使用を可能とし、集積回路と絶縁基
板との電気的接続の安定化法に関する。
The present invention relates to a method for testing an integrated circuit, and more particularly to a method for making it possible to repeatedly use an insulating substrate on which an integrated circuit is mounted and for stabilizing the electrical connection between the integrated circuit and the insulating substrate.

〔従来の技術〕[Conventional technology]

第5図は従来技術により試験用集積回路を絶縁基板に搭
載した模式側断面図である。
FIG. 5 is a schematic side sectional view of a test integrated circuit mounted on an insulating substrate according to the prior art.

第5図において、セラミック等にてなる回路基板2に外
部接続端子3.所望の回路素子を形成および搭載した集
積回路1は、絶縁基板(プリント配線板)4の中心部の
集積回路収容部5に収容し、絶縁基板4の上面に形成し
た多数の導体パターン6は、一端が絶縁基板4に植設し
たピン7に接続し他端にはワイヤ8を介して集積回路1
の端子3に接続させる。
In FIG. 5, a circuit board 2 made of ceramic or the like is provided with external connection terminals 3. The integrated circuit 1 on which desired circuit elements have been formed and mounted is housed in an integrated circuit accommodating portion 5 at the center of an insulating substrate (printed wiring board) 4, and a large number of conductor patterns 6 formed on the upper surface of the insulating substrate 4 are One end is connected to a pin 7 embedded in an insulating substrate 4, and the other end is connected to an integrated circuit 1 via a wire 8.
Connect to terminal 3 of the

ワイヤ8には、例えば直径100μ山の金線を使用する
For the wire 8, for example, a gold wire with a diameter of 100 μm is used.

集積回路収容部5は、集積回路1の四隅を支持する棚板
部9が形成された透孔を絶縁基板3に設けた構成であり
、集積回路収容部5に収容された集積回路Iは、多数の
ワイヤ8により絶縁基板3に保持されるようになる。
The integrated circuit accommodating portion 5 has a configuration in which a through hole in which a shelf board portion 9 for supporting the four corners of the integrated circuit 1 is formed is provided in the insulating substrate 3. The integrated circuit I accommodated in the integrated circuit accommodating portion 5 is It is held on the insulating substrate 3 by a large number of wires 8.

多数の製品の中からサンプリングによって抽出された試
験用集積回路lの特性は、絶縁基板4を集積回路試験装
置に搭載し、各ピン6には測定端子が接触する。
The characteristics of the test integrated circuit l extracted from a large number of products by sampling are determined by mounting the insulating substrate 4 on an integrated circuit testing device, and each pin 6 is in contact with a measurement terminal.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来技術による集積回路lの前記試験方法において、集
積回路1は機械的強度の弱いワイヤ8で保持されており
、絶縁基板4に外部からの振動や衝撃が加わると、その
影響を受は易いワイヤ8の一部が切断されることがあり
、切断されたワイヤ8は、手操作によってワイヤボンデ
ィングを遺り直さねばならないという煩わしさがあった
In the above-mentioned method for testing an integrated circuit 1 according to the prior art, the integrated circuit 1 is held by a wire 8 having low mechanical strength, and when external vibration or impact is applied to the insulating substrate 4, the wire is easily affected by the vibration or impact. A part of the wire 8 may be cut off, and the wire bonding of the cut wire 8 must be manually re-bonded, which is troublesome.

また、多数の導体パターン6を形成し、それぞれの導体
パターン6に対応するピン7を植設した絶縁基板4は、
繰り返し使用することなく1回だけの使い捨て、即ち使
用済みワイヤ8の除去が極めて煩わしいため使い捨てで
あった。
In addition, the insulating substrate 4 has a large number of conductor patterns 6 formed thereon and has pins 7 corresponding to each conductor pattern 6 embedded therein.
It is disposable only once without being used repeatedly, that is, it is disposable because removing the used wire 8 is extremely troublesome.

本発明の目的は、ワイヤ8を使用することによる前記切
断をなくすと共に、絶縁基板4を繰り返し使用できるよ
うにすることである。
An object of the present invention is to eliminate the above-mentioned cutting caused by using the wire 8 and to enable the insulating substrate 4 to be used repeatedly.

〔課題を解決するための手段〕[Means to solve the problem]

本発明方法はその実施例を示す第1図によれば、中心部
に集積回路収容部5を有する絶縁基板4には、集積回路
試験装置の測定端子と接続される多数の導体パターンI
Iを該収容部5の四方に形成し、内端部が集積回路1の
外部接続端子3に対向し中間部から外端部が導体パター
ン11に対向する多数のテープ状導体リード14を絶縁
フィルム12に形成し、 絶縁フィルム12には、集積回路収容部5に対向する第
1の透孔13と導体パターンIIに重なる部分で導体リ
ード14を表呈せしめる第2の透孔15.16とを設け
、 導体リード14の内端部を絶縁フィルム12の第1の透
孔13より突出せしめると共に、導体リードI4の外端
部を絶縁フィルム12の外縁端より突出せしめ、 絶縁基板4の第1回目の使用時には、導体り一ド14の
内端部を該集積回路1の外部接続端子3に圧着すると共
に、導体リード14の外端部を導体パターン11に圧着
し、 導体リード14と導体パターン11との圧着を剥離せし
め集積回路1と絶縁フィルム12とを交換する絶縁基板
4の第2回目以降の繰り返し使用時には、その繰り返し
毎に導体パターン11と導体リード14との圧着が、第
2の透孔15.16内に表呈する部分の導体リード14
を用い、前回圧着時と重ならないように順次導体リード
14の長さ方向内側に移動せしめることを特徴とする集
積回路の試験方法である。
According to FIG. 1, which shows an embodiment of the method of the present invention, an insulating substrate 4 having an integrated circuit accommodating portion 5 in the center has a large number of conductor patterns I connected to measurement terminals of an integrated circuit testing device.
A large number of tape-shaped conductor leads 14 are formed on all sides of the housing part 5, and a large number of tape-shaped conductor leads 14 whose inner ends face the external connection terminals 3 of the integrated circuit 1 and whose middle and outer ends face the conductor pattern 11 are covered with an insulating film. 12, and the insulating film 12 has a first through hole 13 facing the integrated circuit accommodating portion 5 and a second through hole 15, 16 through which the conductor lead 14 is exposed in a portion overlapping with the conductor pattern II. The inner end of the conductor lead 14 is made to protrude from the first through hole 13 of the insulating film 12, and the outer end of the conductor lead I4 is made to protrude from the outer edge of the insulating film 12. When using the conductor lead 14, the inner end of the conductor lead 14 is crimped to the external connection terminal 3 of the integrated circuit 1, and the outer end of the conductor lead 14 is crimped to the conductor pattern 11. When the insulating substrate 4 is used repeatedly after the second time, in which the integrated circuit 1 and the insulating film 12 are peeled off and the insulating film 12 is replaced, the crimping between the conductor pattern 11 and the conductor lead 14 is removed by the second transparent The portion of the conductor lead 14 exposed within the hole 15.16
This integrated circuit testing method is characterized by sequentially moving the conductor leads 14 inward in the length direction so as not to overlap with the previous crimping.

〔作用〕[Effect]

上記手段によれば、絶縁フィルムに形成した導体リード
の一端を集積回路に接続し、絶縁基板の導体パターンに
導体リードの他端を接続し、絶縁基板の繰り返し使用に
際して、絶縁フィルムには導体リードの中間部を表呈せ
しめる透孔を設け、導体パターンと導体リードとの接続
部を導体リード内側へ移動可能とした。
According to the above means, one end of the conductor lead formed on the insulating film is connected to the integrated circuit, the other end of the conductor lead is connected to the conductor pattern of the insulating substrate, and when the insulating substrate is repeatedly used, the conductor lead is attached to the insulating film. A through hole is provided to expose the middle part of the conductor pattern, and the connecting part between the conductor pattern and the conductor lead can be moved inside the conductor lead.

即ち、本発明では機械的強度の弱い導体リードを絶縁フ
ィルムで補強して使用し、導体パターンと導体リードと
の接続部を導体リードの内側へ移動可能としたことによ
って、集積回路と導体パターンとの電気的接続の機械的
強度を改善し、絶縁基板の繰り返し利用が可能になる。
That is, in the present invention, a conductor lead with low mechanical strength is reinforced with an insulating film, and the connection part between the conductor pattern and the conductor lead can be moved inside the conductor lead, thereby making it possible to connect the integrated circuit and the conductor pattern. This improves the mechanical strength of the electrical connections and allows the insulating substrate to be used repeatedly.

〔実施例〕〔Example〕

以下に、図面を用いて本発明の実施例に係わる集積回路
の試験方法を説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for testing an integrated circuit according to an embodiment of the present invention will be described below with reference to the drawings.

第1図は本発明方法の一実施例によって試験用絶縁基板
に搭載した集積回路の模式平面図(イ)とその断面図(
ロ)、第2図は第1図に示す絶縁基板の模式平面図、第
3図は第1図に示す絶縁フィルムの模式下面図、第4図
は第3回目の使用時の絶縁基板に搭載した集積回路の模
式断面図である。
Figure 1 shows a schematic plan view (A) and a cross-sectional view (A) of an integrated circuit mounted on an insulating substrate for testing according to an embodiment of the method of the present invention.
b), Figure 2 is a schematic plan view of the insulating substrate shown in Figure 1, Figure 3 is a schematic bottom view of the insulating film shown in Figure 1, and Figure 4 is mounted on the insulating substrate during the third use. FIG. 2 is a schematic cross-sectional view of an integrated circuit.

第1図は繰り返し使用される絶縁基板4の第1回目の使
用時であり、集積回路試験装置の測定端子と集積回路l
とを電気的に接続するための絶縁基板4は、その詳細を
第2図に示す如く、中心部に集積回路収容部5を設け、
収容部5から少し離れた多数の導体パターン11を四方
に向けて設け、各導体パターン11は絶縁基板4に植設
したピン7に接続し、収容部5の四隅には集積回路lを
支持する棚板部9を有する。導体パターン11は、例え
ば厚さ0.1mmの銅に金めっきする。
Figure 1 shows the first use of the insulating substrate 4, which is used repeatedly, and shows the measurement terminals of the integrated circuit testing equipment and the integrated circuit
As shown in detail in FIG. 2, the insulating substrate 4 for electrically connecting the
A large number of conductor patterns 11 are provided slightly away from the accommodating part 5 in all directions, each conductor pattern 11 is connected to a pin 7 implanted in the insulating substrate 4, and integrated circuits l are supported at the four corners of the accommodating part 5. It has a shelf part 9. The conductive pattern 11 is formed by plating copper with a thickness of 0.1 mm, for example, with gold.

例えばポリイミドにてなる角型の絶縁フィルム12は、
その詳細を第3図に示す如く、収容部5に対向する第1
の透孔13が中心部にあけられており、四方の各外縁端
近傍に長方形の第2の透孔15と16があけられてなる
。そして、絶縁フィルム12の下面に形成された多数の
テープ状導体リード14は、内端部14aが透孔I3内
に突出し、外端部14bが絶縁フィルム12の外縁端よ
り突出し、外端部14bより内側部分が透孔15.16
内に表呈する。
For example, the square insulating film 12 made of polyimide is
As the details are shown in FIG. 3, the first
A through hole 13 is formed in the center, and rectangular second through holes 15 and 16 are formed near each of the four outer edges. A large number of tape-shaped conductor leads 14 formed on the lower surface of the insulating film 12 have an inner end 14a protruding into the through hole I3, an outer end 14b protruding from the outer edge of the insulating film 12, and an outer end 14b. The inner part is through hole 15.16
express within.

かかる導体パターン■4は、例えば成形前のポリイミド
フィルムに貼着した厚さ μmの金箔をエツチングし形
成する。
The conductor pattern (4) is formed, for example, by etching a μm-thick gold foil adhered to a polyimide film before molding.

絶縁基板4の第1回目の使用時において、絶縁フィルム
12の各導体リードI4の内端部14aと集積回路1の
接続端子3および、各導体リード14の外端部14bと
導体パターン11との接続部I7は、TAB (Tap
e Automated Bonding)接続する。
When the insulating substrate 4 is used for the first time, the inner end 14a of each conductor lead I4 of the insulating film 12 and the connection terminal 3 of the integrated circuit 1 and the outer end 14b of each conductor lead 14 and the conductor pattern 11 are connected. The connection part I7 is TAB (Tap
e Automated Bonding) connection.

従って、各接続端子3は導体リード14.導体パターン
11を介してピン7に接続されるようになる。
Therefore, each connection terminal 3 has a conductor lead 14. It comes to be connected to the pin 7 via the conductor pattern 11.

次いで、絶縁基板4の第2回目の使用時には、透孔15
内に表呈する部分で導体リード14を導体パターン11
にTAB接続し、絶縁基板4の第3回目の使用時には、
透孔16内に表呈する部分で導体り−ド14を導体パタ
ーン11にTAB接続する。その際、絶縁フィルム12
はその何便用してもよいが、第3図に記入したL型破線
Aまたは破線Bの延長線に沿って絶縁フィルムI2を切
断すれば、前回使用時における導体リード14の残滓が
導体パターン11に被着していても、その影響を受ける
ことな(新規導体リードI4の接続が可能である。
Next, when the insulating substrate 4 is used for the second time, the through holes 15 are
The conductor lead 14 is connected to the conductor pattern 11 at the portion exposed inside.
When using the insulating board 4 for the third time,
The conductive wire 14 is connected to the conductive pattern 11 by TAB at the portion exposed inside the through hole 16. At that time, the insulating film 12
However, if you cut the insulating film I2 along the extended line of the L-shaped broken line A or the broken line B drawn in FIG. 11, the new conductor lead I4 can be connected without being affected by it.

第4図において、絶縁基板4の第3回目の使用時である
絶縁フィルム12は破線Bの延長線に沿って切断し、そ
の外縁端から適当長さだけ突出するように導体リード1
4を切断した状態であり、符号18はその導体リード1
4と接続端子3.導体パターンIIとのTAB接続部で
ある。
In FIG. 4, the insulating film 12 used for the third time of the insulating substrate 4 is cut along the extended line of the broken line B, and the conductor leads 12 are cut so as to protrude by an appropriate length from the outer edge of the insulating film 12.
4 is cut, and the code 18 is the conductor lead 1.
4 and connection terminal 3. This is a TAB connection part with conductor pattern II.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明方法によれば、従来のワイヤ
に替え絶縁フィルムに形成した導体リードを使用したこ
とによって、集積回路と導体パターンとの電気的接続の
機械的強度を改善し、導体パターンと導体リードとの接
続部を導体リードの内側へ移動可能としたことによって
、導体パターンの形成された絶縁基板の繰り返し利用を
可能にした。
As explained above, according to the method of the present invention, by using conductor leads formed on an insulating film instead of conventional wires, the mechanical strength of the electrical connection between the integrated circuit and the conductor pattern is improved, and the conductor By making the connecting portion between the conductor lead and the conductor lead movable inside the conductor lead, it is possible to repeatedly use the insulating substrate on which the conductor pattern is formed.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明方法の一実施例の説明図、第2図は第1
図に示す絶縁基板、 第3図は第1図に示す絶縁フィルム、 第4図は絶縁基板の第3回目の使用時の説明図、第5図
は従来技術の説明図、 である。 図中において、 1よ集積回路、 3は外部接続端子、 4は絶縁基板、 5は集積回路収容部、 11は導体パターン、 12は絶縁フィルム、 13は第1の透孔、 14は導体リード、 14aは導体リード内端部、 14bは導体リード外端部、 15、16は第2の透孔、 を示す。 4絶縁基択 第 1 図 第1図にホナ身ジ1靭反 第 l 図 第1図に示す東すゑフィルへ 第 図
FIG. 1 is an explanatory diagram of one embodiment of the method of the present invention, and FIG.
FIG. 3 is an insulating film shown in FIG. 1, FIG. 4 is an explanatory diagram of the insulating substrate used for the third time, and FIG. 5 is an explanatory diagram of the prior art. In the figure, 1 is an integrated circuit, 3 is an external connection terminal, 4 is an insulating substrate, 5 is an integrated circuit housing part, 11 is a conductor pattern, 12 is an insulating film, 13 is a first through hole, 14 is a conductor lead, 14a is an inner end of the conductor lead, 14b is an outer end of the conductor lead, and 15 and 16 are second through holes. 4. Insulation standard selection 1. Figure 1.

Claims (1)

【特許請求の範囲】  中心部に集積回路収容部(5)を有する絶縁基板(4
)には、集積回路試験装置の測定端子と接続される多数
の導体パターン(11)を該収容部(5)の四方に形成
し、 内端部が集積回路(1)の外部接続端子(3)に対向し
中間部から外端部が該導体パターン(11)に対向する
多数のテープ状導体リード(14)を絶縁フィルム(1
2)に形成し、 該絶縁フィルム(12)には、該集積回路収容部(5)
に対向する第1の透孔(13)と該導体パターン(11
)に重なる部分で該導体リード(14)を表呈せしめる
第2の透孔(15、16)とを設け、 該導体リード(14)の内端部を該絶縁フィルム(12
)の第1の透孔(13)より突出せしめると共に、該導
体リード(14)の外端部を該絶縁フィルム(12)の
外縁端より突出せしめ、 該絶縁基板(4)の第1回目の使用時には、該導体リー
ド(14)の内端部を該集積回路(1)の外部接続端子
(3)に圧着すると共に、該導体リード(14)の外端
部を該導体パターン(11)に圧着し、該導体リード(
14)と該導体パターン(11)との圧着を剥離せしめ
該集積回路(1)と該絶縁フィルム(12)とを交換す
る該絶縁基板(4)の第2回目以降の繰り返し使用時に
は、その繰り返し毎に該導体パターン(11)と該導体
リード(14)との圧着が、該第2の透孔(15、16
)内に表呈する部分の該導体リード(14)を用い、前
回圧着時と重ならないように順次該導体リード(14)
の長さ方向内側に移動せしめることを特徴とする集積回
路の試験方法。
[Claims] An insulating substrate (4) having an integrated circuit accommodating portion (5) in the center.
), a large number of conductor patterns (11) to be connected to the measurement terminals of the integrated circuit testing device are formed on all sides of the housing part (5), and the inner end is connected to the external connection terminal (3) of the integrated circuit (1). ), and a large number of tape-shaped conductor leads (14) whose middle part and outer end face the conductor pattern (11) are covered with an insulating film (1).
2), and the insulating film (12) has the integrated circuit housing portion (5).
The first through hole (13) facing the conductor pattern (11)
), and second through holes (15, 16) are provided to expose the conductor lead (14) at a portion overlapping the conductor lead (14), and the inner end of the conductor lead (14) is connected to the insulating film (12).
), and the outer end of the conductor lead (14) is made to protrude from the outer edge of the insulating film (12), and the first through hole (13) of the insulating substrate (4) In use, the inner end of the conductor lead (14) is crimped to the external connection terminal (3) of the integrated circuit (1), and the outer end of the conductor lead (14) is attached to the conductor pattern (11). Crimp the conductor lead (
14) and the conductor pattern (11) is peeled off and the integrated circuit (1) and the insulating film (12) are replaced. Each time, the conductor pattern (11) and the conductor lead (14) are crimped through the second through hole (15, 16).
) Using the conductor lead (14) of the part exposed in
A method for testing an integrated circuit, characterized by moving the circuit inward in the length direction.
JP2158204A 1990-06-15 1990-06-15 Method of testing integrated circuits Pending JPH0453150A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2158204A JPH0453150A (en) 1990-06-15 1990-06-15 Method of testing integrated circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2158204A JPH0453150A (en) 1990-06-15 1990-06-15 Method of testing integrated circuits

Publications (1)

Publication Number Publication Date
JPH0453150A true JPH0453150A (en) 1992-02-20

Family

ID=15666560

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2158204A Pending JPH0453150A (en) 1990-06-15 1990-06-15 Method of testing integrated circuits

Country Status (1)

Country Link
JP (1) JPH0453150A (en)

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