JPH0453323U - - Google Patents
Info
- Publication number
- JPH0453323U JPH0453323U JP9583690U JP9583690U JPH0453323U JP H0453323 U JPH0453323 U JP H0453323U JP 9583690 U JP9583690 U JP 9583690U JP 9583690 U JP9583690 U JP 9583690U JP H0453323 U JPH0453323 U JP H0453323U
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- signal
- filter
- division ratio
- frequency division
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Filters That Use Time-Delay Elements (AREA)
Description
第１図は本考案に係るフイルタ回路の構成例を
示す図、第２図はスイツチト・キヤパシタ・フイ
ルタを説明する図である。
１……ＳＣフイルタ、２……ローパスフイルタ
、４……分周器、５……ＣＰＵ。
FIG. 1 is a diagram showing an example of the configuration of a filter circuit according to the present invention, and FIG. 2 is a diagram illustrating a switched capacitor filter. 1...SC filter, 2...Low pass filter, 4...Frequency divider, 5...CPU.
Claims (1)
ツトオフ周波数ｆＸが、ｆＸ＝ｆｃＮで制御され
、導入した信号を瀘波するスイツチト・キヤパシ
タ方式の第１フイルタと（Ｎは定数）、 第１フイルタの折り返し現象防止用のフイルタ
特性で入力信号Ｓｉを瀘波し、その瀘波信号を第
１フイルタへ加えるローパスフイルタ２と、 分周比ｎにて、導入した基準周波数ｆＲの信号
を分周し、周波数ｆｃ＝ｆＲｎのクロツク信号を
出力する分周器と、 任意のカツトオフ周波数ｆＡを指令する信号を
導入し、 ｎ＝（１Ｎ）・（ｆＲＦＡ） の演算
を行つて分周比ｎを算出し、前記分周器の分周比
ｎを制御するＣＰＵと、 を備えたフイルタ回路。[Claims for Utility Model Registration] The cutoff frequency fX is controlled by the applied clock signal of frequency fc as fX=fcN, and a first filter of the switched capacitor type filters the introduced signal (N is a constant). , a low-pass filter 2 that filters the input signal Si using the filter characteristics for preventing aliasing of the first filter and applies the filtered signal to the first filter, and a signal of the reference frequency fR introduced at a frequency division ratio n. Introducing a frequency divider that outputs a clock signal with frequency fc = fRn and a signal that commands an arbitrary cutoff frequency fA, and calculates the frequency division ratio by calculating n = (1N) / (fRFA). a CPU that calculates the frequency division ratio n of the frequency divider and controls the frequency division ratio n of the frequency divider.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9583690U JPH0453323U (en) | 1990-09-12 | 1990-09-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9583690U JPH0453323U (en) | 1990-09-12 | 1990-09-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0453323U true JPH0453323U (en) | 1992-05-07 |
Family
ID=31834889
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9583690U Pending JPH0453323U (en) | 1990-09-12 | 1990-09-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0453323U (en) |
-
1990
- 1990-09-12 JP JP9583690U patent/JPH0453323U/ja active Pending
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