JPH0453324A - Method of pulling into synchronism - Google Patents

Abstract

PURPOSE:To pull-in frame synchronization in a short time by continuing the accumulation which judges the acquisition of frame synchronization even after the occurrence of cycle slip without canceling the accumulation due to the occurrence of the cycle slip. CONSTITUTION:An adder circuit 14 obtains a 1st accumulating value, in which an initial value is started from 0, 1 is incremented when a unique word is detected at the prescribed location of a frame and 1 is decremented when the unique word is not detected at the prescribed location of the frame. Then the absolute value of the 1st accumulating value is limited at a 1st prescribed value decided by a delay stage number of a delay circuit 12, an adder circuit 17 obtains a 2nd accumulating value by accumulating the absolute value of the 1st accumulating value and when the 2nd accumulating values are 2nd prescribed values or above, it is judged that frame synchronization is pulled-in. Thus, in the case of the occurrence of a cycle slip, frame synchronization is pulled-in a shorter time than that of a conventional synchronization pulling-in method.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a synchronization pull-in method, for example to a frame synchronization pull-in method for an Inmarsat 5TD-C system.

B1 Summary of the Invention The synchronization pull-in method according to the present invention is a synchronization pull-in method that pulls in frame synchronization using a unique word placed at a predetermined position of a frame, the method starts with an initial value of 0,
At a predetermined position in the frame, when a unique word is detected, +1 is added, and when no unique word is detected, -1 is added to obtain a first cumulative value.
The absolute value of the cumulative value of is limited by a first predetermined value, and the first
A second cumulative value is obtained by accumulating the absolute value of the cumulative value of
By determining that frame synchronization has been engaged when the cumulative value of It is designed to be retractable.

C0 Conventional technology International maritime communications, that is, communications between ships and land or between ships, mainly rely on short waves, but they are limited in terms of communication time zones and coverage, as well as in terms of communication quality and line capacity. It wasn't enough. Therefore,
The so-called Inmarsat (INMARSAT):
International MaritimeSat
elite Organization) in 1979
The Maritime Satellite Communication System (hereinafter referred to as the Inmarsat system) began operation in 1982 in the Atlantic and Pacific Oceans.

The Inmarzat system relays stationary or mobile satellites to communicate between ships and land, or between ships, and uses a network control station (NC3: Network Co., Ltd.) that controls satellites, lines, and calls (traffic).
Ordination 5tation), Coastal Earth Station (CES) on the land side
5tation), shipside ship earth station (ME
S: Mobile Earth 5taLion)
Consists of etc.

Furthermore, the above-mentioned ship earth stations are classified as follows according to the services provided.

Using a parabolic antenna with a diameter of about 1.2 m, telephone,
Low-speed data communication such as telex, voice band data communication,
Standard A station capable of 56 Kbps high-speed data communication (ship to land), targeting small ships, miniaturization of shipboard antennas (short pack fire antenna with a diameter of approximately 0.4 m),
Aiming at economicalization, standard B stations capable of low-speed data communication such as telephone and telex, and short hack fire antennas, dipole antennas, etc. are used for small ships), distress safety communication, telex with a focus on distress safety communication. Standard 0 stations capable of low-speed data communication such as Standard A above
There is a standard station that has a parabolic antenna with a diameter of 2.5 to 3 m, which is larger than the station, and is capable of high-speed data communication in oil rigs, multiplex telephone transmission, etc.

By the way, in the Inmarsat system, the frequency used between the satellite and the ship's earth station is 1.6/1゜5GH.
The 6/4 GHz band is used between satellites and coastal earth stations, and so-called demand assignment is used to allocate lines when a call (traffic) occurs.
ned) method is used. Telephony also uses frequency modulation/time division multiple access (F, M/TDMA).
: Frequency Modulation/
Time Division Multiple Ac
For low-speed data such as telex, binary phase keying (BPSK) is used.
TDM (TD
M: Time Division Multiplex
) method (land → ship) and TDMA method (ship → land) are used.

Here, the above-mentioned Inmarsat Soto standard 0 station system (hereinafter referred to as the Inmarsat 5TD-C system) will be briefly explained.

The INMARSAT) STD-C system uses a DCE (DCE) that interfaces with the satellite, as shown in Figure 4.
: Data C1rcuit terminati
ng Equipment) 50 and a DTE (Data Termi) with a user interface.
When transmitting message (data) from a ship to land (once a month, for example), the DTE 80 converts data from a terminal, such as a word processor, into a predetermined format, and then the DCE 50 converts the data into a predetermined format. error correction encoding,
The signal is subjected to BPSK modulation, etc. and transmitted to the satellite in the 1.5 GHz band. The signal is then converted to the 4 GHz band by the satellite, amplified, and transmitted to a coastal earth station.

Furthermore, when sending messages (data) from land to a ship, the data is transmitted from a coastal earth station to a satellite in the 6 GHz band. Then, after being converted into a 1.5 GHz band by the satellite, it is amplified and transmitted to the DCE 50 of the ship's earth station. Then, the DCE 50 performs BPSK demodulation, error correction, etc., and reproduces the data.
80 to the terminal.

Specifically, as shown in FIG. 4, the DCE 50 uses an antenna (ANT) 51, a transmission system circuit 60, a reception system circuit 70, and the antenna 51 by switching between transmission and reception. a local oscillation circuit (SYNTH) 53 that supplies carrier waves and clocks to the transmission system circuit 60 and reception system circuit 70;
It is comprised of a controller 54 that handles access control and messages.

The transmission system circuit 60 includes a scrambler 61 that performs pseudorandom encoding on data from the controller 54 for power spreading, a convolutional encoder 62 that performs convolutional encoding for error correction, and a convolutional encoder 62 that performs burst error correction. An interleave circuit 63 without interleaving for converting into random errors, and a BPSK modulator 6 that performs two-phase phase modulation.
4, a multiplier 65 that converts a signal after BPSK modulation into a transmission frequency signal, and a high power amplifier (HPA) 6 (i) that amplifies the transmission signal.

On the other hand, the receiving system circuit 70 includes a low noise amplifier (LNA) 71 that amplifies the received signal from the antenna 51, a multiplier 72 that converts the received signal into an intermediate frequency signal,
An IF circuit 73 that amplifies intermediate frequency signals, a BPSK demodulator 74 that demodulates binary phase modulation, a frame synchronization circuit 75 that pulls in TDM frame synchronization, and a circuit that returns interleaved data to its original state. It is composed of an interleave circuit 76, a Viterbi decoder 77 that performs error correction on convolutionally encoded data, and a descrambler 78 that restores pseudorandomly encoded data to its original state.

By the way, in the Inmarsat I-S TDC system, data is sent in frame units, and as shown in FIG. 5, one row consists of 162 symbols, and one frame is composed of 64 rows. In other words, a frame consists of 10368 (162x64) symbols,
A so-called unique word Wh<W is placed in the first and second symbol positions of each row.

W,,W,W,,”...W63Wb3) are arranged,
Data is placed in the next 160 symbol positions. −
Frame synchronization is achieved by detecting these unique words WII.

Specifically, as shown in FIG. 6, the main part of the frame synchronization circuit 75 synchronizes the symbol X received at the first and second symbol positions of each row of the frame and the unique word Wk (k = A multiplication circuit 91 that calculates the product of 0 to 63), and an addition circuit 92 that accumulates this multiplication value.
and a delay circuit 93, and A that calculates the absolute value of this cumulative value.
BS circuit 94.

That is, the multiplication circuit 91 includes this frame synchronization circuit 7.
The first and second symbols Xk of each row of the frame detected by the circuit at the front stage of the main part of 5 are sequentially supplied via the terminal 90 from the beginning of the frame. The multiplier circuit 91 multiplies the symbol X6 by the unique word Wk sequentially supplied via the terminal 95, and outputs the multiplied value to the adder circuit 92. Specifically, this multiplication circuit 91 is
“1” when symbol x3 is equal to unique word Wk
", and when the symbol x6 is different from the unique word W, it outputs "-1°'.

Addition circuit 92 adds the multiplication value from multiplication circuit 91 to the previous addition value from delay circuit 93 . That is, the addition circuit 92 and the delay circuit 93 constitute an accumulation circuit. for example,
The output of adder circuit 92 increases by .degree.'1" when symbol X3 is equal to unique word Wk, and decreases by "1" when symbol XII differs from unique word W.

The cumulative value from the adding circuit 92 accumulated in this way is
The absolute value is taken in the ABS circuit 94 and sent to the terminal 96.
is output from.

Then, when the absolute value of the cumulative value from the ABS circuit 94 is equal to or greater than a predetermined value, it is assumed that frame synchronization has been correctly established, and data reception is performed.

By the way, demodulation (synchronous detection) in the BPSK modulation method
compares the phase of the reference carrier wave and the received signal,
For example, if the phase is in-phase, it is set to 1"', and if it is out of phase, it is set to '0°'. By the way, in satellite communications using the TDMA system, the carrier wave that is the reference for this demodulation is used for a short time at the beginning of the frame, for example. (The so-called carrier recovery code (CR: Carrier Rec
obtained by reproducing the ``overy''. Therefore, if the CNR deteriorates due to line conditions such as fading,
A so-called cycle slip occurs in which the phase of a reference reproduced carrier wave is pulled into an incorrect phase, and the received symbol may be inverted. When this cycle slip occurs during frame synchronization pull-in, the output of the multiplication circuit 91 is
As shown in FIG. 7, the cycle is reversed before and after a cycle slip occurs. Then, subtraction of the absolute value of the accumulated value from the ABS circuit 94 accumulated before the occurrence of the cycle slip starts, and after the absolute value of the accumulated value becomes 0'', the accumulation for frame synchronization pull-in is resumed. As a result, there is a problem in that it takes time for the absolute value of the cumulative value to reach a predetermined value, and it takes time to pull in frame synchronization.

D3 Problems to be Solved by the Invention As described above, in the conventional synchronization pull-in method, if a cycle slip occurs during frame synchronization pull-in, there is a problem that it takes time to pull-in frame synchronization.

The present invention has been made in view of the above circumstances, and provides a synchronization pull-in method that allows frame synchronization pull-in to be performed in a shorter time than conventional methods even if a cycle slip occurs during frame synchronization pull-in. The purpose is to provide.

81 Means for Solving the Problems In order to solve the above problems, the synchronization pull-in method according to the present invention is a synchronization pull-in method that pulls in frame synchronization using a unique word placed at a predetermined position of a frame, The value is started from O, and at a predetermined position in the frame, when a unique word is detected, 1 is added, and when no unique word is detected, -1 is added to obtain the first cumulative value, and the first cumulative value is obtained. The absolute value of the first cumulative value is limited by a first predetermined value, the absolute value of the first cumulative value is accumulated to obtain a second cumulative value, and the second cumulative value is a second predetermined value. The feature is that when the value is greater than or equal to the value, it is determined that the frame synchronization is engaged.

F6 action In the synchronization pull-in method according to the present invention, +1 is added when a unique word is detected, and -1 is added when a unique word is not detected to obtain a first cumulative value. The absolute value of the cumulative value of 1 is limited by a first predetermined value. Then, a second cumulative value is determined by accumulating the absolute values of the first cumulative values, and when the second cumulative value is equal to or greater than a second predetermined value, it is determined that frame synchronization is being engaged.

G. Example Hereinafter, an example of the synchronization pull-in method according to the present invention will be described with reference to the drawings.

In this embodiment, the synchronization pull-in method according to the present invention is applied to, for example, the above-mentioned Inmarsat 5TD-C system. That is, it is applied to the frame synchronization circuit 75 shown in FIG. 4 described above, and FIG. It corresponds to this.

By the way, as shown in FIG. 5 mentioned above, the frame of the INMARSAT L-S TDC system consists of 62 symbols per row, and one frame is composed of 64 rows. , the so-called unique word W□(W, W, , W, W, . . . ) is placed in the second symbol position.
W b 3W b 3) is arranged, and data is arranged in the following 160 symbols. By detecting these unique words Wll, frame synchronization (frame sync) is established.

First, the main parts of the frame synchronization circuit shown in FIG. 1 will be explained.

As shown in FIG. 1, the main parts of the frame synchronization circuit are the symbol positions received at the first and second symbol positions of each row of the frame and the unique word W□(k-
0 to 63); a delay circuit 12 that delays the multiplication value; an addition circuit 13 that subtracts the delayed multiplication value from the multiplication value from the multiplication circuit 11; An addition circuit 14 and a delay circuit 15 for accumulating the added value from the circuit 13, an ABS circuit 16 for calculating the absolute value of the accumulated value, and an adding circuit 17 and delay for accumulating the absolute value of the accumulated value. The first and second symbols X of each row of the frame detected by the circuit at the front stage of the main part of this frame circuit are sequentially supplied via terminal 1 from the beginning of the frame. It looks like this.

The multiplier circuit 11 multiplies the symbol X sequentially supplied via the terminal 1 by the unique word W□ sequentially supplied via the terminal 2, and the multiplication value is used by the delay circuit 12 and the adder circuit. Send to 13th. Specifically, the multiplication circuit 11 outputs '1°' when the symbol XI+ is equal to the unique word W□, and outputs 1lil+ when the symbol X5 differs by the unique word Wk.

Further, the delay circuit 12 may include, for example, five
The multiplication value from the multiplier circuit 11 is transmitted in five rows, that is, 810
The signal is delayed by (162×5) symbols and sent to the adder circuit 13.

The adder circuit 13 subtracts the output of the delay circuit 12 from the output of the multiplier circuit 11, and sends the subtraction result (added value) to the adder circuit 14.

The adding circuit 14 adds the added value from the adding circuit 13 to the previous added value from the delay circuit 5. That is, the adder circuit 14 and the delay circuit 15 constitute an accumulation circuit. For example, the output of the adder circuit 14 is
When the output of “■” increases by °′1”, the adder circuit 1
When the output of 3 is '°-1'', the output decreases by 1''.

The cumulative value from the adder circuit 14 accumulated in this way is
The absolute value is taken in the ABS circuit 16, and the absolute value of this accumulated value is sent to the addition circuit 17.

Like the addition circuit 14, the addition circuit 17 forms an accumulation circuit together with the delay circuit 18, and calculates the cumulative value of the absolute value of the cumulative value from the ABS circuit 16.

The synchronization pull-in method according to the present invention determines that frame synchronization has been correctly pulled in when the output of the adder circuit 17 exceeds a predetermined value.

Specifically, the initial values of the delay circuits 12a to 12e are
0'', and when the symbols X at the first and second symbol positions in each row of the frame are consecutively equal to the unique word W, the output of the multiplier circuit 11 is as shown in FIG. It becomes "1'" continuously. Then, the addition circuit 13
, from the current output of the multiplier circuit 11 to the multiplier circuit 11
As shown in FIG. When the value is less than a predetermined value, for example, ``5'', it is increased by ``pips'', and thereafter it is fixed at ``5''.

As a result, the output of the adder circuit 17 that calculates the cumulative value of the absolute value of the cumulative value is 1, 3 (
=1+2), 6 (=3+3), 10 (・6
+4), 15 (・1015), 20 (=15+
5), and thereafter the value obtained by adding "5"...

The synchronization pull-in method according to the present invention determines that frame synchronization has been correctly pulled in when the output of the adder circuit 17 is equal to or higher than a second predetermined value.

For example, the frame synchronization pull-in of the synchronization pull-in method according to the present invention corresponds to the frame synchronization pull-in judgment criterion in the conventional synchronization pull-in method shown in the bottom column of FIG. When the determination criterion "70" or higher is reached, it is determined that frame synchronization has been correctly established.

By the way, as described above, when the line condition deteriorates and the CNR deteriorates due to fading, for example, and a so-called cycle slip occurs, the received symbol is inverted. If this cycle slip occurs during frame synchronization pull-in,
As shown in FIG. 3, the output of the multiplication circuit 11 is inverted before and after a cycle slip occurs.

In this case, as shown in FIG. 3, the output of the ABS circuit 16 decreases by "1" from the time when the cycle slip occurs to 0, and then increases to "I I" until it becomes "5" again.
Increase by I.

As a result, the output of the adder circuit 17 increases at a rate of 4.3.2.1.0 from the time when the cycle slip occurs.
■, 2.3.4.5, 5 continues...°'. That is, even if a cycle slip occurs, the output of the adder circuit 17, which is the frame synchronization pull-in judgment criterion, will be "39.42.44.45.45." from the time the cycle slip occurs, as shown in FIG. 46.48.51
．． 55, the value obtained by adding "5'" thereafter becomes "...", and although the rate of increase temporarily decreases, the value does not decrease.

That is, in the synchronization pull-in method according to the present invention, the output of the adder circuit 17, that is, the cumulative value for determining frame synchronization pull-in, is not canceled by the occurrence of a cycle slip, but continues to accumulate even after the cycle slip occurs. As a result, frame synchronization can be achieved in a shorter time than with conventional synchronization methods. For example, if the frame synchronization pull-in judgment criterion is set to ``70'' or higher, as shown in FIG.
When the frame synchronization is detected consecutively, it is determined that the frame synchronization has been pulled in. However, in the conventional synchronization pull-in method, the output of the ABS circuit 94 shown in FIG.
As shown in the bottom column of the figure, it is 0.3'', and it is not determined that frame synchronization has been established.

As described above, in the synchronous pull-in method according to the present invention, the first
As shown in the figure, the initial value starts from 0, and when a unique code is detected at a predetermined position in the above frame, +
1 is added, and when a unique word is not detected, -1 is added to obtain a first cumulative value in the adding circuit 14, and the absolute value of this first cumulative value is determined by the number of delay stages in the delay circuit 12. the second cumulative value is obtained by accumulating the absolute value of the first cumulative value in the adding circuit 17, and when this second cumulative value is equal to or greater than the second predetermined value; By determining that the frame synchronization has been pulled in, when a cycle slip occurs, frame synchronization can be pulled in in a shorter time than in conventional synchronization pulling methods.

H. Effects of the Invention As is clear from the above explanation, in the synchronization pull-in method according to the present invention, the initial value is started from 0, and +1 is added when a unique word is detected at a predetermined position of the frame. When a unique word is not detected, -1 is added to obtain a first cumulative value, and the absolute value of the first cumulative value is limited by a first predetermined value, and the absolute value of the first cumulative value is accumulated. to obtain the second cumulative value, and the second cumulative value is the second cumulative value.
By determining that the frame synchronization is in a state where the frame synchronization is greater than a predetermined value, when a cycle slip occurs, frame synchronization can be pulled in in a shorter time than with conventional synchronization pull-in methods.

[Brief explanation of the drawing]

FIG. 1 is a block circuit of a main part of a frame synchronization circuit for implementing the synchronization pull-in method according to the present invention, and FIG. 2 is a block diagram of the above-mentioned FIG. FIG. 3 is a diagram showing the output of the main part of the frame synchronization circuit shown in FIG. 1, and FIG. 3 is a diagram showing the output of the main part of the frame synchronization circuit shown in FIG. Figure 4 is a block circuit diagram of the Inmarsat 5TD-C system, and Figure 5 is a diagram showing the output of the main parts.
FIG. 6 is a block circuit diagram of the main parts of a conventional frame synchronization circuit, and FIG. 7 is a diagram showing the frame configuration of the -C system, and FIG. 7 is a diagram showing the state shown in FIG. FIG. 3 is a diagram showing the output of the main part of the frame synchronization circuit. 11...Multiplication circuit 12...Delay circuit 13.14.17...Addition circuit 15.18...Delay circuit 16...Absolute value circuit

Claims (1)

[Claims] A synchronization pull-in method for pulling in frame synchronization using a unique word placed at a predetermined position of a frame, the method comprising: starting from an initial value of 0, and detecting a unique word at a predetermined position of the frame. When a unique word is not detected, +1 is added, and -1 is added when a unique word is not detected to obtain a first cumulative value, and the absolute value of the first cumulative value is
A second cumulative value is obtained by accumulating the absolute value of the first cumulative value, and when the second cumulative value is greater than or equal to the second predetermined value, frame synchronization is engaged. A synchronous attraction method characterized by determining that.