JPH0453325A - Delay lock loop - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a delay lock loop that performs synchronous tracking of a spreading code in a spread spectrum communication device.

[Conventional technology]

Figure 3 shows, for example, the "spread spectrum communication system" R.
Written by C. Dickson, translated by Tateno et al., November 30, 1978.
It is a block diagram showing a conventional delay lock loop shown in the Japanese publication, and in the figure, 1 is a received signal input terminal;
Reference numeral 2 denotes a spreading code generator composed of a shift register, which generates a reference spreading code for despreading the received signal inputted from the received signal input terminal 1. 8 is a first mixer that despreads the received signal using the output signal of the n-1st stage of the spreading code generator 2; 9 despreads the received signal using the output signal of the nth stage of the spreading code generator 2; a second mixer; 10 is a first envelope detector that detects the power of the despread signal output from the first mixer 8; 11 is a second
A second envelope detector 12 detects the power of the despread signal output from the mixer 9; 12 detects the power of the despread signal output from the first envelope detector 10; A comparator that compares the power of the despread signal output from the line detector 11 and outputs the difference, and a low-pass filter 13 that passes only low frequency components in the output of the comparator 12.
14 is a clock generator that changes the frequency according to the output voltage of the LPF 13 and generates a clock for operating the spreading code generator 2; 15 is a spreading code input to the second mixer 9; A delay circuit that delays the spreading code generated by the generator 2 by a time of Tc/2 (Tc: width of 1 bit of the spreading code); 16 is the delay circuit 1 described above;
This is an output terminal that outputs a spreading code delayed by T c /2 by 5 as a spreading code synchronized with the received spreading code.

Next, the operation will be explained.

The received signal inputted from the received signal input terminal 1 is despread by the first mixer 8 and the second mixer 9, and the despreading codes inputted to these two mixers 8 and 9 are spread by a spreading code generator. 2, the despreading timing in the first mixer 8 and the second mixer 9 takes one bit of the spreading code (hereinafter referred to as one chip). There is a time lag. The delay lock loop is a circuit that uses this shift to synchronously follow the received spreading code. 1st. Envelope detectors 10, 11 are provided downstream of the second mixers 8, 9, respectively, and the power of the despread signal is detected. The output of the envelope detector 10, 1.1 is maximum when the despreading timing completely matches the received code, and when the despreading timing completely matches the received code, that is, when the despreading timing is off by one chip or more, the envelope The outputs of the line detectors 10 and 11 are almost O. FIG. 4 shows the first . Second envelope detector 10,1
Normalized output of 1 (maximum output level set to 1)
FIG.

At the point τe = O, the received spreading code inputted from the received signal input terminal 1 and the spreading code outputted from the output terminal 16 are completely matched in phase. τe−−(Δ/2
), Δ/2 (Δ=Tc) are the states in which the despreading timings in the first mixer and the despreading timings in the second mixer match, respectively, and τe
The outputs of the first and second envelope detectors 10 and 11 are compared in level by the comparator 12, and the L P F 13 Only low-frequency components pass through.The clock generator 14 changes the frequency depending on the output voltage of the LPF 13.FIG. 5 shows the normalized signal level input to the clock generator 14,
It is a diagram showing the relationship between τe and τe=o is the synchronization point. −3Δ/2〈τe≠0 within the range of τe < 3Δ/2
Then, a control voltage E corresponding to the value of τe is input to the clock generator 14, and the clock generator 14 supplies the spreading code generator 2 with a clock having a frequency corresponding to the control voltage level. This operation is performed in the direction in which τe becomes O, and this is the operation of the drawing process. After τe is pulled to approximately O, the synchronous tracking state is maintained, and τe is locked to approximately 0. Therefore, from the output terminal 16, a spreading code synchronized with the phase of the received spreading code is obtained.

This circuit is called a 1Δ delay lock loop because the peak of the control voltage level input to the tallock generator 14 has a width of one chip.

[Problem to be Solved by the Invention] Since the conventional delay lock loop is configured as described above, the range of the phase difference τe in which the control voltage E is generated is 13.
The width is 3Δ from Δ/2 to 3Δ/2, and once the delay lock loop enters the synchronous tracking state, the phase difference τe
is locked to approximately O, so the range of the phase difference τe in which the control voltage is generated does not matter much, but the following problem occurs in the pull-in process before the synchronous tracking state. That is, the pull-in operation of the delay lock loop is started by the timing of the acquisition pulse output by the circuit (initial acquisition circuit) that performs initial acquisition of the spreading code. That is, the role of the initial acquisition circuit is to output a start signal (i.e., acquisition pulse) within a width of 3Δ with a phase difference τe that allows the delay lock loop to generate the control voltage E. If the timing of this output acquisition pulse is 1τe1>3Δ/2, the delay lock loop will no longer be able to perform synchronous tracking and will have to start over from the initial acquisition. There were issues such as the time (acquisition time) required from the moment the device entered the synchronous tracking state until the data could be demodulated. FIG. 6 is a block diagram showing a 2Δ delay lock loop in which the range of τe in which the control voltage is generated is wider than that of the 1Δ delay lock loop. The point is that the despreading code input to the mixer 8 is extracted from the (n-2)th stage of the spreading code generator 2.

FIG. 7 is an explanatory diagram showing the relationship between the normalized control voltage level and τe for this 2Δ delay lock loop. The range of τe in which the control voltage E is generated is 4Δ from -2Δ to 2Δ, and It is wider than in the case of . By using this 2Δ delay lock loop, the problem in the pull-in process mentioned earlier can be improved, but
In a 2Δ delay lock loop, the synchronization point τe=o
Since the slope of the control voltage is O at this point, there is a problem that the synchronous tracking characteristic is inferior to that of a 1Δ delay lock loop.

By the way, the current problem, ie, the phenomenon in which the timing of the capture pulse output by the initial capture circuit exceeds the pull-in range of the 1Δ delay lock loop, will be explained using a specific example. FIG. 8 is a block diagram showing an example of a matched filter type acquisition circuit. In the figure, 17 is a clock input terminal, 18 is a carrier wave generator for converting the received signal into a baseband signal,
19 is the carrier wave output from the carrier wave generator 18 by π/2
(rad) phase shifters 20 and 21 are a third phase shifter that converts the received signal into a baseband signal using the carrier wave output from the carrier wave generator 18 and the carrier wave whose phase is shifted by π/2. a mixer and a fourth mixer. The reason why the received signal is converted into two baseband signals in this way is that when the acquisition circuit performs initial acquisition, the carrier wave of the received signal is phase synchronized with the carrier wave output from the carrier wave generator 18 of the acquisition circuit. This is because, since the baseband signal is not established, the baseband signals are converted into two orthogonal baseband signals, and a correlation operation is performed on each baseband signal. The received signals converted into baseband signals by the third mixer 20 and the fourth mixer 21 are sampled by the first sampler 22 and the second sampler 23, respectively, and are sampled by the first correlator 24 and the second correlator. The signal is input to the device 25. The clock used at this time is input from the clock input terminal 17 or is locked. The output of each correlator 24.25 is a squarer 26.27, respectively.
are squared and then summed by a first adder to produce a correlation pulse. The reason for calculating the square sum of the outputs of each correlator here is that the outputs of the first correlator 24 and the second correlator 25 include a phase difference component between the information data component and the carrier wave. This is to remove this. Reference numeral 29 denotes a frame memory, which takes advantage of the property of the above-mentioned correlation pulse to be a periodic signal of the code period and adds it cyclically (cumulatively) to the code period to improve the S/N ratio of the correlation pulse. Stores the cumulative sum of correlated pulse levels. 30 is a second adder that adds the correlation pulse and the cumulative addition value of the correlation pulses stored in the frame memory in order to perform cyclic addition; 31 is a signal for starting the DLL from among the correlation pulse train after cyclic addition; This is a determiner that detects captured pulses as pulse timing. 32 is a capture pulse output terminal, and this capture pulse becomes a start signal for the delay lock loop. The clock that is input to the plate clock input terminal 17 to operate the initial acquisition circuit is in a state where the synchronization of the spreading code by the delay lock loop has not been established, so it is asynchronous with the received signal, so it is normally used at the time of initial acquisition. The clock frequency of the received signal does not match the clock frequency of the receiver. 9th
The figure shows the relationship between the timing of the transmission code period and the correlation pulse timing created by the initial acquisition circuit, assuming that the clock frequencies match, and the correlation pulse timing when the receiver clock frequency is higher. FIG. In Figure 9, the code length of the spreading code is 7'.
This is an example of the case. In addition, FIG. 9(a) shows the timing on the transmitting side, and FIG. 9(b) shows the timing of the captured pulse assuming that the receiver clock is synchronized with the clock of the received signal. In this case, the correlation pulses are generated at a correct period of 7' in accordance with the timing of the transmitting side.

The first one shows the process of cyclically adding these correlated pulses.
This is figure 0. In FIG. 10, the value stored in the frame memory 29 is the sum of the correlated pulse levels in a vertical column, so the timing with a high probability of outputting the captured pulse is the correlation pulse level on the rightmost side of the frame memory 29. This is the timing to write the pulse. On the other hand, FIG. 9(c) shows an example of the correlation pulse timing when the clock frequency of the receiver is higher than the clock frequency of the received signal. In this case, the correlation pulse has the correct period. 7
’ does not occur. For example, a correlation pulse that should be output at the 14th clock timing may be output across the 14th and 15th clock timings. Then, the process of cyclic addition in this case becomes as shown in FIG. 11, and the timings with a high probability of outputting the capture pulse are expanded. In this example, this range is exactly 4 chips,
This exceeds the retractable range of the conventional 1∆ delay lock loop.

In this way, the acquisition pulse output from the initial acquisition circuit, which operates before the synchronization of the spreading code is established by the delay lock loop, is usually deviated from the timing of the device, and the amount of deviation increases as the number of cyclic additions increases. , and increases as the clock frequency deviation increases. Therefore, there is a possibility that a captured pulse may occur at a timing that cannot be captured using the conventional 1Δ delay lock loop. If the number of cyclic additions is reduced, the range of timing in which a capture pulse occurs will be narrowed, but this will reduce the capture probability of the initial capture circuit. Furthermore, if a 2Δ delay lock loop is used which has a wider retractable range than a 1Δ delay lock loop, it is possible to cope with the spread of the timing at which acquisition pulses occur, but in the synchronous tracking state, the characteristics are inferior to the 1Δ delay lock loop. There were issues such as storage.

This invention was made to solve the above-mentioned problems, and it is a delay lock that has a wider retractable range than a 1Δ delay lock loop when retracting, and which can have the same characteristics as a 1Δ delay lock loop during synchronized tracking. The aim is to obtain a loop.

[Means to solve the problem]

A delay lock loop according to the present invention includes a spreading code generator that generates two sets of spreading codes with different phases for despreading an input received signal, and a set of spreading codes from these spreading code generators. a delay circuit for delaying the delay circuit; a switch for selecting between one set of spreading codes obtained through the delay circuit and another set of spreading codes from the spreading code generator not passing through the delay circuit; and a capture pulse. When inputting , in the pull-in state immediately after the input, the spreading code of the set with a large phase difference is selected, and on the other hand, in the synchronized tracking state after the input, the spreading code of the set with the small phase difference is selected. a switch control circuit that controls switching of a switch, and a first mixer that despreads the received signal and a second mixer that despread the received signal by each set of two spreading codes selected by the switch; The output powers of the first mixer and the second mixer are detected by a first envelope detector and a second envelope detector, respectively, and the first envelope detector and the second A difference between the detection outputs of the envelope detectors is detected, and a clock corresponding to this difference is generated from the delay lock loop and input to the spreading code generator.

[Effect]

During pull-in, the delay lock loop operates as a 2Δ delay lock loop using, for example, a 2-chip spacing spreading code, and during synchronized tracking, it is switched to the conventional method of 1-chip spacing spreading code.
It operates as a delta delay lock loop, thereby providing optimal synchronization pull-in and synchronization tracking characteristics.

[Embodiments of the invention]

An embodiment of the present invention will now be described with reference to the drawings.

In FIG. 1, 3 is a first delay circuit that delays the output from the n-th stage of the spreading code generator 2 by T c /2, that is, 1/2 chip time, and 4 is the first delay circuit from the n-th stage of the spreading code generator 2. a second delay circuit that delays the output of 1/2 chip time;
5 are two spreading codes with a 1-chip interval taken out from the n-2nd stage and the n-1st stage of the spreading code generator 2, and two spreading codes with a 2-chip interval delayed by a plate delay circuit. 6 is a capture pulse input terminal that inputs the capture pulse from the initial capture circuit; 7 is the capture pulse input terminal when the delay lock loop is in the retracted state immediately after the capture pulse is input from the capture pulse input terminal 6; This is a switch control circuit that controls the switch 5 to select a spread code with an interval, and controls the switch 5 to select a spread code with a one-chip interval in the synchronous tracking state.

Next, the operation will be explained using the control voltage characteristic diagram shown in FIG.

In the delay-locked loop according to the present invention, in addition to the set of two spreading codes with an interval of 1 chip as in the conventional delay-locked loop, the set of two spreading codes with an interval of 2 chips is used as a reference spreading code for despreading. ing. These two sets of spreading codes with different intervals can be easily created by simply adding two first and second delay circuits 3 and 4 to the spreading code generator 2 used in the conventional delay lock loop. is possible. Now, among these two sets of spreading codes, the spreading code with an interval of 2 chips and the spreading code with an interval of 1 chip are named A and B, respectively, as shown in FIG. If spreading code A is used, this delay lock loop becomes equivalent to the 2Δ delay lock loop shown in FIG. On the other hand, if spreading code B is used, it becomes equivalent to the 1Δ delay lock loop shown in FIG. By selecting either spreading code A or H using the switch 5, this delay lock loop is operated as a 1Δ delay lock loop or a 2Δ delay lock loop. Therefore, this delay lock loop has two control voltage characteristics, and the relationship is as shown in FIG.

That is, as is clear from this, during the bowing operation immediately after the acquisition pulse is input, the spreading code A is used to operate as a 2Δ delay lock loop. This allows the pull-in range to be wider than that of the conventional 1Δ delay lock loop.

On the other hand, in the synchronous tracking state, using spreading code B,
Operates as a 1Δ delay lock loop. As a result, the same synchronous tracking characteristics as the conventional 1Δ delay lock loop can be obtained. Switching between the spreading codes A and H is performed by the switch 5 as described above, and since the switch 5 only performs a completely simple switching operation, it can be easily realized. The configuration of the switch control circuit 7 that controls switching of the switch 5 is such that, for example, the captured pulse is
This circuit can also be realized with a simple configuration by configuring it with a timer as a signal, selecting spreading code A for a certain period of time after the capture pulse is input, and then switching to spreading code B. Become.

Note that in the above embodiment, a case was described in which two spreading codes with a width of 2 chips were used at the time of pull-in, but for example, 1.5
A spreading code having a chip width or a 2.5 chip width may also be used, and the same effect as described above can be obtained. In such a case, the first
In the configuration shown in the figure, this can be easily realized by simply changing the delay amounts of the first delay circuit 3 and the second delay circuit 4. For example, to create a spreading code with a width of 2.5 chips, the delay amount of the first delay circuit 3 should be changed from T c / 2 to 3 Ta / 4
In this case, the delay amount of the second delay circuit 4 is simply changed to T c /4.

〔Effect of the invention〕

As described above, according to the present invention, there is provided a spreading code generator that generates two sets of spreading codes with different phases for despreading an input received signal, and one set of spreading codes from these spreading code generators.
a delay circuit that delays the set of spreading codes, and switches either one set of spreading codes obtained through the delay circuit and another set of spreading codes from the spreading code generator that is not passed through the delay circuit. to allow selection by
When a capture pulse is input, in the pull-in state immediately after the input, a set of spreading codes with a large phase difference is selected, and on the other hand,
In the synchronous tracking state after the input, the switch control circuit is configured to control switching of the switch so that the spread code of the set with a small phase difference is selected.
At the time of retraction, the width of the acquisition pulse timing that can be retracted is made wider than that of the conventional method, and at the time of synchronous tracking, the same synchronous tracking characteristics as the conventional method can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a delay-locked loop according to an embodiment of the present invention, FIG. 2 is a characteristic diagram showing control voltage characteristics of the delay-locked loop shown in FIG. 1, and FIG. 3 shows a conventional delay-locked loop. Block diagram, Figure 4 is a characteristic diagram showing the envelope detector output in Figure 3, Figure 5 is a characteristic diagram showing the control voltage characteristics in Figure 3, Figure 6 is a block diagram showing the conventional 2Δ delay lock loop. 7 is a characteristic diagram showing the control voltage characteristics in FIG. 6, and FIG. 8 is a block diagram showing a conventional multifilter type initial acquisition circuit.
FIG. 9 is a timing chart 1 showing the capture pulses output by the initial capture circuit of FIG. 8, and FIGS. 10 and 11 are explanatory diagrams showing the timing of the capture pulses in the frame memory of FIG. 8. 2 is a spreading code generator, 3 and 4 are delay circuits, 5 is a switch, 7 is a switch control circuit, 8 is a first mixer, and 9 is a second mixer.
10 is a first envelope detector, 11 is a second envelope detector, and 14 is a clock generator. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. ] Heisei Sho (Spontaneous) 2, °0, 31 Year, Month, Day 6, Contents of amendment (1) The scope of the multiple patent claims in the attached sheet will be amended. (2) The specification shall be amended as follows. 2. Name of the invention Delay Lock Loop 3. Relationship with the person making the amendment Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Corporation Representative Moriya Shiki Tokyo Minato-ku Nishishin @ 1-4-10, subject of amendment 7, one or more documents stating the amended scope of claims in the list of attached documents; scope of amended claims To despread the input received signal. A spreading code generator that generates two sets of spreading codes with different phases, a delay circuit that delays one set of spreading codes from these spreading code generators, and one set of spreading codes obtained through this delay circuit. and a switch for selecting one of the other sets of spreading codes from the spreading code generator that is not passed through the delay circuit, and a switch for selecting one of the other sets of spreading codes from the spreading code generator that does not pass through the delay circuit, and the above set of spreading codes having a large phase difference in the pull-in state immediately after the input of the capture pulse. a switch control circuit for controlling the switching of the switch, and a switch control circuit for controlling the switching of the switch, so as to select a spreading code, and on the other hand, in a synchronous tracking state after the input, selecting a set of spreading codes having a small phase difference; a first mixer and a second mixer that despread the received signal using the set of spreading codes; and a first envelope detector that detects the output power of the first mixer and the second mixer. and the second envelope detector, and detect the difference between the detection outputs of the first envelope detector and the second envelope detector, generate a clock having a frequency according to this difference, and perform the above-described process. A delay lock loop having a clock generator input to a spreading code generator.

Claims (1)

[Claims] a spreading code generator that generates two sets of spreading codes with different phases for despreading an input received signal; a delay circuit that delays one set of spreading codes from these spreading code generators; a switch for selecting either one set of spreading codes obtained through the delay circuit and another set of spreading codes from the spreading code generator that is not passed through the delay circuit; Switch control for controlling the switching of the switch so that in the pull-in state, the set of spreading codes with a large phase difference is selected, and on the other hand, in the synchronized tracking state after the input, the spreading codes of the set with a small phase difference are selected. a first mixer and a second mixer for despreading the received signal by each set of two spreading codes selected by the switch; and output powers of the first mixer and the second mixer. A first envelope detector and a second envelope detector to be detected and a difference between the detection outputs of these first envelope detector and second envelope detector are detected, and a and a clock generator that generates a clock and inputs it to the spreading code generator.