JPH0453327B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] This is a sequence operation check circuit for a counter circuit, which detects the lowest digit position where the “0” value of the counter circuit exists from a priority encoder circuit, and detects the lowest digit position where the “0” value exists in the counter circuit, and The determined value is output, and the exclusive OR of this value and the inverted value of the predicted parity value output from the predicted parity value output circuit is output as the next predicted parity value, and this output predicted parity value is The parity checker circuit performs a parity check of the counter value by adding it to the counter value of the counter circuit, thereby checking the sequence operation of the counter circuit.

[Industrial application field]

The present invention relates to a sequence operation check circuit for a counter circuit, and more particularly to a sequence operation check circuit for a counter circuit that confirms whether states that change sequentially based on a certain regularity are occurring correctly.

For example, in the field of digital data communications, a plurality of divided digital data (frames) are transmitted and received at corresponding time intervals. Each time interval at that time is determined individually and is called a “time slot”.
It is beginning to be produced as a.

[Prior Art] Conventionally, a time slot defined as such has been formed by counting clock pulses with a counter (frame counter), for example, and using a time interval determined according to the counting state of the counter. The counting state of the counter changes sequentially in accordance with the regularity of each clock input, and the time length based on such sequentially changing states is an integral multiple of the clock time interval.

Each digital data string is conveyed via a transmission line according to the time slots created in this manner. In this way, the time slot for conveying the digital data string to be conveyed is determined.
Multiplex transmission is possible by accurately synchronizing time slots (frames) on the transmitting and receiving sides.

[Problem that the invention seeks to solve]

By the way, if the defined time slot and the data string corresponding to the time slot are "consistent"
Otherwise, digital data communication will not be performed properly. In that case, especially if the length (time length) of the time slot is not formed correctly, a situation may arise in which the data string that should be loaded in that time slot is not loaded correctly.

However, conventionally, no means has been taken to monitor whether or not the counting operation (regular and sequential changing state changing operation) of the counter forming the time slot is being performed correctly. Therefore, if the counter is not working properly for some reason, the accurate time slot will not be defined.
Correct digital data transmission will not be performed. There is a problem in that if the operation of the counter is disturbed in this way, the entire digital data communication system is affected.

The present invention has been created in view of the above points, and provides a sequence operation check circuit for a counter circuit that can monitor whether or not regular and sequentially changing states are changing correctly. The purpose is to

[Means for solving problems]

FIG. 1 is a principle block diagram of a sequence check circuit of a counter circuit according to the present invention.

In the figure, a counter circuit 115 responds to a clock signal 111 and sequentially outputs a counter value 113 for each clock signal.

The priority encoder circuit 117 detects the lowest digit position where the "0" value of the counter value outputted from the counter circuit exists, and outputs a value A ₀ 119 determined according to the detected position.

The predicted parity value output circuit 114 performs an exclusive OR with the clock signal 111, the output value A ₀ 119 of the priority encoder circuit 117, and the inverted value 116 of the predicted parity value output from the predicted parity value output circuit. Next predicted parity value 1
Output as 27.

The parity checker circuit 129 performs a parity check on the entire value obtained by adding the predicted parity value from the predicted parity value output circuit 114 to the counter value from the counter circuit 115.

With these configurations, it is possible to check the sequence operation of the counter circuit.

[Effect]

The counter values of the counter circuit 115 that are sequentially output in response to the clock signal 111 are determined by the priority encoder circuit 117 to be the lowest value in which the "0" value of the counter values input and output from the counter circuit exists. Detects the digit position of and outputs a value A ₀ 119 determined according to the detected position.

This value A ₀ 119 is input to the predicted parity value output circuit 114 which is supplied with the clock signal 111, and is excluded from the value obtained by inverting the predicted parity value output from itself in the predicted parity value output circuit 114. The logical OR is output as the next predicted parity value.

In response to the predicted parity value from the predicted parity value output circuit 114 and the counter value from the counter circuit 115, a parity checker circuit 129 performs a parity check on the entirety of the predicted parity value, so that the output from the counter circuit 115 is The counter value can be checked.

〔Example〕

FIG. 2 shows an embodiment of the invention. here,
Assuming that the present invention is applied to a system that performs communication using the TDM multiplexing method, a device for monitoring the operation of a sequence circuit for generating time slot addresses will be described as an example.

In the figure, a frame counter 211 as a regular sequential operating device is a sequence circuit for generating time slot addresses, and a time slot TS clock signal 213 is introduced into its clock input terminal CL. From the output terminal OUT of this frame counter 211, multiple bits (for example, 4
An output signal 215 (bit) is generated.

Output signal 215 is priority encoder 2
The lower bit is supplied to the 17 input terminal PEi as if it were input to the upper bit terminal, and the 1-bit sign output signal 219 is supplied from the output terminal _A0 of the least significant bit to the exclusive OR gate 221. . The output signal 223 of this gate 221 is supplied to the D input terminal of a D-type flip-flop 225, and the output signal of the D-type flip-flop 225 is fed back to the exclusive OR gate 221. The priority encoder 217 and the D-type flip-flop 225 constitute a prediction means.

Also, the TS clock signal 213 is introduced into the clock input terminal CL of the D-type flip-flop 225, and its Q output signal 227 is applied to the parity checker 2.
29 is supplied to the first input terminal _PC1 . Furthermore, the output signal 215 of the frame counter 211 is introduced into the second input terminal PC ₂ of the parity checker 229.

A parity output signal 231 from the output terminal _PC0 of the parity checker 229 is supplied to the set input terminal S of the R-GS flip-flop 233, and a reset signal 235 from the outside is supplied to the reset input terminal R. The Q output signal 237 of this flip-flop 233 is generated as a confirmation signal. This paritei chietsuka 2
29 and flip-flop 233 constitute testing means.

Next, the operation of the above configuration will be explained below.

In this embodiment, the frame counter 211
There is the following regularity in the counting state, and based on this regularity, the parity after a predetermined time (that is, at the next clock time in the frame counter 211) is predicted.

The regularity in this case will be explained with reference to FIG.

Now, set the frame counter 211 to 4 bits b ₀ ~
b If it is _{a 3} counter, count information (0 to F),
The counting states of these 4 bits have a corresponding relationship shown in the left half of FIG. However, bit _b0 is the least significant bit. Furthermore, the value of the priority encoder 217 for each counting state is 3 bits A ₀ to
A ₂ is shown in the third column from the left in the figure.

By the way, as is clear from the figure, the value (logical state) of the least significant bit A ₀ of the priority encode 217 is the lowest digit of the 4 bits b ₀ to b ₃ of the frame counter 211 that is "0". The number of bits lower than that digit is an "odd number"
In the case of , it is "1", and in the case of "even number", it is "0".

Based on this regularity, only the lowest bit _A0 of the priority encoder 217 is output, and the set or reset state is regulated by the previous clock and D is kept in that state.
The output of flip-flop 225 is exclusive-ORed with the output of flip-flop 225. In response to the clock pulse of the TS clock signal 213, the D-type flip-flop 225 performs the
Continues to maintain the state of “0” and “1”. Like this D
Since the output signal of the flip-flop 225 is fed back to the exclusive OR gate 221, the manner in which the logic state of the Q output signal 227 of the flip-flop 225 changes with respect to the TS clock signal is shown in the rightmost column of FIG. It becomes as shown in .

As mentioned above, priority encoder 2
Exclusive OR gate 221 based on the output of 17
The next parity (logic state of signal 227) generated by D-type flip-flop 225 is applied to parity checker 229 at the next stage.

In other words, as can be seen from this relationship diagram, if the number of bits from the least significant digit where no bit is set in the 4 bits b ₀ to b ₃ of the frame counter 211 is an odd number (the least significant bit of the priority encoder 217 When A ₀ is “1”), the parity (predicted parity) at the next counting state (represented by the output signal 215) does not change at all; however, in the case of an even number (A ₀
="0"), the (predicted) parity in the next counting state is reversed.

The parity checker 229 is also supplied with the output signal 215 of the frame counter 211, and on its second input terminal _PC2 side, if the number of bits that are set ('1') among the 4-bit signal is an even number ( Parity is defined such that parity is "1" for zeros (including zero) and "0" for odd numbers.

Now, for example, in response to the clock signal 213, the count information of the frame counter 211 is "1"("1000").
It is assumed that the value has been transferred from ``2'' (0100) to ``2'' (0100).

Then, the "predicted parity" given from the D-type flip-flop 225 is "0". Also,
4 bits _b0 to _b3 representing count information “2” are “0100”
Therefore, the specified parity on the second input terminal _PC2 side of the parity checker 229 is "0".
Therefore, since the predicted parity given to the first input terminal PC ₁ is also "0", the desired relationship that the two parities match is established, so the output from the parity checker 229 takes the logic state "0". A signal 231 is generated.

Subsequently, by continuing counting, the frame counter 21
Count information of 1 is from "2" (0100) to "3" (1100)
It is assumed that the transition to Then, the predicted parity becomes "1". In contrast, the output signal 215
The 4 bits _b0 to _b3 are “1100”, so they are “1”.
The number of bits is 2, and the specified parity at the second input terminal PC ₂ side of the parity checker 229 is “1”.
It is. Therefore, the output state of parity checker 229 remains "0".

In addition, as long as the frame counter 211 responds to the clock signal 213 and correctly counts according to its regularity as shown in FIG. 3, the output state of the parity checker 229 will never be other than "0". . Therefore, initially the reset signal 23
The R-S flip-flop 233, which had been reset by 5, continues to maintain its reset state. Therefore, the Q of R-S flip-flop 233
The "0" logic state of the output signal 237 is maintained,
No "alarm signal" is generated, and the output signal 215 representing the counting state of the frame counter 211 is supplied to a time slot generator (not shown) to form a correct time slot.

What has been described above is a case where the frame counter 211 sequentially changes its state according to its inherent regularity, and performs the correct changing operation in response to the clock signal 213.

On the other hand, suppose that for some reason the frame counter 211 performs an inconvenient operation that does not follow the regularity. For example, possible causes include a failure of the frame counter 211 itself, a response to noise, and a drop in the driving power supply voltage.

Assume now that the frame counter 211 jumps, for example, from "2"("0100") to "4"("0010") in response to the clock signal 213 as an irregular operation. In that case, the expected parity produced by D-type flip-flop 2225 in response to the clock after the "2" state is "1". However, as a result, the 4 bits b ₀ to _{b 3} of the counting state represented by the output signal 215 from the frame counter 211
is “0010” and only 1 bit is set, so the second input terminal of parity checker 229
The specified parity on the PC ₂ side is "0". In this way, the predicted parity and the specified parity do not have the desired (matching) relationship. Therefore, Paritei Chietsuka 2
The logic state of the output signal 231 of 29 becomes "1", and the R-S flip-flop 233 is set. This set state is determined by the reset signal 235.
The Q output signal 237 of the flip-flop 233 continues to maintain a logic state during this time, and the "alarm signal" continues to be generated. The alarm signal (signal 237) generated in this manner cancels the energization of other circuits by the output signal 215 of the frame counter 211 (however, the means for canceling this is omitted). Therefore, it is possible to prevent an adverse effect on multiplex transmission or reception (system failure) due to irregular operation of the frame counter 211.

Further, even if the counting state of the frame counter 211 jumps two steps from another state, an alarm signal is generated in exactly the same way.

In the above embodiment, the state of the next clock in the counting operation of the frame counter 211 is predicted and compared with the actual changing state of the clock, but the present invention is not limited to this. For example, the prediction step may be several clocks ahead.

In addition, a counter 211 as a sequence circuit
The device may be used not only to monitor the counting state of the device, but also to check the changing behavior of other things that exhibit regular and sequential changing states. However, if the state changes sequentially,
It is necessary to correlate timing with the occurrence of the predicted state by the prediction means.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to monitor the operation of a device itself that outputs states that change in a regular order with a simple circuit configuration, so it is extremely useful in practice. .

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram of a sequence operation check circuit of a counter circuit according to the present invention, FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 3 is a diagram illustrating the operation of an embodiment of the present invention. It is a correspondence explanatory diagram shown in a value table. In FIG. 1, 111 is a clock signal;
3 is a counter value, 114 is a predicted parity value output circuit, 115 is a counter circuit, 116 is an inverted value of the predicted parity value, 117 is a priority encoder circuit, 119 is a value determined according to the detection position, 12
7 is the next parity predicted value, 129 is the parity checker circuit, and in FIG. 2, 211 is the frame counter;
213 is a TS clock signal, 217 is a priority encoder, 221 is an exclusive OR gate,
225 is a D-type flip-flop, 227 is an output signal, 229 is a parity checker, 233 is an R-S
It's flip flop.

Claims (1)

[Claims] 1. A counter circuit 115 that counts the clock signal 111 and a check circuit thereof, and adds a predicted parity value generated in advance to the output value of the counter circuit 115 to control the sequence operation of the counter circuit. In the circuit to be checked, check the state of the counter value output from the counter circuit, detect the lowest digit position where the "0" value exists, and determine the value A ₀ 119 determined according to the detected position.
A priority encoder circuit 117 that outputs
and the exclusive OR of the value output from the priority encoder circuit 117 in response to the clock signal 111 and the value 116 obtained by inverting the predicted parity value generated before the output of the value. A predicted parity value output circuit 114 outputs the predicted parity value as the next predicted parity value 127, and the predicted parity value outputted from the predicted parity value output circuit 114 is added to the counter value, and a parity check of the entire value is performed. 1. A sequence operation check circuit for a counter circuit, comprising a parity checker circuit 129 for performing a parity check circuit.