JPH0453346B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] The currents supplied from the power supply circuit to the A line and the B line are each independently detected, each current is compared to see if it is above a threshold value, and the sum of the detected currents is the threshold value. By comparing whether the above is the same or not, and using the logical sum of the respective comparison outputs as a monitoring signal, it is possible to detect off-hook of a subscriber without error even when the level of common mode noise is large.

[Industrial application field]

The present invention relates to a monitoring circuit for monitoring line conditions in a subscriber circuit of an exchange.

In order to detect when a subscriber is on-hook or off-hook, a monitoring circuit is used to detect the power supply currents of the A line and B line. This monitoring circuit ensures that the subscriber's on-hook,
It is desired to be able to detect off-hook.

[Conventional technology]

As a conventional monitoring circuit, for example, the configuration shown in FIG. 3 is known. In the figure, Qa and Qb are transistors for supplying currents I _A and I _B to the A line and B line, and BC ₁ and BC ₂ are power supply control circuits (B control circuits) for controlling transistors Qa and Qb. ), CMP ₁ , CMP ₂
is the comparison circuit, Re ₁ and Re ₂ are the resistances Vth, 〓Vth is the threshold voltage, R _L1 is the line load resistance (resistance on the subscriber side),
V _BB is, for example, -48V battery supply voltage, SCNA,
SCNB is a monitoring signal applied to a scanning circuit (not shown).

The transistors Qa and Qb, the resistors Re ₁ and Re ₂ , and the power supply control circuits BC ₁ and BC ₂ constitute a power supply circuit that supplies a predetermined current to the line load resistance R _L , and
The voltages of R _e1 and R _e2 are the current I _A flowing in the A line and B line,
This is a proportional example of I _B. Therefore, the comparison circuit
In CMP ₁ and CMP ₂ , the threshold voltages Vth, 〓Vth (however, the absolute values are equal and the polarities are opposite, that is, |Vth|
=|〓Vth|), it is possible to monitor whether the loop current is due to the off-hook of the subscriber. That is, the monitoring circuit
If only either SCNA or SCNB is connected, it is due to a ground fault or interference in the subscriber line, and the monitoring signal
If both SCNA and SCNB are output, it can be determined that the subscriber is off-hook.

Also known is a monitoring circuit that detects the sum of the currents flowing through the A line and the B line, and determines that the current is off-hook when the sum is greater than a certain value.

[Problem that the invention seeks to solve]

As shown in Figure 3, when the A line and B line are monitored independently, if the common mode noise level is large, the B
When the current I _B on the line side is canceled out by the noise component and decreases, the current I _B on the B line side may become less than the threshold value due to the sum with the noise component, and in that case, the comparator circuit The output of the monitoring signal SCNB from CMP ₂ is stopped. Then, when the polarity of the common-mode noise is reversed, the current I _A on the A line side decreases, and the current I _A on the A line side becomes less than the threshold value, and the output of the monitoring signal SCNA from the comparator circuit CMP ₁ is stopped. Ru. That is, there was a drawback that the output of the monitoring signals SCNA and SCNB was alternately and repeatedly stopped.

In addition, in the conventional monitoring circuit that detects the sum of the currents flowing in the A line and the B line and controls the common mode noise mentioned above, even when one of the currents increases due to a ground fault, etc.
Since the current exceeds a certain value, it is detected as a subscriber's off-hook and has the disadvantage that abnormal conditions cannot be detected.

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned conventional drawbacks and provide a monitoring circuit that is not affected by common mode noise and can independently monitor the A line and B line.

[Means for solving problems]

To explain the monitoring _circuit of the present invention with reference to FIG. ₁ , the line load resistance _R Supply currents I _A and I _B to Then, first and second current detection means including resistors R _e1 , R _e2 and the like detect the current flowing in the A line and the B line, respectively, and each of the current detected by the first and second current detection means current and threshold value Vth ₁ ,
First and second comparison circuits that compare Vth ₂
CMP ₁ , CMP ₂ , and first and second comparison circuits
CMP ₁ , CMP ₂ and a third comparator circuit CMP ₃ that calculates the sum of the currents detected by the first and second current detection means using an adder circuit ADD or the like and compares it with a threshold value Vth ₃ ; By adding the comparison outputs of these first, second, and third comparison circuits CMP ₁ , CMP ₂ , and CMP ₃ , the first and second monitoring signals SCNA and SCNB are simultaneously output during normal off-hook, and the ground fault is detected. Sometimes,
A gate circuit G ₁ that outputs only the ground fault side monitoring signal of one of the first and second monitoring signals SCNA and SCNB,
It is equipped with a logic circuit consisting of G ₂ , G, etc.

[Effect]

In the case of a normal off-hook of the subscriber, the currents I _A and I _B flowing through the A line and the B line are almost balanced, and the detected current values are greater than the threshold values Vth ₁ and Vth ₂ . Further, the value of the detected current obtained by the addition circuit ADD or the like also becomes a value equal to or higher than the threshold value Vth ₃ . Therefore, when the logic circuit is constituted by gate circuits G ₁ and G ₂ , the first and second monitoring signals SCNA and SCNB are output simultaneously.

Also, when high-level in-phase noise is added to the subscriber's off-hook state, the currents I _A and I _B flowing through the A and B lines will fluctuate, but since their sum is almost constant, The sum value maintains the threshold value Vth ₃ or more, and the threshold values Vth ₁ and Vth ₂ are relatively small values, so the currents I _A and I _B of the A line and B line are also the threshold value.
Maintain Vth ₁ , Vth ₂ or more, therefore, the first and second
The monitoring signals SCNA and SCNB are not output alternately, and the monitoring signals SCNA and SCNB are stable.
SCNB is output.

For example, when the A line is grounded, only the current flowing in the A line increases and exceeds the threshold value Vth ₁ , but when the subscriber is on-hook, the current flowing in the B line becomes negligible and exceeds the threshold value Vth 1. ₂ or less. Also, the sum of the currents flowing in the A line and B line is the threshold
If it exceeds Vth ₃ , the first monitoring signal on the ground fault side
Only SCNA is output, and the second monitoring signal SCNB is not output. Therefore, it can be determined that a fault has occurred in which a large current flows only in the A line. Further, when a ground fault occurs in the B line, only the second monitoring signal SCNB is output, and it can be identified that a fault has occurred in which a large current flows only in the B line.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a main circuit diagram of an embodiment of the present invention,
The same symbols as in FIG. 1 indicate the same parts, M1 to M3.
is a mirror circuit, Q1 to Q7 are transistors, V _EE
is a power supply voltage, CI ₁ and CI ₂ are constant current sources, and Rc ₁ to Rc ₃ and Rs ₁ to _{Rs 3} are resistances. The power supply control circuits BC ₁ and BC ₂ B that control the transistors Qa and Qb that supply current to the A line and the B line are not shown, and the mirror circuits M1 to M3 are explained with a current ratio of 1. do.

Transistors Q ₁ and Q ₄ connected to the emitters of transistors Qa and Qb are connected to constant current sources CI ₁ and CI ₂ , so they are connected to resistors Re ₁ and Re ₂ with high impedance. . Further, the emitter potential of transistors Q ₂ and Q ₃ whose bases are connected to the emitter of transistor _Q 1 becomes equal to the potential of resistor Re ₁ , and is converted into a current by resistors Rc ₁ and Rc ₂ . Further, the emitter potential of the transistor ^Q5 whose base is connected to the emitter of the transistor _Q4 is equal to the potential of the resistor _Re2 , and the voltage of the resistor _Re2 is converted into a current by the resistor _Rc3 .

The current converted by this resistor _Rc3 flows into the input terminal of the mirror circuit M1, and a current equal to this current flows into the first output terminal of the mirror circuit M1 through the resistance.
It flows through Rs ₂ and is converted into a voltage by its resistance Rs ₂ . Also, the current flowing into the second output terminal of the mirror circuit M1 flows through the resistor _Rs3 , and this resistor
Since the current converted by the resistor Rc ₁ also flows through Rs ₃ , this resistor Rs ₃ converts it into a voltage corresponding to the sum of the currents flowing through the A line and the B line. Therefore _, the configuration in which wired-OR connection is made to _the resistor Rs ₃ corresponds to the adder circuit ADD in FIG. ₁ to _Q5 , the mirror circuit M1, the resistors _Rc1 to _Rc3 , and the like constitute the first and second current detection means.

The current converted by the resistor Rc ₂ flows through the resistor Rs ₁ connected to the first comparator circuit CMP ₁ , is converted into a voltage, and is compared with the threshold value Vth ₁ . Further, the current at the first output terminal of the mirror circuit M1 flows through a resistor _Rs2 connected to the second comparator circuit _CMP2 , is converted into a voltage, and is compared with a threshold value _Vth2 . Also resistance Rs ₃
The voltage converted by
It is compared with the threshold value Vth ₃ by CMP ₃ . In this embodiment, the polarity of voltage V _BB is negative, so
The polarities of the thresholds Vth ₁ , Vth ₂ , and Vth ₃ are also negative. When the subscriber is on-hook and no current flows through the A and B lines, no current flows through the resistors Rs ₁ , Rs ₂ , and Rs ₃ , so the + terminals of the comparison circuits CMP ₁ and CMP ₂ Since the ground potential is 0V, which is higher than the thresholds Vth ₁ A and Vth ₂ applied to one terminal, the outputs of the comparison circuits CMP ₁ and CMP ₂ are high level, and the transistors Q ₆ and Q ₇ are turned on.

Also, when current flows through the A line and the B line, the resistance Rs ₁ ,
From the voltage converted by Rs ₂ , the comparator circuit
The positive terminals of CMP ₁ and CMP ₂ have a potential lower than the threshold values Vth ₁ and Vth ₂ , and the outputs of the comparison circuits CMP ₁ and CMP ₂ become low level. Therefore, transistor Q ₆ ,
Q ₇ is off. At that time, the voltage at the resistor Rs ₃ causes the potential at the negative terminal of the comparator CMP ₃ to reach the threshold value.
When it becomes lower than Vth ₃ , its output becomes high level, current flows through mirror circuits M2 and M3, and monitoring signals SCNA and SCNB are output.

Therefore, mirror circuits M2, M3 and transistors
The configuration consisting of Q ₆ and Q ₇ is the gate circuit shown in Figure 1.
It corresponds to the logic circuit consisting of G ₁ and G ₂ , but since the output conditions of the comparator circuits CMP ₁ , CMP ₂ , and CMP ₃ are different from those shown in _{FIG .} The logic circuit consisting of will act as an inhibit gate.

As mentioned above, the first and second comparison circuits CMP ₁ ,
The threshold values Vth ₁ and Vth ₂ of CMP ₂ are relatively small values, and even if the line load resistance R _L in the subscriber's off-hook state is a relatively large value, the value of the current flowing in the A line and B line is This becomes larger than the threshold values Vth ₁ and Vth ₂ , and the transistors Q ₆ and Q ₇ are turned off by the outputs of the comparison circuits CMP ₁ and CMP ₂ . At that time,
When the value of the sum of the currents flowing in the A line and the B line becomes larger than the threshold value Vth ₃ , the current flows from the third comparator circuit CMP ₃ to the input terminals of the mirror circuits M2 and M3. Monitoring signals SCNA and SCNB are output from the output terminals.

In addition, in the case of a ground fault in the A line, the current flowing in the A line becomes very large, and the output of the first comparison circuit CMP ₁ turns off the transistor Q ₆ , and the output of the third comparison circuit CMP ₃ turns off. Output current is mirror circuit M
2. If it is applied to the input terminal of M3, the monitoring signal SCNA will be output from the mirror circuit M2, but
Since the transistor ^Q7 is in the on state, the output current of the comparator circuit _CMP3 flows through the transistor _Q7 and does not flow into the input terminal of the mirror circuit M3. Therefore, the supervisory signal SCNB will not be output.

Also, when the level of common mode noise is large, the A line,
Since the sum of the currents in the B line is almost constant, the current is supplied from the third comparator circuit CMP ₃ to the input terminals of the mirror circuits M2 and M3, and at that time, the currents in the A line and B line reach the threshold value Vth ₁ , If Vth does not decrease below ₂ , transistors Q ₆ and Q ₇ will remain off, so
Monitoring signals SCNA and SCNB are output continuously.
Therefore, as mentioned above, transistors Q ₆ , Q ₇ ,
A logic circuit composed of mirror circuits M2 and M3 converts the output of the third comparison circuit CMP 3 into the first and second comparison circuits CMP ₁ and CMP ₂ when the outputs of the first and second comparison circuits CMP 1 and CMP ₂ are "0". It functions as an inhibit gate to output as second monitoring signals SCNA and SCNB.

As mentioned above, the logic circuit is shown in FIG. 1 as an AND circuit consisting of gate circuits G ₁ and G ₂ , and in FIG. 2 as an inhibit gate. This shows that.
In other words, the logic circuit outputs the first and second monitoring signals SCNA and SCNB simultaneously when the subscriber is off-hook normally, and a large current due to a ground fault in either the A line or the B line is directed to one side. If only the ground fault is flowing, the configuration is such that only the monitoring signal on the side caused by the ground fault or the like is output.

〔Effect of the invention〕

As explained above, the present invention detects the current flowing in the A line and the B line by the first and second current detection means consisting of resistors Re ₁ and Re ₂ , etc., and sets the detected current to a threshold value, respectively. Vth ₁ and Vth ₂ are compared in the first and second comparison circuits CMP ₁ and CMP ₂ , and the sum of the detected currents and the threshold value Vth ₃ are compared in the third comparison circuit.
The comparison outputs of the first, second, and third comparison circuits CMP ₁ , CMP ₂ , and CMP ₃ are added to the logic circuit, and when _the subscriber is in a normal off-hook state, the logic circuit outputs the 1. Second monitoring signal SCNA,
By outputting SCNB at the same time, off-hook detection can be performed, and if a large current flows in either the A line or B line due to a ground fault, etc.
Since only the monitoring signal on the side caused by the ground fault etc. is output from the logic circuit, the A line and B line can be monitored independently. Also, due to common mode noise, the first and second
The monitoring signals SCNA and SCNB are not outputted alternately, and therefore, there is an advantage that on-hook and off-hook states of the subscriber can be detected stably.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating the principle of the present invention, FIG. 2 is a circuit diagram of a main part of an embodiment of the invention, and FIG. 3 is a circuit diagram of a main part of a conventional example. CMP ₁ , CMP ₂ , CMP ₃ C are first to third comparison circuits, Qa, Qb are transistors for power supply,
Re ₁ and Re ₂ are resistors that constitute the current detection section, BC ₁ and
BC ₂ is the power supply control circuit, ADD is the addition circuit, Vth ₁ ,
Vth ₂ and Vth ₃ are threshold values, G ₁ and G ₂ are gate circuits,
SCNA, SCNB are monitoring signals, CI ₁ , CI ₂ are constant current sources, M1, M2, M3 are mirror circuits, Q ₁ to _{Q 7} are transistors, Rc ₁ to _{Rc 3} , Rs ₁ to Rs ₃ are resistors, R _L
is the line load resistance.

Claims (1)

[Claims] 1. First and second current detection means for detecting the currents flowing in the A line and the B line, respectively, and the respective current values detected by the first and second current detection means. first and second comparison circuits (CMP ₁ ,
CMP ₂ ), and a third comparison that compares the sum of the current values detected by the first and second current detection means and a third threshold value that is larger than the first and second threshold values. An output corresponding to the AND of the comparison outputs of the circuit (CMP ₃ ), the first comparison circuit (CMP ₁ ), and the third comparison circuit (CMP ₃ ) is set as a first monitoring signal (SCNA), The output corresponding to the logical product of the comparison outputs of the second comparison circuit (CMP ₂ ) and the third comparison circuit (CMP ₃ ) is used as a second monitoring signal (SCNB), and the first, Second monitoring signal (SCNA,
SCNB), and a logic circuit that outputs only the monitoring signal corresponding to the ground fault side of the first and second monitoring signals (SCNA, SCNB) in the event of a ground fault. monitoring circuit.