JPH0453377A - Reproducing device for television signal - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a television signal reproducing apparatus for digitally processing and reproducing video signals.

BACKGROUND OF THE INVENTION FIG. 5 is a block diagram of a conventional television signal reproducing apparatus. In FIG. 5, a clamp circuit 1 to which a video signal is input is connected to an A/D converter 2, and further connected to a memory 3 at the subsequent stage to input digital data of the video signal to the memory 3. A timing generation circuit 4 to which a video signal is input is connected to an address generation circuit 5,
Furthermore, it is connected to the memory 3 and inputs the write and read addresses of digital data of the video signal from the address generation circuit 5 to the memory 3. The output terminal of memory 3 is D/
It is connected to an A converter 6 and has a configuration in which digital data read from the memory 3 is converted into analog data by the D/A converter 6.

The operation of the above configuration will be explained below. First, the video signal is clamped at a pedestal level by a clamp circuit 1, and is applied to an A/D converter 2 where it is converted into digital data. In the timing generation circuit 4, a system clock of 14.3MHz, which is four times the frequency of the color subcarrier, is reproduced from the video signal, and necessary timing pulses such as horizontal and vertical rates are generated, and the address generation circuit 5
is supplied to The address generation circuit 5 is connected to the A/D converter 2
Addresses are set for sequentially writing data in the video signal period and vertical blanking period of the video signal from 1 to 3 into the memory 3, and addresses are set so that the video signal period is subjected to the desired processing in the system and the vertical blanking period is read out sequentially. occurs, memory 3
give to Therefore, from the memory 3, a video signal that has been subjected to desired processing in the system for the video signal period is given to the D/A converter 6, and the D/A converter 6 outputs the desired video signal. Ru.

Here, in video signal processing of a television receiver,
The video signal period (from the beginning of the 22nd H to the middle of the 262nd H, and from the middle of the 283rd H to the end of the 525th H) and the vertical blanking period (from the beginning of the 1st H to the end of the 21st H, and from the middle of the 262nd H) The sampling clock for sampling the 283rd H (up to the middle of the 283rd H) is the same 14.3 MHz, and the number of sample points in one horizontal scanning period is 910. Therefore, if quantization is performed using 8 bits,
The memory capacity required for the vertical retrace period is 152.88 bits (=910 x 8 x 2 +).

Problems to be Solved by the Invention In the above-mentioned conventional television signal reproducing device, the video signal period and the vertical blanking period are similarly sampled and quantized, and in order to write them into the memory 3, read them out, and reproduce them. There was a problem in that a large capacity RAM was required as the memory 3 because of the vertical blanking period, which is not directly related to the content and quality of the video displayed on the television receiver.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and it is an object of the present invention to provide a television signal reproducing apparatus that can reproduce a vertical blanking period using a small-capacity memory.

Means for Solving the Problems In order to solve the above problems, the television signal reproducing apparatus of the present invention includes a synchronization signal storage means for storing the vicinity of the change point of the synchronization signal during the vertical blanking period, and When reproducing the vertical retrace period, the data in the synchronizing signal storage means and the read-only memory having a longer reproduction period than the data in the synchronizing signal storage means are stored. and means for reproducing the vertical retrace period by switching.

Further, the television signal reproducing apparatus of the present invention includes a read-only memory that stores a vertical blanking period, and a reproduction period other than the sync signal changing point in the vertical blanking period from a reproduction period near the sync signal changing point in the vertical blanking period. The apparatus is provided with means for reproducing data in the read-only memory by lengthening the reproducing cycle of the portion.

Effect With the above configuration, the vicinity of the change point of the synchronization signal during the vertical retrace period is stored in the synchronization signal storage means, and during playback, this stored data is combined with data from the read-only memory that is played back at a longer playback cycle. Since the vertical blanking period is reproduced by switching the vertical blanking period, the capacity of the memory for storing the vertical blanking period is reduced, and the accuracy of the change in the change point of the synchronizing signal is ensured for reproduction.

In addition, the reproduction period of the data generated by the read-only memory for reproducing the vertical blanking period is set so that the reproduction period of the data in the vicinity of the change point of the synchronization signal of the vertical blanking period is higher than that of the other parts. Since the reproduction cycle is lengthened, it becomes possible to reproduce the vertical blanking period using a small capacity and low cost read-only memory instead of the conventional memory for recording the vertical blanking period.

EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings. It should be noted that components that have the same functions and effects as those of the conventional example will be coded in the same manner, and their explanation will be omitted.

FIG. 1 is a block diagram of a television signal reproducing apparatus showing a first embodiment of the present invention. In Figure 1, A/
The output end of the D converter 2 is connected to the memo 1, and the digital data of the video signal is input to the memory 11. A video signal period address generation circuit 12 connected to the timing generation circuit 4 is connected to the memo January 1, and inputs a write address and a read address to the memo January 1. Memory 11 is connected to D/A converter 6 via switching circuit 13.

On the other hand, the output terminal of the timing generation circuit 4 is directly connected to the control circuit 14 and also connected to the control circuit 14 via a frequency dividing circuit 15, so that the system clock and the system clock are divided into l/10. You will be given an updated clock. The control circuit i4 is connected to the ROM 16 and the synchronizing signal storage circuit 17 to which the output end of the A/D converter 2 is connected, and controls the ROM 16 and the synchronizing signal storage circuit 17 in response to reproduction of the vertical retrace period. The output ends of the ROM16 and the synchronizing signal storage circuit 17 are connected to the switching circuit 13,
Further, the control circuit 14 is connected to the switching circuit 13, and a switching signal from the control circuit 14 is input to the switching circuit 13 to switch the outputs of the memory 11, ROM 16, and synchronizing signal storage circuit 17.

The operation of the above configuration will be described below.

First, the video signal period address generation circuit 12 sequentially reads out the data of the video signal period in the digital data of the video signal from the A/D converter 2 according to the address to be written in the memo 1/1 and the desired processing in the system. An address is generated and given to the memory 11. Therefore, from January 1 onward, the switching circuit 13 is given the video signal of the video signal period in which the desired processing in the system has been performed. On the other hand, the synchronization signal storage circuit 17 stores the falling part of the synchronization signal of a specific horizontal scanning line (hereinafter referred to as H) in the vertical blanking period in the digital data of the video signal given from the A/D converter 2. Now, the falling part of the synchronization signal of the 3H horizontal synchronization signal cycle is stored. The control circuit 14 has a 14.3 MHz system clock generated by the timing generation circuit 4, and a frequency dividing circuit 15 which divides the 14.3 MHz fast rate system clock generated by the timing generation circuit 4 into 1/10. A clock of 43 MHz is applied, and the reproduction of data in the ROM 16 and the synchronizing signal storage circuit 17 is controlled in response to reproduction during the vertical retrace period. This control circuit 14
Therefore, during the falling period of the synchronizing signal during the vertical retrace period, the falling data of the synchronizing signal stored in the synchronizing signal storage circuit 17 is given to the switching circuit 13 at the regeneration cycle of the 14.3 MHz clock, R during the vertical retrace period
Data from the OM 16 is applied to the switching circuit 13 at a clock reproduction cycle with a rough rate of 1.43 MHz. At this time, the memory capacity of the ROM 16 is reduced by the roughness of the clock rate. The switching circuit 13 switches the video signal from memory I during the video signal period and R during the vertical retrace period.
The data from the OM16 and the data from the synchronizing signal storage circuit 17 are switched by the switching signal from the control circuit i4.
/A converter 6, and D/A converter 6 outputs a desired video signal.

FIG. 2 shows a reproduction timing diagram of the vertical retrace period which is switched and reproduced by the switching circuit 13.

In FIG. 2, KL is a period of reproduction from the ROM 16, and KH is a period of reproduction from the synchronization signal storage circuit 17. Since the falling edge of the horizontal synchronization period of the synchronization signal can be considered to be equal for all H, the K at each H during the vertical retrace period is
The reproduction of the H period is performed by reproducing the falling signal of the synchronization signal of the third H horizontal synchronization signal period stored in the synchronization signal storage circuit 17 with the same clock as the clock for processing the video signal period. The line period also has the same falling characteristic of the horizontal synchronization period of the synchronization signal as the video signal period.

Now, the KH period is set to 10 with a 14.3MHz clock.
Assuming clock minutes, the memory required for the vertical retrace period is 8
There will be 0 bits (-10X8) of RAM and 1.512 bits of ROM.

As described above, the synchronization signal storage means stores the vicinity of the change point of the vertical retrace period, and during playback, this stored data and R
By switching the data from the OM and regenerating the vertical retrace period, it maintains the accuracy of the fall of the synchronization signal, which is important for synchronized playback, and is also a low-cost, small-capacity ROM.
The vertical retrace period can be played back.

FIG. 3 is a block diagram of a television signal reproducing apparatus showing a second embodiment of the present invention. In Figure 3, A/
The output end of the D converter 2 is connected to the memory 21, and digital data of the video signal is input to the memory 21. A video signal period address generation circuit 22 connected to the timing generation circuit 4 is connected to the memory 21 and inputs a write address and a read address to the memory 21. The memory 21 is connected to the D/A converter 6 via a switching circuit 23.

On the other hand, the output terminal of the timing generation circuit 4 is directly connected to the switching circuit 24 and also connected to the switching circuit 24 via a frequency dividing circuit 25, and the switching circuit 24 divides the system clock into 1/10. A completed clock is given. The switching circuit 24 stores the vertical retrace period.
It is connected to the OM26 and performs reproduction of the vicinity of the synchronization signal change point during the vertical retrace period using the system clock input directly from the timing generation circuit 4, and separates the reproduction of parts other than the vicinity of the synchronization signal change point. The configuration is such that the data in the ROM 26 is reproduced by switching to use the clock from the circuit 25. The ROM 26 is connected to a data conversion circuit 27 and further connected to a switching circuit 23 at the subsequent stage, and the switching circuit 23 switches between the output of the memory 21 and the output of the data conversion circuit 27 and outputs it to the D/A converter 6. The configuration is as follows.

The operation of the above configuration will be explained below. First, the video signal period address generation circuit 22 generates an address for sequentially writing video signal period data in the digital data of the video signal from the A/D converter 2 into the memory 21, and an address for reading it according to desired processing in the system. generated and provided to the memory 21. Therefore, from memory 21,
Digital data of the video signal during the video signal period in which the desired processing in the system has been performed is provided to the switching circuit 23.

On the other hand, the frequency divider circuit 25 divides the system clock having a fast rate of 14.3 MHz to 1/10, and outputs a frequency of 1.43 MHz.
A clock with a rough rate of 1 is applied to the switching circuit 24. The system clock from the timing generation circuit 4 is also applied to this switching circuit 24, and in the vertical retrace period, in the vicinity of the change point of the synchronization signal, the system clock from the timing generation circuit 4 is applied.
．． An address generated at a cycle of 3 MHz is given to the ROM 26, and an address generated at a cycle of a 1.43 MHz clock from the frequency divider circuit 25 is given to the ROM 26 in areas other than the changing point of the synchronization signal during the vertical retrace period. give. Furthermore, binary data is read out from the ROM 26 as a vertical synchronization signal according to the address from the switching circuit 24, and the data is adjusted in advance by the data conversion circuit 27 to be equal to the synchronization level of the video signal read out from the memory 21. Converted to the set value. Here, the switching circuit 23 transfers data from the memory 21 during the video signal period, and transfers data from the data conversion circuit 27 to the D/A converter 6 during the vertical retrace period.
The D/A converter 6 outputs a desired video signal.

FIG. 4 shows the address timing given to the ROM 26 by the switching circuit 24. In Fig. 4, the period of KH is 14.3MH in the 3rd and 4th H of the vertical retrace period.
The clock cycle of z (hereinafter referred to as Th) corresponds to 10 clocks, and the KL period corresponds to an address of 90 clocks with a cycle of 1.43 MHz (hereinafter referred to as Tl). Near the falling edge of the synchronization signal, the data of the synchronization signal can be reproduced with Th,
With the data in the ROM 26, it is possible to match the falling phase of the horizontal synchronizing signal during the video signal period with the falling phase of the horizontal synchronizing signal period of the synchronizing signal during the vertical blanking period. The reason why the KH period is only in the vicinity of the falling edge of the synchronizing signal is because the precision of the rising edge and the falling edge are not required for synchronized reproduction in the receiver.

Effects of the Invention As described above, according to the present invention, the accuracy of the vertical blanking period can be maintained, and the vertical blanking period can be reproduced using a low-cost, small-capacity read-only memory. be.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a television signal reproducing apparatus according to a first embodiment of the present invention, FIG. 2 is an address timing diagram of the same television signal reproducing apparatus, and FIG. 3 is a block diagram of a television signal reproducing apparatus according to a first embodiment of the present invention. FIG. 4 is a block diagram of a television signal reproducing apparatus showing an embodiment, FIG. 4 is an address timing diagram in the same television signal reproducing apparatus, and FIG. 5 is a block diagram of a conventional television signal reproducing apparatus. 4...Timing generation circuit, 11.21...Memory, 12゜22...Video signal period address generation circuit, 1
3...Switching circuit, 14...Control circuit, 1525...
- Frequency division circuit, 16... ROM117... Synchronous signal storage circuit, 23... Switching circuit, 24... Switching circuit, 2
6... ROM, 27... data conversion circuit. Agent Yoshihiro Morimoto

Claims (1)

[Scope of Claims] 1. A synchronizing signal storage means for storing the vicinity of the changing point of the synchronizing signal during the vertical retrace period, a read-only memory storing a portion other than the changing point of the synchronizing signal, and the vertical retrace line. means for reproducing the vertical blanking period by switching between data in the synchronizing signal storage means and data in a read-only memory having a longer reproduction cycle than the data in the synchronizing signal storage means when reproducing the period. playback device. 2. Read-only memory that stores the vertical retrace period;
A television signal comprising means for reproducing data in the read-only memory by making the reproduction cycle of a portion other than the vicinity of the synchronization signal change point longer than the reproduction cycle of the vicinity of the synchronization signal change point of the vertical blanking period. playback device.