JPH0545112B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video processing device that digitally time-compresses an analog video signal and outputs the time-compressed analog video signal.

[Prior Art] Conventionally, a television receiver having a two-screen display function has, for example, a display screen (hereinafter referred to as a main screen) of an analog received video signal of a desired channel.
In order to insert and display a time-compressed screen (hereinafter referred to as a child screen) of an analog received video signal of another channel or an analog input video signal input from an external device such as a video tape recorder,
It is equipped with a video processing device that digitally time-compresses the original input video signal for the child screen and outputs a time-compressed analog video signal.

Conventional video processing devices of this kind are disclosed in, for example, Japanese Patent Publication No. 47792/1983 and September 2, 1982.
As described on pages 7 to 12 of the dated document ``Television Society Technical Report (TEBS99-2),'' a field memory for time compression whose storage capacity is set to the storage capacity of one field of video data; Equipped with a buffer memory set to the storage capacity of video data for a horizontal scanning period (hereinafter referred to as 1H),
Each time-series video data formed by digitally converting the original input video signal mentioned above is temporarily stored in the buffer memory, and 1H video is stored from the buffer memory into the field memory by selecting a time when the field memory is not controlled for reading. By reading the data, for example
Sequentially writes 1H of video data every 3H to the field memory, reads the field memory at a higher speed than writing, converts each read video data into analog, and outputs a time-compressed analog video signal. It is configured as follows.

In other words, since digital memories such as field memories usually cannot perform writing and reading at the same time, conventional video processing devices of this type include a buffer memory together with the field memory, completely separating writing and reading from the field memory. time compression.

[Problem that the invention seeks to solve]

Therefore, conventional video processing devices of this kind need to be equipped with a buffer memory as well as a field memory, which increases the memory capacity of the device and requires two types of memory control, leading to the problem of complicating memory peripheral circuits. There is a point.

Note that when using a high-speed accessible memory with a short cycle time as the field memory and compressing the time to 1/n, for example, one write and n times are performed by n+1 accesses in each period of digital conversion. If reading is performed, time can be compressed using only the field memory, but in this case the field memory becomes very expensive and is not practical.

[Means for solving problems]

This invention has been made with the above-mentioned points in mind, and includes digitally converting an analog input video signal into digital video data, time-compressing the video data, and then converting the video data into an analog signal. In a video processing device that forms an output video signal, the digital conversion is performed based on a write address that is controlled to write during a period of 1/n of each period of the digital conversion and whose contents change at the speed of the digital conversion. A read address to which each formed video data is written and whose contents change at a speed n times the speed of the digital conversion, which is controlled to read during the remaining (n-1)/n period of each cycle. A field memory for time compression in which each video data written based on the writing is read out by skipping the data of the period controlled by the writing, and a field memory for time compression in which each video data read from the memory is inputted and converted into input data. Therefore, a signal processing circuit interpolates and forms missing data in the period controlled by the writing, and sequentially outputs n pieces of video data in each of the periods to the analog conversion circuit for forming the output video signal. This is an image processing device characterized by:

[Effect]

Therefore, in each period of digital conversion, video data is read out from the field memory at a speed n-1 times faster than the writing speed, and only the data of the period controlled for writing is transferred from the field memory to the signal processing circuit. Then, each video data written in the field memory is output.

Furthermore, the missing data in the period controlled by writing is interpolated and formed by the signal processing circuit, and in each period of digital conversion, the data is combined with n-1 pieces of video data input from the signal processing circuit to the analog conversion circuit. Since n pieces of video data consisting of one piece of interpolated video data are output, the video data is input to the analog conversion circuit at n times the writing speed of the field memory without any loss, and the time is reduced to 1/n. A compressed analog output video signal is output from the analog conversion circuit, and time compression can be performed using only a field memory with a cycle time of 1/n of the digital conversion period.

〔Example〕

Next, the present invention will be explained in detail with reference to FIGS. 1 to 4 showing one embodiment thereof.

Figure 1 shows the case where it is applied to a television receiver having a two-screen display function.
is an analog input video signal consisting of the original input video signal for the child screen (hereinafter referred to as the child screen video signal)
The input terminal 2 is a digital conversion circuit connected to the input terminal, which consists of an analog/digital converter operated by the sampling clock described later, and digitally converts the small screen video signal into m-bit video data. and output it.

Reference numeral 3 denotes a switch section for data input/output switching provided between the conversion circuit 2 and the field memory 4, and is formed using an analog switch or the like, and the memory 4 controls writing based on a switching control signal described later. During the period when the memory 4 is controlled to read, the input/output port of the memory 4 is connected to the conversion circuit 2, and during the period when the memory 4 is controlled for reading, the input/output port of the memory 4 is connected to a signal processing circuit, which will be described later.

Reference numeral 5 denotes a signal processing circuit connected to the memory 4 via the switch unit 3, which calculates the average of video data before and after missing data based on a timing control signal to be described later, and interpolates and forms the missing data. , the input video data and the interpolated video data are sequentially output.

Reference numeral 6 denotes an analog conversion circuit connected to the signal processing circuit 5, which consists of an m-bit input digital/analog converter, converts input video data into analog, and outputs a time-compressed analog output video signal. .

7 is an input terminal for the reference clock signal ck, 8, 9
10 and 11 are input terminals for the horizontal and vertical synchronization signals ha and va of the video signal for the main screen being displayed (hereinafter referred to as the main screen video signal), respectively, and 10 and 11 are the horizontal and vertical synchronization signals for the sub-screen video signal of input terminal 1. These are input terminals for signals hb and vb.

12 is a clock signal ck, synchronization signals ha, va, hb,
This is a control unit to which Vb is input, and is formed by a microcomputer, etc., and has a built-in timing control means and address generation means, and has a conversion circuit 2.
sampling clock for digital conversion control
ck', a switching control signal sw to the switch section 3, a multi-bit control signal cx to the signal processing circuit 5, and a write/read timing signal t _W/R and write/read address. A multi-bit control signal consisting of signals A _W and _AR is output to the memory 4.

Note that the number in the figure indicates m bits.

Then, the horizontal of the sub-screen video signal of input terminal 1,
When both the vertical time is compressed to 1/3 (n=3), the operation is performed as described below.

First, in each field of the sub-screen video signal, in order to convert one pixel out of every three pixels into video data only in each 1H of every 3H, the control unit 12 converts each 3H in each field of the sub-screen video signal. each of each
1H, 3 pixels in one cycle Ta in synchronization with the synchronization signal hb
A sampling pulse ck' is outputted to the converter 2, and one period of digital conversion of the converter 2 is set to Ta.

In addition, in order to sequentially write each video data output from the converter 2 into the memory 4, the control unit 12
supplies the memory 4 with a write address A _W whose content increases monotonically at the rate of digital conversion of the converter 2 .

On the other hand, in order to display the screen of the time-compressed child screen video signal on a part of the screen of the main screen video signal, it is necessary to read out the memory 4 in synchronization with the main screen video signal.

Then, in order to make the read speed of the memory 4 n-1 times the write speed, that is, twice, the control unit 12
In each field of the main screen video signal,
The timing signal t _W/R and the read address are output in synchronization with the synchronization signal ha, and at this time, the content of the timing signal t _W/R changes every 1/3 period of each period Ta of digital conversion, and each The control content for writing becomes the period of 1/3 of the trailing edge of one cycle Ta, and the control content for reading continuously becomes the content for the remaining 2/3 of each cycle Ta.

In addition, the read address A _R is 1/1/1 of each period Ta.
The content changes to sequentially specify each address in the memory 4 every 3 periods, that is, at a speed three times faster than digital conversion.

Next, to specifically explain the writing in the memory 4, in each 1H of every 3H of the sub-screen video signal, from the scanning start ts in FIG. The period shown in b in the figure is delayed by the time Tb until the scanning period of
Ta's sampling clock ck′ is output.

Therefore _, as _shown in FIG _.
The sub-screen video signals at t ₃ , t ₄ , t ₅ , t ₆ , t ₇ , ... are sampled and the video data Y ₀ , Y ₁ , Y ₂ , Y ₃ , Y ₄ ,
The video data Y ₅ , Y ₆ , Y ₇ , ... are sequentially converted into digital data, and each video data Y ₀ , Y ₁ , Y ₃ , ... is converted into digital data as shown in d of the same figure.
are output for each period Ta until the next video data Y ₁ , Y ₂ , Y ₄ , . . . are formed by the sampling clock ck'.

On the other hand, the write address A _W output from the control unit 12 to the memory 4 is
In 1H, as shown in Fig. 2e, the contents change every cycle Ta in synchronization with the digital conversion of the converter 2, and in the case of Fig. 2e, the video data Y ₀ , Y ₁ ,
For Y ₂ , . . . , the specified contents of the address change sequentially to 0, 1, 2, . . . incremented by 1.

Further, as described above, the timing signal t _W/R output from the control unit 12 to the memory 4 changes sequentially to read, read, and write in one period Ta each in synchronization with the main screen video signal.

By the way, since the main screen video signal and the sub-screen video signal are not necessarily completely synchronized and input at the same timing, the contents of the timing signal t _W/R are input in each period Ta in synchronization with the main screen video signal. Even if the timing signal t W/R changes in the order of read R, read R, and write W, in each period Ta synchronized with the child screen video signal, the changing order of the contents of the timing signal t _W/R is the same as that of the main screen video signal and the child screen video signal. Depending on the time lag with the screen video signal, one of the following three types will occur.

(1)...Read R, read R, write W (2)...read R, write W, read R (3)...write W, read R, read R For example, if the contents of the timing signal t _W/R change in the order of read R, write W, and read _R in one cycle Ta, then the memory _{4 ,} as _{shown in FIG .}
are controlled sequentially.

Furthermore, during the period in which the memory 4 is controlled to write W by switching the switch section 3 based on the switching control signal sw output from the control section 12 to the switch section 3, the input/output port of the memory 4 is switched to the switch section 3. The converter circuit 2 is connected to the converter circuit 2 via the converter circuit 2.

Therefore, the memory 4 stores t ₀ -t ₁ , t ₁ -t ₂ , t ₂ -
In each period Ta of t ₃ , ..., the video data Y ₀ , Y ₁ , Y ₂ , ... outputted from the conversion circuit 2 in each period Ta is transferred to the write address A _W during the period controlled by the write W. Therefore, the specified address, that is, 0,
Written to addresses 1, 2, . . . respectively.

Then, since the above-mentioned operation is repeated for each field of the sub-screen video signal, the memory 4 has the following information:
Video data obtained by thinning out the sub-screen video signal of each field to 1/3 in both the horizontal and vertical directions is sequentially written in units of, for example, 1H.

Next, to explain the reading from the memory 4 in detail, reading from the memory 4 is performed by reading any arbitrary part of the main screen video signal.
This is done every 1H from 1H, and at this time, from the scanning start ts' in Fig. 3a, when the synchronization signal ha of each 1H falls,
After a delay of a predetermined time, that is, a time Tc corresponding to the predetermined time Tb during writing, the timing signal t _W/R is output as shown in FIG.

The timing signal t _W/R has one period Ta synchronized with the synchronization signal ha, that is, t ₀ ′~t ₁ ′, t ₁ ′~
In t ₂ ′, t ₂ ′ to _{t 3} ′, t ₃ ′ to t ₄ ′, t ₄ ′ to _{t 5} ′,...
The contents change in the order of read R, read R, and write W.

On the other hand, the read address A _R outputted from the control unit 12 to the memory 4 changes its contents every 1/3 of each cycle Ta in each 1H, as shown in FIG. In the case of 0, 1, 2, 3, 4, 5,
The content changes to specify the addresses 6, 7, 8, 9, 10, 11, 12, etc.

Note that the read address A _R changes repeatedly during each 1H to the address designation contents for the same 1H in the memory 4, and the read address A _R during 1 field changes repeatedly.
All addresses in the memory 4 are sequentially and repeatedly designated by .

Then, as described above, the memory 4 is controlled to read R while the content of the timing signal t _W/R becomes read R, and the image at the address specified by the read address A _R input at that time is Read data.

By the way, the timing signal t _W/R has one cycle each Ta
The contents of W are necessarily written only once.

On the other hand, the contents of the read address A _R also change when the memory 4 is controlled to write W.

Then, the timing signal t _W/R of FIG. 3 b, c,
When read address A _R is input to memory 4,
When the timing signal t _W/R becomes the contents of the write W, that is, the read address A _R is 2, 5, 8,
When the content specifies addresses 11, . . . , the video data in the memory 4 cannot be read out.

Therefore, the timing signals of Fig. 3 b, c
t _W/R , for the read address A _R , from the memory 4, as shown in d of the same figure, the video data while being controlled by the write W, that is, the video at addresses 2, 5, 8, 11, ... Each video data Y ₀ , Y ₁ , −, Y ₃ , written by skipping the data Y ₂ , Y ₅ , Y ₈ , Y ₁₁ , ...
. One read period in each vertical direction is 1/3 of the write period.

By switching the switch section 3 based on the switching control signal sw, the input/output port of the memory 4 is connected to the processing circuit 5 via the switch section 3 during a period in which the memory 4 is controlled to read R.

Therefore, FIG. 4a read out from memory 4
The video data Y ₀ , Y ₁ , −, Y ₃ , . . . are sequentially input to the processing circuit 5.

Then, based on the control signal cx output from the control unit 12, the processing circuit 5 processes the missing video data Y ₂ , Y ₅ , Y ₈ , Y ₁₁ ,
… is formed by interpolation.

By the way, the processing circuit 5 includes, for example, a cascade circuit of two flip-flops, and an averaging circuit that calculates and outputs the average data of the video data input to the flip-flop at the front stage and the video data input to the flip-flop at the rear stage. and a switch that switches and outputs the video data input to the subsequent flip-flop and the arithmetic average data, and both flip-flops receive a timing signal.
The input data is delayed and output by 1/3 of one period Ta in synchronization with t _W/R , and the missing video data Y ₂ , Y ₅ , Y ₈ , Y ₁₁ ,... is sent to the flip-flop in the subsequent stage. The switch is set to output the averaged data only when it is input.

Then, the processing circuit 5 sequentially outputs each of the input video data Y ₀ , Y ₁ , −, Y ₃ , ... with a delay of 1/3 of one cycle Ta, and also outputs the input video data Y 0 , Y 1 , −, Y 3 , etc. ₂ , Y ₅ , Y ₈ , ... are input to the flip-flop in the subsequent stage, that is, the video data Y ₂ , Y ₅ , Y ₈ , ... missing in the flip-flop in the previous stage
The video data one after Y ₃ , Y ₆ , Y ₉ , ... is input, and the video data one before the video data Y ₂ , Y ₅ , Y ₈ , ... that is missing from the flip-flop at the subsequent stage.
When Y ₁ , Y ₄ , Y ₇ , ... are output, the average data Ya, _Yb , _Yc , ... that is, the average data (Y ₁ +Y ₃ )/2, (Y ₄ +Y ₆ )/2, (Y ₇
+Y ₉ )/2,... is output.

Therefore, the processing circuit 5 processes the missing video data.
Y ₂ , Y ₅ , Y ₈ , ..., video data Ya, Yb, Yc,
..., and the video data Y ₀ , Y ₁ , −, in FIG. 4a
When Y ₃ , Y ₄ , −, Y ₆ , Y ₇ , −, Y ₉ , Y ₁₀ , ... are input sequentially, one cycle is generated as shown in Figure b.
After a delay of 1/3 of Ta, video data Y ₀ , Y ₁ ,
Ya, Y ₃ , Y ₄ , Yb, Y ₆ , Y ₇ , Yc, Y ₉ , Y ₁₀ ,…
is sequentially output to the conversion circuit 6, and in this case, in each period Ta, three video data consisting of two input video data and one interpolated video data are sequentially converted. It is output to circuit 6.

Therefore, in the conversion circuit 6, the memory 4 is stored for one cycle each.
The video data is input to Ta at a speed equivalent to when it is read out at three times the writing speed without any loss, and the conversion circuit 6 sequentially converts each input video data into analog data. , 4th
As shown by the solid line in FIG. c, an analog output video signal is output, which is obtained by time-compressing the small screen video signal of the input terminal 1 to 1/3 in the horizontal and vertical directions.

Note that the broken line in Figure 4c indicates missing video data.
This shows when Y ₂ and Y ₅ are converted to analog.

Therefore, by using only the memory 4 whose cycle time is 1/n, that is, 1/3 of each cycle Ta of digital conversion, the time in the horizontal and vertical directions of the small screen video signal of the input terminal 1 is converted into digital data. The memory capacity of the device can be reduced to 1/3 compared to the conventional method, and the memory peripheral circuit can be simplified and formed at low cost.

In addition, a field memory that can be accessed at high speed is used instead of memory 4, and the cycle time of the field memory is reduced by 1/2 in each period Ta.
(n+1), that is, 1/4, write once and read three times, and change the contents of read address A _R sequentially only when reading, the above-mentioned omission will not occur. In this case, time compression can be performed without performing interpolation formation in the processing circuit 5, but in this case, the access time of the field memory becomes a high-speed access of several tens of nanoseconds, and such a high-speed accessible memory is extremely expensive. Therefore, in Figure 1, the cycle time is 1/
A memory 4 and a processing circuit 5 similar to those in the prior art of No. 3 are used.

Incidentally, in the embodiment described above, the explanation was given on the assumption that n=3 in order to compress the time to 1/3, but it is of course applicable when n is other than 3.

Further, in the above embodiment, it is applied to an image processing device of a television receiver having a two-screen display function,
Although the field memory is read in synchronization with the main screen video signal, it can of course be applied to video processing devices of various video equipment. Of course, it may be performed in synchronization with the video signal or a video signal separate from the video signal.

Furthermore, it goes without saying that the method of interpolating and forming missing video data by the processing circuit 5 may be different from that of the embodiment.

〔Effect of the invention〕

As described above, according to the video processing device of the present invention, in each cycle of digital conversion, the field memory is read out at a speed (n-1) times faster than the writing speed, and the signal processing circuit also eliminates data missing due to writing. By interpolating and forming the video data, the same video data as when the field memory is read out at n times the writing speed without any loss is input to the analog conversion circuit. Using only memory, the input video signal can be digitally time-compressed to 1/n, and the memory capacity of the device can be reduced and the memory peripheral circuitry can be simplified, making it possible to reduce the cost.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the video processing device of the present invention, FIGS. 2 a to f are timing charts for explaining writing to the field memory, and FIGS. 3 a to
4d is a timing chart for explaining reading of the field memory, and FIGS. 4a to 4c are timing charts for explaining the operation of the signal processing circuit. 2...Analog conversion circuit, 3...Switch section,
4...Field memory, 5...Signal processing circuit,
6...Analog conversion circuit, 12...Control unit.

Claims (1)

[Claims] 1. In a video processing device that digitally converts an analog input video signal into digital video data, and performs analog conversion after time-compressing the video data to form a time-compressed analog output video signal, the digital conversion Each video data formed by the digital conversion is written in a period of 1/n of each cycle based on a write address whose contents change at the speed of the digital conversion, and the video data is written in each cycle. During the remaining (n-1)/n period, each video data written based on a read address whose contents change at a speed n times the speed of the digital conversion is controlled to read out and is controlled to write. A field memory for time compression that is read by skipping data of a period, and each video data read from the memory is input, and the missing data of the period controlled by the input data to be written is interpolated and formed. , and a signal processing circuit that sequentially outputs n pieces of video data to an analog conversion circuit for forming the output video signal in each cycle.