JPH0453396B2 - - Google Patents

Description

[Detailed Description of the Invention] <Technical Field> The present invention relates to a pulse modulation type photodetection device used, for example, as a photoelectric switch or a photointerrupter. This relates to the configuration of the processing circuit portion.

<Prior art> A pulse modulation type photodetector includes a light emitting element and a light receiving element, emits pulsed light from the light emitting element, and
The light-receiving element receives pulsed light reflected by the object to be detected or pulsed light transmitted through the object, and the presence or absence of the object is detected in accordance with the reception of the pulsed light by the light-receiving element.

FIG. 4 shows a block diagram of a conventional pulse modulation type photodetector. As shown in the figure, the conventional pulse modulation type photodetector includes a pulse generation circuit 1 ₀ , a light emitting element drive circuit 2 ₀ , a light emitting element 3 ₀ , a light receiving element 4 ₀ , and an AC amplifier circuit 5 ₀ . , determination circuit 6 ₀ , synchronization detection circuit 7 ₀ , integration circuit 8 ₀ , determination circuit 9 ₀ ,
It is composed of an output circuit ₁₀₀ .

As shown in the time chart of FIG. 5, in the above photodetecting device, _{the light emitting element drive circuit 20 outputs} the light emission signal _a0 in response to the pulse signal from the pulse generation circuit 10, and the light emission signal The light emitting element 3 ₀ is driven by a ₀ and emits pulse-modulated light. The pulsed light from the light emitting element 3 ₀ is reflected by the object M or transmitted through the object M and enters the light receiving element 4 ₀ . Therefore, the light receiving element 4 ₀
The pulsed light incident on is turned on/off depending on the presence or absence of object M. The light receiving element 4 ₀ outputs a signal depending on the presence or absence of the object M. This signal is amplified by the AC amplifier circuit 5 ₀ and becomes a received light signal having the waveform shown in FIG. 5 (d ₀ ). This light reception signal d ₀ is waveform-shaped into a digital signal waveform by the determination circuit 6 ₀ and input to the synchronization detection circuit 7 ₀ . In the synchronization detection circuit ₇₀ , the output _e0 of the determination circuit ₆₀ is synchronously detected by a sampling pulse whose timing coincides with the light emission signal _a0 , and is converted into the waveform shown in FIG. 5 _f0 . The output f ₀ of the synchronization detection circuit 7 ₀ is input to the integration circuit 8 ₀ , and the integrated output g ₀ is waveform-shaped by the determination circuit 9 ₀ and outputted from the output circuit 10 ₀ as the detection signal h ₀ .

By the way, in such a photodetector, the object M
Due to the presence of the light emitting element ₃₀ , during the period when the pulsed light from the light emitting element 30 is not incident on the light receiving element ₄₀ , the dimming of the fluorescent lamp, the disturbance light of the optical signal of the remote control device, etc.
C ₀ may enter the light receiving element 4 ₀ as noise. In that case, the output of the synchronization detection circuit ₇₀ is
As shown in FIG. 5 d ₀ , the influence of the disturbance light C ₀ appears in the portion d ₁ . Therefore, there is a risk that the photodetector may malfunction or detect incorrectly due to the disturbance light C ₀ .

In order to prevent this malfunction, conventional photodetecting devices require an integrating circuit ₈₀ with a large time constant, as shown in FIG. 4, and due to the operation of this integrating circuit ₈₀ , the response is slow. Become. Also, the integrating circuit 8 ₀
Since a capacitor with a large capacitance is used in the photodetection device, this has been an obstacle to miniaturizing the photodetection device and converting it into an IC.

Furthermore, Japanese Patent Application Laid-Open No. 57-136179 proposes a device that detects a light reception signal at a timing that coincides with the light emission timing and at a time when the light emitting element does not emit light, and prevents malfunctions due to ambient light using a digital circuit configuration. There is.

However, this controls a frequency divider circuit that generates various timing signals when a light reception signal is detected at a non-emission timing, and this frequency divider control temporarily stops the pulse emission itself and also controls the pulse emission at the emission timing. Detects the received light signal
It is also necessary to cut off the reset signal of the flip-flop that is held and the clock signal of the counter that counts the number of times the light reception signal continues at the light emission timing.
This had the disadvantage that the circuit configuration and control system were complicated.

<Object of the Invention> The present invention has been made in view of the above-mentioned problems, and uses a simple circuit configuration of two latch circuits and a level holding circuit to reliably prevent malfunctions caused by ambient light and improve response speed. The purpose is to speed up the process and enable miniaturization.

<Configuration of the Invention> In order to achieve the above object, the present invention emits pulse-modulated light from a light emitting element, receives reflected light or transmitted light from an object to be detected by a light receiving element, and detects the object. In a pulse modulation type photodetector that detects the presence or absence of light, a first latch circuit that latches a digitized light reception signal at the light emission timing of a light emitting element every light emission cycle, and a A second latch circuit that latches at the timing when the light emitting element does not emit light every cycle, and the output of the first latch circuit are introduced, and the corresponding detection output is synchronized with the clock every cycle to input data. and a level holding circuit that holds the level and cuts off the clock at the time of inputting the data in response to the output of the second latch circuit when the output of the second latch circuit indicates light reception at a non-emission timing. This is the configuration of the device.

<Example> Hereinafter, the present invention will be described in detail based on an example shown in the drawings. FIG. 1 is a block diagram of one embodiment of the present invention. The pulse modulation type detection device of this embodiment includes a pulse generation circuit 1 and a light emitting element drive circuit 2.
, a light emitting element 3, a light receiving element 4, an AC amplifier circuit 5, a determination circuit 6, a synchronization detection circuit 7, and an output circuit 8. It does not have a circuit or a subsequent judgment circuit. In addition, as will be described in detail later, the synchronization detection circuit 7 in this embodiment does not capture and detect light reception data only at timings that match the light emission signal, as in conventional pulse modulation type photodetectors; Light reception data is captured and detected at two timings: timing that coincides with the signal (hereinafter referred to as emission timing), and timing that is synchronized with the emission signal but has a different phase from the emission signal (hereinafter referred to as non-emission timing). It is something. Further, the pulse generation circuit 1 is adapted to supply a predetermined light emission pulse to the light emitting element drive circuit 2, and also supply various necessary pulses to the synchronization detection circuit 7.

The configuration of the synchronization detection circuit 7 is shown in the block diagram of FIG. As shown in the figure, the synchronization detection circuit 7
The first latch circuit 9 latches the output of the determination circuit 6 at the light emission timing, the second latch circuit 10 latches the output of the determination circuit 6 at the non-light emission timing, and both the first and second latch circuits. The level holding circuit 11 generates a detection signal by introducing the outputs of 9 and 10.

The first latch circuit 9 receives the output b of the determination circuit 6.
and the light emission timing pulse c is input.
It consists of a NAND gate 12 and a first SR type flip-flop 13 to which the output d of the NAND gate 12 is input to a set terminal. A reset pulse e corresponding to the light emission timing pulse c is input to the reset terminal of the first SR type flip-flop 13. In addition, the second latch circuit 10 is a NAND circuit to which the output b of the determination circuit 6 and the non-emission timing pulse g are input.
It consists of a gate 14 and a second SR type flip-flop 15 to which the output h of the NAND gate 14 is input to a set terminal. A reset pulse i corresponding to the non-emission timing pulse g is input to the reset terminal of the second SR type flip-flop 15.

The level holding circuit 11 outputs a detection signal m corresponding to the output f of the first latch circuit 9, and
When the output j of the second latch circuit 10 indicates light reception at a non-emission timing, the detection signal level is maintained at a level corresponding to the previous output f of the first latch circuit 9 in response to the output j. a NAND gate 16 to which the inverted output j of the second latch circuit 10 and the clock pulse k are input;
A D-type flip-flop 17 inputs the output f of the first latch circuit 9 to the D input terminal, and the output l of the NAND gate 16 to the clock terminal.
It consists of.

The operation of the above configuration will be explained based on the time chart of FIG. The light emitting operation of the light emitting element 3, the light receiving operation of the light receiving element 4, and the waveform shaping operation of the determination circuit 6 are the same as those of the conventional pulse modulation type photodetector, and the signal waveforms of each part are also a ₀ to e in FIG. Since this is the same as indicating ₀ , a detailed explanation of this point will be omitted.

Now, as in the case of the time chart in Figure 5,
Let us consider a case in which disturbance light is incident when the pulsed light is prevented from entering the light receiving element 4 by the object M, and a case in which disturbance light is incident while the pulsed light is incident on the light receiving element 4. In that case, the received light signal a is
The waveform becomes as shown in FIG. 3a. This received light signal a is waveform-shaped by the determination circuit 6 and becomes a digital signal waveform shown in FIG.
Enter.

In the synchronization detection circuit 7, the judgment output b is the first
and are input to the NAND gates 12 and 14 of the second latch circuits 9 and 10, respectively. Therefore, in the first latch circuit 9, when the light emission timing pulse c and the judgment output b indicating light reception by the light receiving element 4 are both at high level, the output d of the NAND gate 12, that is, the first The set input of the S-R flip-flop 13 is at a low level, and in other cases, is at a high level. Therefore, the set input d becomes a waveform obtained by picking up each high level portion (the portion indicating light reception by the light receiving element 4) of the judgment output b. In this case, the set input d
also picks up the signal portion corresponding to the reception of disturbance light. The output f of the first S-R type flip-flop 13 is transmitted to the light receiving element 4 at every light emission timing pulse c.
It becomes a high level in response to light reception at the light receiving element 4, and a low level in response to a state in which light is not received by the light receiving element 4.
It shows the light reception state at the light emission timing. The output f of this first S-R flip-flop 13
contains a signal portion f ₁ affected by the disturbance light, similar to the S input d.

Next, in the second latch circuit 10, when the non-emission timing pulse g and the judgment output b are both at high level, the output h of the NAND gate 14, that is, the set input of the second S-R flip-flop 15 is set. becomes low level. Therefore, the set input h has a waveform that picks up each high level portion (the portion indicating light reception by the light receiving element 4) of the judgment output b, but the timing of the normal light reception signal is as follows.
Since the timing is out of phase with the timing of the non-emission timing pulse g, what is picked up by the non-emission timing pulse g is a signal portion that becomes high level due to light reception during non-emission time, that is, reception of disturbance light. Therefore, the inverted output j of the second S-R type flip-flop 15 becomes a signal indicating light reception when no light is emitted.

The output j of the second S-R flip-flop 15 and the clock pulse k are sent to the level holding circuit 1.
1 to the NAND gate 16. Second S-
When the output of the R-type flip-flop 15 becomes low level, the NAND gate 16 outputs the clock pulse k.
is cut off and is not input to the D-type flip-flop 17. In other words, a signal indicating light reception when no light is emitted (low level S-R type flip-flop output j)
When input to the NAND gate 16, the clock pulse k is cut off. Therefore, the clock pulse k is interrupted at the time when the disturbance light is received. The output of the NAND gate 16 is
The waveform is shown in FIG. 3l.

By blocking the clock pulse k, D
The type flip-flop 17 maintains the output level caused by the previous clock pulse k. The output level due to the previous clock pulse k is the output f of the first latch circuit 9 at a time when it is not affected by disturbance light.
The level corresponds to Therefore, the level of the detection signal m, which is the output of the D-type flip-flop 17, is maintained at the output level at the time when it is not affected by the disturbance light. If the output f of the first latch circuit 9 at the time when the disturbance light is not affected is different from the output f of the first latch circuit 9 at the time when the disturbance light is received, the output f of the first latch circuit 9 when the disturbance light is not affected is different. By blocking the clock pulse k, the output portion f ₁ is avoided and no longer appears in the detection signal m, thereby eliminating the influence of disturbance light from the detection signal m.

<Effects of the Invention> As described above, according to the present invention, the signal portion due to disturbance light in the light reception signal at the light emission timing is excluded by the light reception signal at the non-light emission timing, and as a result, Malfunctions caused by ambient light can be reliably prevented.

Furthermore, since it does not use an integrating circuit as in the prior art, the response is fast and objects can be detected instantaneously. Furthermore, there is no need for a capacitor for integral operation, and the circuit configuration is extremely simple, consisting of a combination of a latch circuit and a level holding circuit, and the entire device can be integrated into an IC and miniaturized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
FIG. 3 is a block diagram of a synchronization detection circuit, FIG. 3 is a time chart for explaining the operation, FIG. 4 is a block diagram of a conventional pulse modulation type photodetector, and FIG. 5 is a time chart showing its operation. DESCRIPTION OF SYMBOLS 1... Pulse generation circuit, 2... Light emitting element drive circuit, 3... Light emitting element, 4... Light receiving element, 6... Judgment circuit, 7... Synchronization detection circuit, 9... First latch circuit, 10... ...Second latch circuit, 11...Level holding circuit, c...Light emission timing pulse, g...
Non-luminous timing pulse.

Claims (1)

[Claims] 1. Emitting pulse-modulated light from a light emitting element,
In a pulse modulation type photodetector that detects the presence or absence of an object by receiving reflected light or transmitted light from the object to be detected by a light receiving element, a digitized light reception signal is sent to the light emitting element to emit light every light emitting cycle. A first latch circuit that latches at timing, a second latch circuit that latches the digitized light reception signal every cycle at the timing when the light emitting element is not emitting light, and the output of the first latch circuit are introduced. The detection output corresponding to this is inputted and held in synchronization with the clock every cycle, and when the output of the second latch circuit indicates light reception at a non-emission timing, the above-mentioned data is inputted in response to the output of the second latch circuit. What is claimed is: 1. A pulse modulation type photodetection device comprising: a level holding circuit that blocks a clock at the time of input;