JPH0454020A - Digital/analog converter - Google Patents

Abstract

PURPOSE:To form a D/A converter which can responds to a digital signal at high speed with high accuracy by providing a delay means delaying either a 1st input signal or a 2nd input signal to the D/A converter for a prescribed time so as to reduce glitch included in an output signal. CONSTITUTION:The D/A converter is provided with a delay means 3 delaying either a 1st input signal Din1 or a 2nd input signal Din2 for a prescribed time. Then the 1st input signal Din1 inputted to a control terminal of one transistor(TR) 1 being the component of a current switch is delayed by the delay means 3 for a prescribed time. Thus, just after the switching of the level of the 1st input signal Din1 is started, the signal level is switched at a signal level at which the level intersects the 2nd input signal Din2 and the current switch is easily operated. As a result, glitch included in the output signal is reduced markedly and the response characteristic of the output signal with a fast speed and high accuracy is ensured.

Description

[Detailed Description of the Invention] [Table of Contents] Overview of the Prior Art (Figs. 12 to 15) Problems to be Solved by the Invention (Figs. 16 and 17) Examples of Means and Actions for Solving the Problems ( a) One embodiment of the present invention (FIGS. 3 and 4) (b) Other embodiments of the present invention (FIGS. 5 and 6) (c) Other embodiments of the present invention (FIG. 7) ~Figure 9) (d) Other embodiments of the present invention (Figures 10 and 11) Effects of the invention [Summary] Regarding a digital-to-analog converter that converts a digital signal into an analog signal, in particular, the output analog signal is Regarding digital-to-analog converters that respond to input digital signals at high speed and with high accuracy, the purpose of this invention is to provide a D/A converter that responds at high speed and with high accuracy by minimizing glitches contained in output signals. a first transistor connected between the first power source and the second power source; and a second transistor connected between the output terminal and the second power source, the first and second transistors A digital-to-analog converter that outputs an analog value output signal from the output terminal based on first and second input signals, at least one of which is a digital value, input to a control terminal of the converter. It is provided with a delay means for delaying one of the signals for a predetermined period of time.

[Industrial Field of Application] The present invention relates to a digital-to-analog converter that converts a digital signal to an analog signal, and more particularly to a digital-to-analog converter in which an output analog signal responds quickly and accurately to an input digital signal.

In recent years, various devices such as image processing devices and electron beam exposure devices are required to perform signal processing at higher speeds or with higher precision.

In these various devices, a digital-to-analog converter (hereinafter referred to as a D/A converter) is used to convert a digital signal input as a control signal into an analog signal. Therefore, it is necessary to perform the conversion operation of the current switch constituting this D/A converter at high speed and with high precision.

[Conventional technology]

Conventionally, this type of D/A converter is shown in Figures 12 to 1.
There was one shown in Figure 5. These FIGS. 12 and 14 are configuration diagrams of each conventional D/A converter, and FIGS. 13 and 15.
The figure shows operation timing charts corresponding to the circuits shown in FIGS. 12 and 14, respectively.

The conventional D/A converter shown in FIG. 12 has the drain side connected to the ground side GND or the output end. Connect to llll,
A pair of MOS FETs with each source side commonly connected
Current +I consisting of T T "2 switch 10 and the pair of MOS FETs T,
.

MOS FET T as a buffer transistor whose drain side is connected to the common connection point of Tr2.

and the source side of the MO3FET T and the power supply terminal V
5. The constant voltage v from the constant voltage circuit 6 is connected between
This configuration includes a constant current source circuit 20 that controls the current from the power supply terminal v3s to a constant current based on No. 6.

Next, the operation of a conventional D/A converter based on the above configuration will be explained with reference to FIG.

First, the constant current source circuit 20 draws a constant current based on the constant voltage v6 from the constant voltage circuit 6, and the input terminal Di
MOSFET T is turned on based on the input of n3.

This MOS FET T is a current switch 10
Suppresses current output vibration when switching.

In this state, the MO at the current switch 10
The input signal vixl is input to the gate side of the S FET T through the input terminal D, and the MOS
An input signal 1l12 having a constant voltage value is input to the gate side of the FET T through the input terminal Din2. Based on these input signals v1 and vil12, each MO3FET T,..., Tr2 is driven to
The current flowing to the emitter of S FET TI2 is output from the output terminal I as a signal for a predetermined current value! oat
ou
Output t. This output signal (2) is an analog signal whose amplitude is the current value (Io~!1) controlled by the constant current source circuit wt20.

The other conventional D/A converter shown in FIG. 14 includes a current switch 10, MOS FET T+3, a constant current source circuit 20, and a constant voltage circuit 6, similar to the conventional D/A converter shown in FIG. 12. In addition to this configuration, a MOS FET in the current switch 10
A differential signal Q (or Q) is applied to each gate terminal of T, 1, and T12 as a digital signal DIl! and strobe signal D1
．． This configuration includes a differential signal generation circuit 1 that outputs an output based on 2.

Next, the operation of another D/A converter based on the above configuration will be explained based on FIG. 15. First, a digital signal Dinl and a strobe signal DI112, each having a predetermined digital value, are input to the differential signal generation circuit 1, which generates a differential signal QSQ.

These differential signals Q and Q are input to the current switch 10, and the MOSFET of this current switch is
, t, T, and 2 are each driven to output an output signal (■) from the output terminal D.

[Problem to be solved by the invention]

Since each conventional D/A converter is configured as described above, MOS FET T, , (or T, 2
) is the gate input of the digital value input signal DIIl.
When l (or Dia2) fluctuates in rising and falling as shown in the input signal waveform (dashed line portion) in FIGS. 13 and 15, the output signal shown in the dashed line in FIGS. 13 and 15 ■ There will also be fluctuations in the rising and falling o1 timings.

When a plurality of current switches that output the output signal I having fluctuations are arranged in parallel, a large glitch will occur in the output signal I as shown in FIGS. The problem was that digital-to-analog conversion was not possible.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a D/A converter that responds at high speed and with high accuracy by minimizing glitches contained in an output signal.

[Means to solve the problem]

FIG. 1 shows a diagram explaining the principle of the first invention.

In the figure, the D/A converter according to the first invention is
A first transistor (T, 1) connected between a first power source and a second power source; and a second transistor (Tr2) connected between an output terminal (Iout) and the second power source. ), at least one of which is input to the control terminals tl' +2 of the first and second transistors (TT) is a digital value;
In a digital-to-analog converter that outputs an analog value output signal from the output terminal (Iout) based on a second input signal (D, , Di12), the first and second input signals (Dial, DI112)
) delaying means (3) for delaying either one for a predetermined period of time.
It is equipped with the following.

Moreover, FIG. 2 shows a diagram explaining the principle of the second invention.

In the figure, the D/A converter according to the second invention is
a first transistor (Tr1) connected between a first power source and a second power source; a w second transistor (TB) connected between an output terminal (Iout) and the second power source; , at least one of which is input to the control terminals r1 and r2 of the first and second transistors (TT) is a digital value;
In a digital-to-analog converter that outputs an analog value output signal from the output terminal (Iout) based on a second input signal (D, 1, Dlfi2), the first input signal (Dial) delay means (3) for delaying the second input signal (D,
) to the first input signal (Dll, ) during the delay time by the delay means 2 (3).
signal adjustment means (5) for adjusting the signal level to approach the signal level of
).

[Effect]

In the first aspect of the present invention, the first
By delaying the input signal D by the delay means 3 for a certain period of time, the first input signal D
Immediately after +ol starts switching the signal level, +ol crosses the second input signal D1112, and the signal level is switched at a signal level at which the current switch can easily operate, thereby reducing glitches included in the output signal as much as possible. Ensure high-speed and highly accurate output signal response characteristics.

In the second aspect of the present invention, the first
The input signal Dial is delayed by a predetermined delay time by the delay means 3, and the signal level of the second input signal "n2 is brought close to the signal level of the first input signal D1, 1 at the predetermined delay time by the signal adjustment means 5. After the predetermined delay time elapses, the first input signal Di
The signal level is switched at a signal level that is easier to operate by crossing the second input signal 2, which has made a close transition immediately after the signal level switching starts, and the glitch included in the output signal is reduced as much as possible. This improves the response characteristics of high-speed and highly accurate output signals.

〔Example〕

(a) An embodiment of the first invention The following describes a case in which an embodiment of the first invention is configured as a 1-bit D/A converter with reference to FIGS. 3 and 4. FIG. 3 shows a circuit configuration diagram of this embodiment, and FIG. 4 shows an operation timing chart of this embodiment.

In each of the above figures, the D/A converter according to this embodiment is
Similar to the prior art, the present invention has a configuration including a differential signal generation circuit 1, a current switch 10, a MOS FET constant voltage circuit 6, and a constant current source circuit 20, and in addition to this configuration, the differential signal generation circuit The configuration includes a delay circuit 3 that delays the differential signal Q output from MOSFET T by a delay time τ and outputs this delayed differential signal Q1 to the gate side of MOSFET T.

Next, the operation of the A/A converter of this embodiment based on the above configuration will be explained. As a premise of converter operation, M
An appropriate constant voltage is applied to the gate of the OS FET T to suppress vibrations in the current value when the current switch 10 is switched. Further, the constant voltage circuit 6 generates a highly accurate constant voltage Vε and outputs it to the constant current source circuit 20. This constant current source circuit 20 includes an OP amplifier 7 and a MOS FET.
It is composed of T, 4 and a resistor R, and acts as a constant current source that supplies a constant current based on the constant voltage v6.

This constant current value I is (v - v)/R1.

In this state, the differential signal generation circuit 1 generates the differential signals Q, Q at the "H" (■) level and the "L" (v2) level based on the digital data and the strobe signal.The differential signal Q is input to the delay circuit 3, which delays the differential signal Q by a delay time τ and inputs the delayed differential signal Q1 to the gate of the MOS FET T. remains as MOS
FET T.

input into the gate.

The case where the delayed differential signal vQl and the differential signal Q are respectively inputted will be sequentially explained from time t to time t6 in FIG. 4. At this time t1, the differential signal Q is at the "H" level and the delayed differential signal vQ1 is at the "L" level, so the MOS FETs T, , of the current switch 10 are turned off, and the MOSFET T is turned on. In this state, the output current 1 = (V
-V7) 10ut o
wl 6R1 is drawn in.

At time t2 in the figure, the differential signal Q changes from “H” level to “
At the same time as starting the transition to L rubel, the delayed differential signal vQ
1 starts the delay and maintains the "L" level.

Furthermore, at time t3 in the figure, the delayed differential signal vQl is “L”.
The transition from “level” to “H” level starts, and at time t, delayed differential signal vQ1 and differential signal Q intersect and each MO
The gate voltages of the 8FETs T, . . . Tt2 become equal.

At time t5 in the figure, the differential signal Q completes the transition to the "L" level, and furthermore, at time t6, the delayed differential signal Q1 also changes to "L".
The transition to H'' level is completed, the MOS FETs T,, of the current switch 10 are turned on, the MOS FET Tr2 is turned off, and the current value of the output at signal l from the output terminal I becomes zero.

o+rl In this way, the signal levels of the differential signal Q are brought close to each other at the start of the transition of the delayed differential signal vQ1, so even if the signal level changes as shown by the chain line in Figure 4, the fluctuation of the output signal ■ can be reduced. This means that the occurrence of glitches can be suppressed.

(b) Second embodiment of the present invention FIG. 5 shows an embodiment of the second invention.

In the figure, the D/A converter according to the present embodiment includes a differential signal generation circuit 1, a delay circuit 3, a current switch 10, an M
The configuration includes an OS FET T constant current r3ゝ pressure circuit 6 and a constant current source circuit 20, and in addition to this configuration, the maximum value v3 of the differential signal Q output from the differential signal generating circuit 1 is used as a delayed differential signal. Maximum value of vQl■
At the same time, the minimum value (4) of the differential signal Q is adjusted to a value that is thicker than (and extremely close to) the minimum value (2) of the delayed differential signal Ql, and the adjusted differential signal vQ2 is the MOS FE of the current switch 10
It is provided with a level/gain adjustment circuit 5 that inputs input to the gate of T.

Next, the operation of this embodiment based on the above configuration will be explained. First, similar to the first invention, a MOS FET
T and the constant current source circuit 20 are operated to obtain a prerequisite state for converter operation.

In the above state, the differential signal Q outputted from the differential signal generation circuit 1 is outputted by the delay circuit 3 as a delayed differential signal Ql to the gates of the MOS FETs T, . Further, the differential signal Q is input to the level/gain adjustment circuit 5 and the level (and gain) is adjusted.

Furthermore, the delayed differential signal vQ1 and the adjusted differential signal VQ2
will be sequentially explained from time t to time t6 with reference to FIG. 6. At this time point 1, the adjusted differential signal (■) adjusted in the previous cycle is at the "H" level and the delayed differential signal vQI is at the "L" level, so that the MOS FETs T, , of the current switch 10 are
is in a cut-off state, and MOS FET T is in a turned-on state.

In this state, the output signal i −t = (V60I
I electric owl ■)
/ The current value of R+ is drawn in and output as a signal.

At time t in the figure, the adjusted differential signal VQ2 is “H” (V
) level to "t," (v4) level, and the delayed differential signal vQl starts to delay and goes to "L".
(v2) Maintain the level state.

Further, at time t22, each r1 of the MOS FET T T is brought close to the "L" (v4) level of the differential signal V adjusted by the level/gain adjustment circuit 5.
2. A state that is easy to switch between on and off will be prepared.

Also, at time t, the delay time τ of the delayed differential signal Ql has elapsed and the level changes from "L" (v2) to "H" (V,
level, and immediately after the start of this transition, L” (V
) Level adjustment differential signal ■Cross with Q2 and MOS
The on/off state of FET T T will be switched.

Further, at time t6, the MO8FET T,1 changes from the cut-off state to the turn-on state, and the MO8FET T,1 changes from the cut-off state to the turn-on state, and
The FET T changes from the turn-on state to the cut-off state, and the current value of the output signal I from the output terminal I at becomes zero. Sunawa+Il
l At this point, the output signal! will be switched as data.

Note that the above output signal ■ is output from the OIl family at time t8. When set, it becomes .

In this way, by delaying the differential signal Q in the delay circuit 3 and adjusting the differential signal Q in the level/gain adjustment circuit 5, the delayed differential signal VQI and the adjusted differential signal vQ2 are
Based on this, it is possible to turn on/off the MOS FETTT earlier than the operation start time +I'2, thereby greatly reducing the fluctuation of the output signal I that changes as shown by the chain line in Figure 6. This makes it possible to suppress the occurrence of glitches.

Further, the response speed can be adjusted by adjusting the differential signal Q using the adjustment circuit 5.

In FIG. 6, the signal level of the adjusted differential signal vQ2 is changed between time t2 and t4, and the current switch 10
is in a state where it is easy to switch.

That is, during this period, even a 16-bit D/A converter can only compensate for low accuracy (for example, 12 bits). However, this effect can be ignored if the period from time t2 to t4 is short in proportion to the period of one cycle (the period from time t2 to t2). The period from time t 1 to t4 can occur in several n5 ecs.

On the other hand, in an actual D/A converter, current switch 1
Even if there is a glitch of 1 to 2 osec in 0, the glitch of 10 to 15 n5ec is generated at the output of the D/A converter. If a slow amplifier is connected after the D/A converter, the effects of glitches will be even more severe.

Therefore, the effect of removing glitches is greater, and overall a faster and more accurate D/A converter is possible.

(C) Another embodiment of the second invention FIG. 7 shows another embodiment in which the second invention is a multi-bit D/A converter, in which the upper 3 bits of the plurality of bits are It shows.

In the figure, the D/A converters according to other embodiments include a converter 100 for the first upper bit, a converter 200 for the second upper bit, and a converter 20 for the third bit.
0 and... are connected in parallel, and delay circuits 31, 32 are generated based on the differential signals Q, Q,...
．． 33... and level/gain adjustment circuits 51, 52.
53,... through the current switch 11.12.1
3, . . . and the current switch 11.
12.13, . . . based on the drive of the output terminals I to ut which are commonly connected.

ut The current switch 11 of the most significant bit is the delay circuit 3
1 and the level/gain adjustment circuit 51, respectively, to achieve high-speed and high-precision switching. Further, the timing and level of the second bit current switch 12 are adjusted by adjusting the delay circuit 32 and the level/gain adjustment circuit 52 respectively so that the switching time difference with respect to the current switch 11 is minimized. . Further, the third bit current switch 13 is the current switch 1
The delay circuit 33 and the level/gain adjustment circuit 53 are each adjusted so that the switching time difference is minimized with respect to 1.12.

Note that in the case of a 16-bit D/A converter, the upper 4
The on/off characteristics of the ~5-bit current switch greatly affect the glitch characteristics. Other examples include the top 4
It is sufficient to apply up to 5 bits. Therefore, the lower bits may be used in other embodiments or in the configuration shown in the conventional art.

FIG. 8 shows the power output characteristics of this other embodiment.

In the figure, it can be seen that the glitch is smaller than the glitch generation principle. Therefore, as shown in FIG. 9, the staircase wave output characteristics also settle quickly.

(d) Other embodiments of the first and second inventions FIG. 10 shows other embodiments of the first and second inventions.

In addition to the configuration of the embodiment described above, another embodiment in the same figure changes the signal level in the direction opposite to the signal level transition direction of the converted digital signal Q2 based on the converted digital signal Q2 output from the level conversion circuit 2. It is equipped with a pulse generation circuit 4 that generates pulses of varying predetermined amplitude, and the pulses generated by the pulse generation circuit 4 are directly transmitted to the current source 1.
This is a configuration in which the voltage is applied to the gate of the MOS FET T at 0.

Further, the generated pulse is adjusted in level or gain via a level/gain adjustment circuit 5, and then outputted to the MOS FET.
It is also possible to adopt a configuration in which the voltage is applied to the gate of T.

Another embodiment based on the above configuration is as shown in FIG.
By always causing the generated pulse serving as the reference voltage to make a transition close to the signal level of the delayed converted digital signal Q3, the switching response speed of the current switch 10 can be made faster and more accurate.

In each of the above embodiments, the current switch etc.
Although it is constructed using an OS FET, it can also be constructed using a transistor such as a bipolar transistor, bi-MOS (bipolar MO8), or a switching element.

〔Effect of the invention〕

As described above, in the first aspect of the present invention, the first input signal DIfi1 input to the control terminal of one transistor Trl forming the current switch is delayed for a predetermined time by the delay means. Immediately after the input signal Dill starts switching the signal level, the second
The input signal of 2 is cut sideways, and the signal level is switched at a signal level at which the current switch can easily operate, thereby minimizing glitches in the output signal and achieving high-speed and high-precision response characteristics of the output signal. This has the effect of ensuring that

Further, in the second aspect of the present invention, the first input signal D input to the control terminal of one transistor Tll forming the current switch is delayed by a predetermined delay time by the delay means 3, and the second input signal Dia2 is The signal level of the first input signal Di111 is adjusted by the signal adjusting means 5 so as to approach the signal level of the first input signal Di111 at the predetermined delay time.

After the predetermined delay time has elapsed, the first input signal D111 crosses the second input signal D1.2 which made a close transition immediately after the signal level switching started, and the signal level is switched at a signal level that is easier to operate. This has the effect of reducing glitches included in the output signal as much as possible and improving the response characteristics of the output signal at high speed and with high accuracy.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the first invention, FIG. 2 is a diagram explaining the principle of the second invention, FIG. 3 is a circuit configuration diagram of an embodiment of the first invention, and FIG. 4 is a diagram explaining the principle of the second invention. 3 is an operation timing chart of the embodiment described in FIG. 5, FIG. 5 is a circuit configuration diagram of an embodiment of the second invention, FIG. 6 is an operation timing chart of the embodiment described in FIG. 5, and FIG. 7 is a diagram of the second embodiment of the present invention. 8 is a current output characteristic diagram of the embodiment shown in FIG. 7, FIG. 9 is an input digital signal-output analog signal characteristic diagram of the embodiment shown in FIG. 7, and FIG. 10 is a circuit diagram of another embodiment of the invention. 11 is an operation timing chart of the embodiment shown in FIG. 10; FIG. 12 is a circuit diagram of a conventional D/A converter; 13. 12 is an operation timing chart of the D/A converter shown in FIG. 12, FIG. 14 is a circuit configuration diagram of another conventional D/A converter, and FIG. 15 is an operation timing chart of the D/A converter shown in FIG. 14. , FIG. 16 is an operation timing chart of the prior art when three current switches are provided, and FIG. 17 is an input digital signal-output analog signal characteristic diagram when a plurality of current switches are provided. 1... Differential signal generation circuit 2... Level conversion circuit 3.31, 32.33, ~... Delay circuit 4... Pulse generation circuit 5.51, 52.53, ~... Level Gain adjustment circuit 6.61.62.63, ~... constant voltage circuit 7.71.
72.73, ~... op amp 10.11.12.1
3.～・・・Current switch T T
T -T S T -T "shi "2ゝ +ll +13 +2
1 +23・MOS FET

Claims (1)

[Claims] 1. A first transistor (T_r_1) connected between a first power supply and a second power supply, and an output terminal (I_o_u_
t) and a second transistor (T_r_2) connected between the first and second transistors (T_r_1, T_r_2), and at least one of the control terminals of the first and second transistors (T_r_1, T_r_2) is a digital 1st, 2nd value
In a digital-to-analog converter that outputs an analog value output signal from the output terminal (I_o_u_t) based on input signals (D_i_n_1, D_i_n_2) of the first and second input signals (D_i_n_1, D_i_n_
A digital-to-analog converter comprising a delay means (3) for delaying either one of (n_2) for a predetermined period of time. 2. The first transistor (T_r_1) connected between the first power supply and the second power supply, and the output terminal (I_o_u_
a second transistor (T_r_2) connected between the first and second transistors (T_r_1, T_r_2), and at least one of the control terminals of the first and second transistors (T_r_1, T_r_2) has a digital value. A digital-to-analog converter that outputs an analog value output signal from the output terminal (I_o_u_t) based on the first and second input signals (D_i_n_1, D_i_n_2) of the converter, the first input signal (D_i_n_1) is a delay means (3) for delaying; and the delay means (3) adjusts the signal level of the second input signal (D_i_n_2) to approach the signal level of the first input signal (D_i_n_1) during the delay time. A digital-to-analog converter comprising signal conditioning means (5). 3. In the digital-to-analog converter according to claim 2, the signal adjusting means (5) adjusts the first input signal (D_i_n
_1) is a signal that changes between two signal levels, and the second input signal (D_i_n_2) is a signal that normally has a constant value level between the two signal levels of the first input signal (D_i_n_1); , the first input signal (
A digital-to-analog converter characterized in that, during a delay time of D_i_n_1), the signal level of the second input signal (D_i_n_2) is brought into close transition to the signal level of the first input signal (D_i_n_1) during the delay time. 4. The digital-to-analog converter according to claim 1, wherein the first and second transistors (T_r_1, T_r
_2) A digital-to-analog converter comprising a plurality of current switches formed as a pair connected in parallel, and outputting the sum of outputs of each current switch as an output signal.